sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34
  35
  36 #if 1
  37 #define DBG(x...) printk(KERN_INFO x)
  38 #else
  39 #define DBG(x...) do { } while (0)
  40 #endif
  41
  42 #define WM8994_TEST
  43
  44 struct i2c_client *wm8994_client;
  45 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  46 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  47
  48 enum wm8994_codec_mode
  49 {
  50   wm8994_AP_to_Headset,
  51   wm8994_AP_to_Speakers,
  52   wm8994_Recorder,
  53   wm8994_FM_to_Headset,
  54   wm8994_FM_to_Headset_and_Record,
  55   wm8994_FM_to_Speakers,
  56   wm8994_FM_to_Speakers_and_Record,
  57   wm8994_HandsetMIC_to_Baseband_to_Headset,
  58   wm8994_HandsetMIC_to_Baseband_to_Headset_and_Record,
  59   wm8994_MainMIC_to_Baseband_to_Earpiece,
  60   wm8994_MainMIC_to_Baseband_to_Earpiece_and_Record,
  61   wm8994_MainMIC_to_Baseband_to_Speakers,
  62   wm8994_MainMIC_to_Baseband_to_Speakers_and_Record,
  63   wm8994_BT_Baseband,
  64   wm8994_BT_Baseband_and_record,
  65 ///PCM BB BEGIN
  66   wm8994_HandsetMIC_to_PCMBaseband_to_Headset,
  67   wm8994_HandsetMIC_to_PCMBaseband_to_Headset_and_Record,
  68   wm8994_MainMIC_to_PCMBaseband_to_Earpiece,
  69   wm8994_MainMIC_to_PCMBaseband_to_Earpiece_and_Record,
  70   wm8994_MainMIC_to_PCMBaseband_to_Speakers,
  71   wm8994_MainMIC_to_PCMBaseband_to_Speakers_and_Record,
  72   wm8994_BT_PCMBaseband,
  73   wm8994_BT_PCMBaseband_and_record,
  74 ///PCM BB END
  75   null
  76 };
  77
  78 unsigned char wm8994_mode=null;
  79
  80 /* For voice device route set, add by phc  */
  81 enum VoiceDeviceSwitch
  82 {
  83         SPEAKER_INCALL,
  84         SPEAKER_NORMAL,
  85
  86         HEADSET_INCALL,
  87         HEADSET_NORMAL,
  88
  89         EARPIECE_INCALL,
  90         EARPIECE_NORMAL,
  91
  92         BLUETOOTH_SCO_INCALL,
  93         BLUETOOTH_SCO_NORMAL,
  94
  95         BLUETOOTH_A2DP_INCALL,
  96         BLUETOOTH_A2DP_NORMAL,
  97
  98         MIC_CAPTURE,
  99
 100         ALL_OPEN,
 101         ALL_CLOSED
 102 };
 103 /*
 104  * wm8994 register cache
 105  * We can't read the WM8994 register space when we
 106  * are using 2 wire for device control, so we cache them instead.
 107  */
 108 static const u16 wm8994_reg[] = {
 109         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 110         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 111         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 112         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 113         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 114         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 115         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 116         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 117         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 118         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 119         0x0079, 0x0079, 0x0079,          /* 40 */
 120 };
 121
 122 /* codec private data */
 123 struct wm8994_priv {
 124         unsigned int sysclk;
 125         struct snd_soc_codec codec;
 126         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 127         u16 reg_cache[WM8994_NUM_REG];
 128 };
 129
 130 static int wm8994_read(unsigned short reg,unsigned short *value)
 131 {
 132         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 133
 134         if (reg_recv_data(wm8994_client,&regs,&values,400000) >= 0)
 135         {
 136                 *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 137                 DBG("Enter::%s----line->%d--reg=0x%x value=%x\n",__FUNCTION__,__LINE__,reg,*value);
 138                 return 0;
 139         }
 140         printk("%s---line->%d:Codec read error!\n",__FUNCTION__,__LINE__);
 141         return -EIO;
 142 }
 143
 144
 145 static int wm8994_write(unsigned short reg,unsigned short value)
 146 {
 147         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 148
 149         DBG("Enter::%s----line->%d-- reg=%x--value=%x -- regs=%x--values=%x\n",__FUNCTION__,__LINE__,reg,value,regs,values);
 150
 151         if (reg_send_data(wm8994_client,&regs,&values,400000)>=0)
 152                 return 0;
 153
 154         printk("%s---line->%d:Codec write error!\n",__FUNCTION__,__LINE__);
 155         return -EIO;
 156 }
 157
 158 #define wm8994_reset()  wm8994_write(WM8994_RESET, 0)
 159
 160 void  AP_to_Headset(void)
 161 {
 162         DBG("Enter::%s----line->%d-- AP_to_Headset\n",__FUNCTION__,__LINE__);
 163         wm8994_mode=wm8994_AP_to_Headset;
 164         wm8994_reset();
 165         mdelay(50);
 166
 167 #if 1
 168         wm8994_write(0x01,  0x0003);
 169         mdelay(50);
 170         wm8994_write(0x221, 0x0700);
 171         wm8994_write(0x222, 0x90C2);  //86C2
 172         wm8994_write(0x223, 0x00E0);
 173
 174 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 175         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 176         wm8994_write(0x303, 0x0050);  // master  0x0050 lrck 40.98kHz bclk 2.15MHz
 177         wm8994_write(0x305, 0x0035);  // master  0x0035 lrck 40.98kHz bclk 2.15MHz
 178 #endif
 179
 180         wm8994_write(0x220, 0x0005);
 181         mdelay(50);
 182         wm8994_write(0x200, 0x0001);  // sysclk = fll (bit4 =1)   0x0011
 183         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 184
 185         wm8994_write(0x01,  0x0303);
 186         wm8994_write(0x05,  0x0303);
 187         wm8994_write(0x2D,  0x0100);
 188         wm8994_write(0x2E,  0x0100);
 189         wm8994_write(0x4C,  0x9F25);
 190         wm8994_write(0x60,  0x00EE);
 191         wm8994_write(0x208, 0x000A);
 192         wm8994_write(0x420, 0x0000);
 193         wm8994_write(0x601, 0x0001);
 194         wm8994_write(0x602, 0x0001);
 195
 196         wm8994_write(0x610, 0x0190);  //DAC1 Left Volume bit0~7
 197         wm8994_write(0x611, 0x0190);  //DAC1 Right Volume bit0~7
 198         wm8994_write(0x03,  0x0300);
 199         wm8994_write(0x22,  0x0000);
 200         wm8994_write(0x23,  0x0100);
 201         wm8994_write(0x36,  0x0003);
 202
 203 #endif
 204 #if 0
 205         wm8994_write(0x01,  0x0003);
 206         mdelay(50);
 207         wm8994_write(0x221, 0x0700);
 208         wm8994_write(0x222, 0x3127);
 209         wm8994_write(0x223, 0x0100);
 210         wm8994_write(0x220, 0x0004);
 211         mdelay(50);
 212         wm8994_write(0x220, 0x0005);
 213
 214         wm8994_write(0x01,  0x0303);  // sysclk = fll (bit4 =1)   0x0011
 215         wm8994_write(0x05,  0x0303);  // i2s 16 bits
 216
 217         wm8994_write(0x2D,  0x0100);
 218         wm8994_write(0x2E,  0x0100);
 219         wm8994_write(0x4C,  0x9F25);
 220         wm8994_write(0x60,  0x00EE);
 221         wm8994_write(0x200, 0x0011);
 222         wm8994_write(0x208, 0x000A);
 223         wm8994_write(0x601, 0x0001);
 224         wm8994_write(0x602, 0x0001);
 225
 226         wm8994_write(0x610, 0x01C0);
 227         wm8994_write(0x611, 0x01C0);
 228         wm8994_write(0x420, 0x0000);
 229 #endif
 230
 231 }
 232
 233 void  AP_to_Speakers(void)
 234 {
 235         DBG("Enter::%s----line->%d-- AP_to_Speakers\n",__FUNCTION__,__LINE__);
 236         wm8994_mode=wm8994_AP_to_Speakers;
 237         wm8994_reset();
 238         mdelay(50);
 239
 240 #if 1  // codec slave
 241         wm8994_write(0x01,  0x0003);
 242         mdelay(50);
 243         wm8994_write(0x221, 0x0700);
 244         wm8994_write(0x222, 0x90C2);
 245         wm8994_write(0x223, 0x00E0);
 246
 247 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 248         wm8994_write(0x302, 0x4000);  // master = 0x4000  slave= 0x0000
 249         wm8994_write(0x303, 0x0050);  // master  0x0050 lrck 40.98kHz bclk 2.15MHz
 250         wm8994_write(0x305, 0x0035);  // master  0x0035 lrck 40.98kHz bclk 2.15MHz
 251 #endif
 252
 253         wm8994_write(0x220, 0x0005);
 254         mdelay(50);
 255         wm8994_write(0x200, 0x0001);  // sysclk = fll (bit4 =1)   0x0011
 256         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 257
 258         wm8994_write(0x01,  0x3003);
 259         wm8994_write(0x05,  0x0303);
 260         wm8994_write(0x2D,  0x0100);
 261         wm8994_write(0x2E,  0x0100);
 262         wm8994_write(0x4C,  0x9F25);
 263         wm8994_write(0x60,  0x00EE);
 264         wm8994_write(0x208, 0x000A);
 265         wm8994_write(0x420, 0x0000);
 266
 267         wm8994_write(0x601, 0x0001);
 268         wm8994_write(0x602, 0x0001);
 269
 270         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 271         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 272         wm8994_write(0x03,  0x0300);
 273         wm8994_write(0x22,  0x0000);
 274         wm8994_write(0x23,  0x0100);
 275         wm8994_write(0x36,  0x0003);
 276         mdelay(50);
 277 #endif
 278 #if 0
 279         wm8994_write(0x01,  0x0003);
 280         mdelay(50);
 281         wm8994_write(0x221, 0x0700);
 282         wm8994_write(0x222, 0x3127);
 283         wm8994_write(0x223, 0x0100);
 284         wm8994_write(0x220, 0x0004);
 285         mdelay(50);
 286         wm8994_write(0x220, 0x0005);
 287
 288         wm8994_write(0x01,  0x3003);  // sysclk = fll (bit4 =1)   0x0011
 289         wm8994_write(0x03,  0x0330);
 290         wm8994_write(0x05,  0x0303);  // i2s 16 bits
 291
 292         wm8994_write(0x22,  0x0000);
 293         wm8994_write(0x23,  0x0100);
 294         wm8994_write(0x2D,  0x0001);
 295         wm8994_write(0x2E,  0x0001);
 296 //      wm8994_write(0x4C,  0x9F25);
 297 //      wm8994_write(0x60,  0x00EE);
 298         wm8994_write(0x200, 0x0011);
 299         wm8994_write(0x208, 0x000A);
 300         wm8994_write(0x601, 0x0001);
 301         wm8994_write(0x602, 0x0001);
 302
 303         wm8994_write(0x610, 0x01C0);
 304         wm8994_write(0x611, 0x01C0);
 305         wm8994_write(0x620, 0x0000);
 306         wm8994_write(0x420, 0x0000);
 307 #endif
 308 }
 309
 310 void  Recorder(void)
 311 {
 312         DBG("Enter::%s----line->%d-- Recorder\n",__FUNCTION__,__LINE__);
 313         wm8994_mode=wm8994_Recorder;
 314         wm8994_reset();
 315         mdelay(50);
 316
 317         wm8994_write(0x01,   0x0013);
 318         mdelay(50);
 319         wm8994_write(0x221,  0x0D00);
 320         wm8994_write(0x222,  0x3300);
 321         wm8994_write(0x223,  0x00E0);
 322
 323 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 324         wm8994_write(0x302,  0x4000);  //master = 0x4000  slave= 0x0000
 325         wm8994_write(0x303,  0x0090);  //master  0x0090 lrck1 8kHz bclk1 515KHz
 326         wm8994_write(0x305,  0x00F0);  //master  0x00F0 lrck1 8kHz bclk1 515KHz
 327 #endif
 328
 329         wm8994_write(0x220,  0x0004);
 330         mdelay(50);
 331         wm8994_write(0x220,  0x0005);
 332
 333         wm8994_write(0x02,   0x6110);
 334         wm8994_write(0x04,   0x0303);
 335         wm8994_write(0x1A,   0x015F);  //volume
 336
 337         wm8994_write(0x28,   0x0003);
 338         wm8994_write(0x2A,   0x0020);
 339         wm8994_write(0x200,  0x0011);
 340         wm8994_write(0x208,  0x000A);
 341         wm8994_write(0x300,  0xC050);
 342         wm8994_write(0x606,  0x0002);
 343         wm8994_write(0x607,  0x0002);
 344         wm8994_write(0x620,  0x0000);
 345
 346 }
 347
 348 void  FM_to_Headset(void)
 349 {
 350         DBG("Enter::%s----line->%d-- FM_to_Headset\n",__FUNCTION__,__LINE__);
 351         wm8994_mode=wm8994_FM_to_Headset;
 352         wm8994_reset();
 353         mdelay(50);
 354
 355         wm8994_write(0x01,  0x0323);
 356         wm8994_write(0x02,  0x03A0);
 357         wm8994_write(0x03,  0x0030);
 358         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 359         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 360
 361         wm8994_write(0x28,  0x0044);
 362         wm8994_write(0x29,  0x0100);
 363         wm8994_write(0x2A,  0x0100);
 364         wm8994_write(0x2D,  0x0040);
 365         wm8994_write(0x2E,  0x0040);
 366         wm8994_write(0x4C,  0x9F25);
 367         wm8994_write(0x60,  0x00EE);
 368         wm8994_write(0x220, 0x0003);
 369         wm8994_write(0x221, 0x0700);
 370         wm8994_write(0x224, 0x0CC0);
 371         wm8994_write(0x200, 0x0011);
 372         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 373         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 374 }
 375
 376 void  FM_to_Headset_and_Record(void)
 377 {
 378         DBG("Enter::%s----line->%d-- FM_to_Headset_and_Record\n",__FUNCTION__,__LINE__);
 379         wm8994_mode=wm8994_FM_to_Headset_and_Record;
 380         wm8994_reset();
 381         mdelay(50);
 382
 383         wm8994_write(0x01,   0x0003);
 384         mdelay(50);
 385         wm8994_write(0x221,  0x1900);  //8~13BIT div
 386
 387 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 388         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 389         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 390 #endif
 391
 392         wm8994_write(0x220,  0x0004);
 393         mdelay(50);
 394         wm8994_write(0x220,  0x0005);
 395
 396         wm8994_write(0x01,   0x0323);
 397         wm8994_write(0x02,   0x03A0);
 398         wm8994_write(0x03,   0x0030);
 399         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 400         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 401
 402         wm8994_write(0x28,   0x0044);
 403         wm8994_write(0x29,   0x0100);
 404         wm8994_write(0x2A,   0x0100);
 405         wm8994_write(0x2D,   0x0040);
 406         wm8994_write(0x2E,   0x0040);
 407         wm8994_write(0x4C,   0x9F25);
 408         wm8994_write(0x60,   0x00EE);
 409         wm8994_write(0x200,  0x0011);
 410         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 411         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 412         wm8994_write(0x04,   0x0303);
 413         wm8994_write(0x208,  0x000A);
 414         wm8994_write(0x300,  0x4050);
 415         wm8994_write(0x606,  0x0002);
 416         wm8994_write(0x607,  0x0002);
 417         wm8994_write(0x620,  0x0000);
 418 }
 419
 420 void  FM_to_Speakers(void)
 421 {
 422         DBG("Enter::%s----line->%d-- FM_to_Speakers\n",__FUNCTION__,__LINE__);
 423         wm8994_mode=wm8994_FM_to_Speakers;
 424         wm8994_reset();
 425         mdelay(50);
 426
 427         wm8994_write(0x01,   0x3023);
 428         wm8994_write(0x02,   0x03A0);
 429         wm8994_write(0x03,   0x0330);
 430         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 431         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 432
 433         wm8994_write(0x22,   0x0000);
 434         wm8994_write(0x23,   0x0000);
 435         wm8994_write(0x36,   0x000C);
 436
 437         wm8994_write(0x28,   0x0044);
 438         wm8994_write(0x29,   0x0100);
 439         wm8994_write(0x2A,   0x0100);
 440         wm8994_write(0x2D,   0x0040);
 441         wm8994_write(0x2E,   0x0040);
 442 //      wm8994_write(0x4C,   0x9F25);
 443 //      wm8994_write(0x60,   0x00EE);
 444
 445         wm8994_write(0x220,  0x0003);
 446         wm8994_write(0x221,  0x0700);
 447         wm8994_write(0x224,  0x0CC0);
 448
 449         wm8994_write(0x200,  0x0011);
 450         wm8994_write(0x20,   0x01F9);
 451         wm8994_write(0x21,   0x01F9);
 452 }
 453
 454 void  FM_to_Speakers_and_Record(void)
 455 {
 456         DBG("Enter::%s----line->%d-- FM_to_Speakers_and_Record\n",__FUNCTION__,__LINE__);
 457         wm8994_mode=wm8994_FM_to_Speakers_and_Record;
 458         wm8994_reset();
 459         mdelay(50);
 460
 461         wm8994_write(0x01,   0x0003);
 462         mdelay(50);
 463
 464 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 465         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 466         wm8994_write(0x303,  0x0090);  //
 467 #endif
 468
 469         wm8994_write(0x220,  0x0006);
 470         mdelay(50);
 471
 472         wm8994_write(0x01,   0x3023);
 473         wm8994_write(0x02,   0x03A0);
 474         wm8994_write(0x03,   0x0330);
 475         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 476         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 477
 478         wm8994_write(0x22,   0x0000);
 479         wm8994_write(0x23,   0x0000);
 480         wm8994_write(0x36,   0x000C);
 481
 482         wm8994_write(0x28,   0x0044);
 483         wm8994_write(0x29,   0x0100);
 484         wm8994_write(0x2A,   0x0100);
 485         wm8994_write(0x2D,   0x0040);
 486         wm8994_write(0x2E,   0x0040);
 487 //      wm8994_write(0x4C,   0x9F25);
 488 //      wm8994_write(0x60,   0x00EE);
 489
 490         wm8994_write(0x220,  0x0003);
 491         wm8994_write(0x221,  0x0700);
 492         wm8994_write(0x224,  0x0CC0);
 493
 494         wm8994_write(0x200,  0x0011);
 495         wm8994_write(0x20,   0x01F9);
 496         wm8994_write(0x21,   0x01F9);
 497         wm8994_write(0x04,   0x0303);
 498         wm8994_write(0x208,  0x000A);
 499         wm8994_write(0x300,  0x4050);
 500         wm8994_write(0x606,  0x0002);
 501         wm8994_write(0x607,  0x0002);
 502         wm8994_write(0x620,  0x0000);
 503 }
 504
 505 void  HandsetMIC_to_Baseband_to_Headset(void)
 506 {
 507         DBG("Enter::%s----line->%d-- HandsetMIC_to_Baseband_to_Headset\n",__FUNCTION__,__LINE__);
 508         wm8994_mode=wm8994_HandsetMIC_to_Baseband_to_Headset;
 509         wm8994_reset();
 510         mdelay(50);
 511
 512         wm8994_write(0x01,  0x0323);
 513         wm8994_write(0x02,  0x6040);
 514         wm8994_write(0x03,  0x3030);
 515         wm8994_write(0x18,  0x014B);  //mic volume
 516         wm8994_write(0x1E,  0x0006);
 517         wm8994_write(0x28,  0x0030);
 518         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 519         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 520         wm8994_write(0x34,  0x0002);
 521         wm8994_write(0x4C,  0x9F25);
 522         wm8994_write(0x60,  0x00EE);
 523         wm8994_write(0x220, 0x0003);
 524         wm8994_write(0x221, 0x0700);
 525         wm8994_write(0x224, 0x0CC0);
 526
 527 //Note: free-running start first, then open AIF1 clock setting
 528         wm8994_write(0x200, 0x0011);
 529 //Note: 0x1C/0x1D=0x01FF-->bypass volume no gain/attenuation
 530         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 531         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 532 }
 533
 534 void  HandsetMIC_to_Baseband_to_Headset_and_Record(void)
 535 {
 536         DBG("Enter::%s----line->%d-- HandsetMIC_to_Baseband_to_Headset_and_Record\n",__FUNCTION__,__LINE__);
 537         wm8994_mode=wm8994_HandsetMIC_to_Baseband_to_Headset_and_Record;
 538         wm8994_reset();
 539         mdelay(50);
 540
 541         wm8994_write(0x01,  0x0323);
 542         wm8994_write(0x02,  0x62C0);
 543         wm8994_write(0x03,  0x3030);
 544         wm8994_write(0x04,  0x0303);
 545         wm8994_write(0x18,  0x014B);  //volume
 546         wm8994_write(0x19,  0x014B);  //volume
 547         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 548         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 549         wm8994_write(0x1E,  0x0006);
 550         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
 551         wm8994_write(0x29,  0x0120);
 552         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 553         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 554         wm8994_write(0x34,  0x0002);
 555         wm8994_write(0x4C,  0x9F25);
 556         wm8994_write(0x60,  0x00EE);
 557         wm8994_write(0x200, 0x0001);
 558         wm8994_write(0x208, 0x000A);
 559         wm8994_write(0x300, 0x0050);
 560
 561 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 562         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 563         wm8994_write(0x303, 0x0090);  // master lrck 16k
 564 #endif
 565
 566         wm8994_write(0x606, 0x0002);
 567         wm8994_write(0x607, 0x0002);
 568         wm8994_write(0x620, 0x0000);
 569
 570         wm8994_write(0x1C, 0x01F9);
 571         wm8994_write(0x1D, 0x01F9);
 572 }
 573
 574 void  MainMIC_to_Baseband_to_Earpiece(void)
 575 {
 576         DBG("Enter::%s----line->%d-- MainMIC_to_Baseband_to_Earpiece\n",__FUNCTION__,__LINE__);
 577         wm8994_mode=wm8994_MainMIC_to_Baseband_to_Earpiece;
 578         wm8994_reset();
 579         mdelay(50);
 580
 581         wm8994_write(0x01, 0x0813);
 582         wm8994_write(0x02, 0x6210);
 583         wm8994_write(0x03, 0x30A0);
 584         wm8994_write(0x1A, 0x015F);  //main mic volume
 585         wm8994_write(0x1E, 0x0006);
 586         wm8994_write(0x1F, 0x0000);
 587         wm8994_write(0x28, 0x0003);
 588         wm8994_write(0x2B, 0x0005);  //VRX_MIXINL_VOL
 589         wm8994_write(0x2D, 0x0040);
 590         wm8994_write(0x33, 0x0010);
 591         wm8994_write(0x34, 0x0004);
 592 }
 593
 594 void  MainMIC_to_Baseband_to_Earpiece_and_Record(void)
 595 {
 596         DBG("Enter::%s----line->%d-- MainMIC_to_Baseband_to_Earpiece_and_Record\n",__FUNCTION__,__LINE__);
 597         wm8994_mode=wm8994_MainMIC_to_Baseband_to_Earpiece_and_Record;
 598         wm8994_reset();
 599         mdelay(50);
 600
 601         wm8994_write(0x01  ,0x0813);
 602         wm8994_write(0x02  ,0x6310);
 603         wm8994_write(0x03  ,0x30A0);
 604         wm8994_write(0x04  ,0x0303);
 605         wm8994_write(0x1A  ,0x014F);
 606         wm8994_write(0x1E  ,0x0006);
 607         wm8994_write(0x1F  ,0x0000);
 608         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R  //
 609         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR   //
 610         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
 611         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
 612         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
 613         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
 614         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1 //
 615         wm8994_write(0x200 ,0x0001);
 616         wm8994_write(0x208 ,0x000A);
 617         wm8994_write(0x300 ,0xC050);
 618
 619 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 620         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 621         wm8994_write(0x303, 0x0090);  // master lrck 16k
 622 #endif
 623
 624         wm8994_write(0x606 ,0x0002);
 625         wm8994_write(0x607 ,0x0002);
 626         wm8994_write(0x620 ,0x0000);
 627 }
 628
 629 void  MainMIC_to_Baseband_to_Speakers(void)
 630 {
 631         DBG("Enter::%s----line->%d-- MainMIC_to_Baseband_to_Speakers\n",__FUNCTION__,__LINE__);
 632         wm8994_mode=wm8994_MainMIC_to_Baseband_to_Speakers;
 633         wm8994_reset();
 634         mdelay(50);
 635
 636 #if 1
 637         wm8994_write(0x01 ,0x3013);
 638         wm8994_write(0x02 ,0x6210);
 639         wm8994_write(0x03 ,0x3330);
 640         wm8994_write(0x1A ,0x015F);
 641         wm8994_write(0x1E ,0x0006);
 642         wm8994_write(0x22 ,0x0000);
 643         wm8994_write(0x23 ,0x0100);
 644         wm8994_write(0x26 ,0x017F);  //Speaker Volume Left bit 0~5
 645         wm8994_write(0x27 ,0x017F);  //Speaker Volume Right bit 0~5
 646         wm8994_write(0x28 ,0x0003);
 647         wm8994_write(0x2D ,0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 648         wm8994_write(0x2E ,0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 649         wm8994_write(0x34 ,0x0004);
 650         wm8994_write(0x36 ,0x000C);
 651 #endif
 652 }
 653
 654 void  MainMIC_to_Baseband_to_Speakers_and_Record(void)
 655 {
 656         DBG("Enter::%s----line->%d-- MainMIC_to_Baseband_to_Speakers_and_Record\n",__FUNCTION__,__LINE__);
 657         wm8994_mode=wm8994_MainMIC_to_Baseband_to_Speakers_and_Record;
 658         wm8994_reset();
 659         mdelay(50);
 660
 661         wm8994_write(0x01, 0x3013);
 662         wm8994_write(0x02, 0x6330);
 663         wm8994_write(0x03, 0x3330);
 664         wm8994_write(0x04, 0x0303);
 665         wm8994_write(0x1A, 0x014B);
 666         wm8994_write(0x1B, 0x014B);
 667         wm8994_write(0x1E, 0x0006);
 668         wm8994_write(0x22, 0x0000);
 669         wm8994_write(0x23, 0x0100);
 670         wm8994_write(0x28, 0x0007);
 671         wm8994_write(0x2A, 0x0120);
 672         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 673         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 674         wm8994_write(0x34, 0x0004);
 675         wm8994_write(0x36, 0x000C);
 676         wm8994_write(0x200, 0x0001);
 677         wm8994_write(0x208, 0x000A);
 678         wm8994_write(0x300, 0xC050);
 679
 680 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 681         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 682         wm8994_write(0x303, 0x0090);  // master lrck 16k
 683 #endif
 684
 685         wm8994_write(0x606, 0x0002);
 686         wm8994_write(0x607, 0x0002);
 687         wm8994_write(0x620, 0x0000);
 688
 689 }
 690
 691 void  BT_Baseband(void)
 692 {
 693         DBG("Enter::%s----line->%d-- BT_Baseband\n",__FUNCTION__,__LINE__);
 694         wm8994_mode=wm8994_BT_Baseband;
 695         wm8994_reset();
 696         mdelay(50);
 697 #if 1
 698         wm8994_write(0x01,  0x0003);
 699         mdelay(50);
 700         wm8994_write(0x221, 0x0700);
 701         wm8994_write(0x222, 0x3127);
 702         wm8994_write(0x223, 0x0100);
 703         wm8994_write(0x220, 0x0004);
 704         mdelay(50);
 705         wm8994_write(0x220, 0x0005);
 706
 707         wm8994_write(0x01,  0x0003);
 708         wm8994_write(0x03,  0x30F0);
 709         wm8994_write(0x05,  0x3003);
 710         wm8994_write(0x2D,  0x0001);
 711         wm8994_write(0x2E,  0x0001);
 712
 713         wm8994_write(0x200, 0x0001);
 714         wm8994_write(0x204, 0x0001);
 715         wm8994_write(0x208, 0x0007);
 716         wm8994_write(0x520, 0x0000);
 717         wm8994_write(0x601, 0x0004);
 718         wm8994_write(0x602, 0x0004);
 719         wm8994_write(0x610, 0x01C0);
 720         wm8994_write(0x611, 0x01C0);
 721         wm8994_write(0x613, 0x01C0);
 722
 723         wm8994_write(0x702, 0xC100);
 724         wm8994_write(0x703, 0xC100);
 725         wm8994_write(0x704, 0xC100);
 726         wm8994_write(0x706, 0x4100);
 727
 728         wm8994_write(0x204, 0x0011);  // AIF2 MCLK=FLL                            //MASTER
 729         wm8994_write(0x211, 0x0039);  //LRCK=8KHZ,Rate=MCLK/1536                         //MASTER
 730         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
 731
 732         wm8994_write(0x313, 0x00F0);
 733         wm8994_write(0x314, 0x0020);
 734         wm8994_write(0x315, 0x0020);
 735         wm8994_write(0x2B,  0x0005);
 736         wm8994_write(0x2C,  0x0005);
 737         wm8994_write(0x02,  0x6300);
 738         wm8994_write(0x04,  0x3003);
 739
 740         wm8994_write(0x1E,  0x0006);  //LINEOUT1N_MUTE(001Eh);
 741         wm8994_write(0x34,  0x0001);  //LINEOUT1_MODE=1;LINEOUT_VMID_BUF_ENA=1;
 742
 743         wm8994_write(0x603, 0x018C);
 744         wm8994_write(0x604, 0x0010);
 745         wm8994_write(0x605, 0x0010);
 746         wm8994_write(0x621, 0x0001);
 747         wm8994_write(0x317, 0x0003);
 748
 749 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 750         wm8994_write(0x312, 0x4000);  //set 0x312 PCM2 as Master
 751         wm8994_write(0x313, 0x0090);  //master   0x0090 lrck2 8kHz bclk2 1MH
 752         wm8994_write(0x315, 0x007D);  //master   0x007D lrck2 8kHz bclk2 1MH
 753 #endif
 754
 755 #endif
 756 #if 0
 757         wm8994_write(0x01 ,0x0003);
 758         wm8994_write(0x02 ,0x63A0);
 759         wm8994_write(0x03 ,0x30A0);
 760         wm8994_write(0x04 ,0x0303);
 761         wm8994_write(0x05 ,0x0202);
 762         wm8994_write(0x06 ,0x0001);
 763         wm8994_write(0x19 ,0x014B);
 764         wm8994_write(0x1B ,0x014B);
 765         wm8994_write(0x1E ,0x0006);
 766         wm8994_write(0x28 ,0x00CC);
 767         wm8994_write(0x29 ,0x0100);
 768         wm8994_write(0x2A ,0x0100);
 769         wm8994_write(0x2D ,0x0001);
 770         wm8994_write(0x34 ,0x0001);
 771         wm8994_write(0x200 ,0x0001);
 772         wm8994_write(0x208 ,0x000A);
 773 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 774         wm8994_write(0x302 ,0x7000);
 775 #endif
 776         wm8994_write(0x303, 0x0090);  //master   0x0090 lrck1 8kHz bclk1 1MH
 777         wm8994_write(0x305, 0x007D);  //master   0x007D lrck1 8kHz bclk1 1MH
 778
 779         wm8994_write(0x420 ,0x0000);
 780         wm8994_write(0x601 ,0x0001);
 781         wm8994_write(0x602 ,0x0001);
 782         wm8994_write(0x606 ,0x0002);
 783         wm8994_write(0x607 ,0x0002);
 784         wm8994_write(0x610 ,0x01C0);
 785         wm8994_write(0x611 ,0x01C0);
 786         wm8994_write(0x620 ,0x0000);
 787         wm8994_write(0x707 ,0xA100);
 788         wm8994_write(0x708 ,0x2100);
 789         wm8994_write(0x709 ,0x2100);
 790         wm8994_write(0x70A ,0x2100);
 791 #endif
 792 }
 793
 794 void  BT_Baseband_and_record(void)
 795 {
 796         DBG("Enter::%s----line->%d-- BT_Baseband_and_record\n",__FUNCTION__,__LINE__);
 797         wm8994_mode=wm8994_BT_Baseband_and_record;
 798         wm8994_reset();
 799         mdelay(50);
 800
 801         wm8994_write(0x01, 0x0003);
 802         wm8994_write(0x02, 0x63A0);
 803         wm8994_write(0x03, 0x30A0);
 804         wm8994_write(0x04, 0x3303);
 805         wm8994_write(0x05, 0x3002);
 806         wm8994_write(0x06, 0x000A);
 807         wm8994_write(0x19, 0x014B);
 808         wm8994_write(0x1B, 0x014B);
 809         wm8994_write(0x1E, 0x0006);
 810         wm8994_write(0x28, 0x00CC);
 811         wm8994_write(0x29, 0x0100);
 812         wm8994_write(0x2A, 0x0100);
 813         wm8994_write(0x2D, 0x0001);
 814         wm8994_write(0x34, 0x0001);
 815         wm8994_write(0x200, 0x0001);
 816         wm8994_write(0x204, 0x0001);
 817         wm8994_write(0x208, 0x000F);
 818
 819 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 820         wm8994_write(0x312, 0x7000);
 821         wm8994_write(0x313, 0x0090);  //master   0x0090 lrck2 8kHz bclk2 1MH
 822         wm8994_write(0x315, 0x007D);  //master   0x007D lrck2 8kHz bclk2 1MH
 823
 824         wm8994_write(0x302, 0x4000);
 825         wm8994_write(0x303, 0x0090);  //master
 826 #endif
 827
 828         wm8994_write(0x440, 0x0018);
 829         wm8994_write(0x450, 0x0018);
 830         wm8994_write(0x480, 0x0000);
 831         wm8994_write(0x481, 0x0000);
 832         wm8994_write(0x4A0, 0x0000);
 833         wm8994_write(0x4A1, 0x0000);
 834         wm8994_write(0x520, 0x0000);
 835         wm8994_write(0x540, 0x0018);
 836         wm8994_write(0x580, 0x0000);
 837         wm8994_write(0x581, 0x0000);
 838         wm8994_write(0x601, 0x0004);
 839         wm8994_write(0x603, 0x000C);
 840         wm8994_write(0x604, 0x0010);
 841         wm8994_write(0x605, 0x0010);
 842         wm8994_write(0x606, 0x0003);
 843         wm8994_write(0x607, 0x0003);
 844         wm8994_write(0x610, 0x01C0);
 845         wm8994_write(0x612, 0x01C0);
 846         wm8994_write(0x613, 0x01C0);
 847         wm8994_write(0x620, 0x0000);
 848         wm8994_write(0x704, 0xA100);
 849         wm8994_write(0x707, 0xA100);
 850         wm8994_write(0x708, 0x2100);
 851         wm8994_write(0x709, 0x2100);
 852         wm8994_write(0x70A, 0x2100);
 853 }
 854
 855
 856 ///PCM BB BEGIN////////////////////////////////////
 857
 858 void  HandsetMIC_to_PCMBaseband_to_Headset(void)
 859 {
 860         DBG("Enter::%s----line->%d-- HandsetMIC_to_PCMBaseband_to_Headset\n",__FUNCTION__,__LINE__);
 861         wm8994_mode=wm8994_HandsetMIC_to_PCMBaseband_to_Headset;
 862         wm8994_reset();
 863         mdelay(50);
 864
 865         wm8994_write(0x01,  0x0003);
 866         mdelay(50);
 867         wm8994_write(0x221, 0x0700);
 868         wm8994_write(0x222, 0x3127);
 869         wm8994_write(0x223, 0x0100);
 870         wm8994_write(0x220, 0x0004);
 871         mdelay(50);
 872         wm8994_write(0x220, 0x0005);
 873
 874         wm8994_write(0x01,  0x0303);  // sysclk = fll (bit4 =1)   0x0011
 875         wm8994_write(0x02,  0x0240);
 876         wm8994_write(0x03,  0x0030);
 877         wm8994_write(0x04,  0x3003);
 878         wm8994_write(0x05,  0x3003);  // i2s 16 bits
 879         wm8994_write(0x18,  0x010B);
 880         wm8994_write(0x28,  0x0030);
 881         wm8994_write(0x29,  0x0020);
 882         wm8994_write(0x2D,  0x0100);
 883         wm8994_write(0x2E,  0x0100);
 884         wm8994_write(0x4C,  0x9F25);
 885         wm8994_write(0x60,  0x00EE);
 886         wm8994_write(0x200, 0x0001);
 887         wm8994_write(0x204, 0x0001);
 888         wm8994_write(0x208, 0x0007);
 889         wm8994_write(0x520, 0x0000);
 890         wm8994_write(0x601, 0x0004);
 891         wm8994_write(0x602, 0x0004);
 892
 893         wm8994_write(0x610, 0x01C0);
 894         wm8994_write(0x611, 0x01C0);
 895         wm8994_write(0x612, 0x01C0);
 896         wm8994_write(0x613, 0x01C0);
 897
 898         wm8994_write(0x702, 0xC100);
 899         wm8994_write(0x703, 0xC100);
 900         wm8994_write(0x704, 0xC100);
 901         wm8994_write(0x706, 0x4100);
 902         wm8994_write(0x204, 0x0011);
 903         wm8994_write(0x211, 0x0009);
 904         wm8994_write(0x310, 0x4118);
 905         wm8994_write(0x313, 0x00F0);
 906         wm8994_write(0x314, 0x0020);
 907         wm8994_write(0x315, 0x0020);
 908
 909         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
 910         wm8994_write(0x604, 0x0010);
 911         wm8994_write(0x605, 0x0010);
 912         wm8994_write(0x621, 0x0001);
 913 //      wm8994_write(0x317, 0x0003);
 914 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 915         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
 916 #endif
 917 }
 918
 919 void  HandsetMIC_to_PCMBaseband_to_Headset_and_Record(void)
 920 {
 921         DBG("Enter::%s----line->%d-- HandsetMIC_to_PCMBaseband_to_Headset_and_Record\n",__FUNCTION__,__LINE__);
 922         wm8994_mode=wm8994_HandsetMIC_to_PCMBaseband_to_Headset_and_Record;
 923         wm8994_reset();
 924         mdelay(50);
 925
 926         wm8994_write(0x01,  0x0003);
 927         mdelay(50);
 928         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
 929         wm8994_write(0x222, 0x3127);
 930         wm8994_write(0x223, 0x0100);
 931         wm8994_write(0x220, 0x0004);
 932         mdelay(50);
 933         wm8994_write(0x220, 0x0005);
 934
 935         wm8994_write(0x01,  0x0303);
 936         wm8994_write(0x02,  0x0240);
 937         wm8994_write(0x03,  0x0030);
 938         wm8994_write(0x04,  0x3003);
 939         wm8994_write(0x05,  0x3003);
 940         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
 941         wm8994_write(0x28,  0x0030);
 942         wm8994_write(0x29,  0x0020);
 943         wm8994_write(0x2D,  0x0100);
 944         wm8994_write(0x2E,  0x0100);
 945         wm8994_write(0x4C,  0x9F25);
 946         wm8994_write(0x60,  0x00EE);
 947         wm8994_write(0x200, 0x0001);
 948         wm8994_write(0x204, 0x0001);
 949         wm8994_write(0x208, 0x0007);
 950         wm8994_write(0x520, 0x0000);
 951         wm8994_write(0x601, 0x0004);
 952         wm8994_write(0x602, 0x0004);
 953
 954         wm8994_write(0x610, 0x01C0);
 955         wm8994_write(0x611, 0x01C0);
 956         wm8994_write(0x612, 0x01C0);
 957         wm8994_write(0x613, 0x01C0);
 958
 959         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
 960         wm8994_write(0x702, 0xC100);
 961         wm8994_write(0x703, 0xC100);
 962         wm8994_write(0x704, 0xC100);
 963         wm8994_write(0x706, 0x4100);
 964         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
 965         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
 966         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
 967         wm8994_write(0x313, 0x00F0);
 968         wm8994_write(0x314, 0x0020);
 969         wm8994_write(0x315, 0x0020);
 970
 971         wm8994_write(0x603, 0x000C);  //Rev.D ADCL SideTone
 972         wm8994_write(0x604, 0x0010);
 973         wm8994_write(0x605, 0x0010);
 974         wm8994_write(0x621, 0x0000);
 975 //      wm8994_write(0x317, 0x0003);
 976 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 977         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
 978 #endif
 979 ////AIF1
 980         wm8994_write(0x04,   0x3303);
 981         wm8994_write(0x200,  0x0001);
 982         wm8994_write(0x208,  0x000F);
 983         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
 984         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
 985         wm8994_write(0x606,  0x0003);
 986         wm8994_write(0x607,  0x0003);
 987
 988 ////AIF1 Master Clock(SR=8KHz)
 989         wm8994_write(0x200,  0x0011);
 990 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 991         wm8994_write(0x302,  0x4000);
 992 #endif
 993         wm8994_write(0x303,  0x00F0);
 994         wm8994_write(0x304,  0x0020);
 995         wm8994_write(0x305,  0x0020);
 996
 997 ////AIF1 DAC1 HP
 998         wm8994_write(0x05,   0x3303);
 999         wm8994_write(0x420,  0x0000);
1000         wm8994_write(0x601,  0x0001);
1001         wm8994_write(0x602,  0x0001);
1002         wm8994_write(0x700,  0x8140);  //SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1003 }
1004
1005 void  MainMIC_to_PCMBaseband_to_Earpiece(void)
1006 {
1007         DBG("Enter::%s----line->%d-- MainMIC_to_PCMBaseband_to_Earpiece\n",__FUNCTION__,__LINE__);
1008         wm8994_mode=wm8994_MainMIC_to_PCMBaseband_to_Earpiece;
1009         wm8994_reset();
1010         mdelay(50);
1011
1012         wm8994_write(0x01,  0x0013);
1013         mdelay(50);
1014         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1015         wm8994_write(0x222, 0x3127);
1016         wm8994_write(0x223, 0x0100);
1017         wm8994_write(0x220, 0x0004);
1018         mdelay(50);
1019         wm8994_write(0x220, 0x0005);
1020
1021         wm8994_write(0x01,  0x0813);
1022         wm8994_write(0x02,  0x0110);
1023         wm8994_write(0x03,  0x00F0);
1024         wm8994_write(0x04,  0x3003);
1025         wm8994_write(0x05,  0x3003);
1026         wm8994_write(0x1A,  0x010B);
1027         wm8994_write(0x1F,  0x0000);
1028         wm8994_write(0x28,  0x0003);
1029         wm8994_write(0x2A,  0x0020);
1030         wm8994_write(0x2D,  0x0001);
1031         wm8994_write(0x2E,  0x0001);
1032         wm8994_write(0x33,  0x0018);
1033 //      wm8994_write(0x4C,  0x9F25);
1034 //      wm8994_write(0x60,  0x00EE);
1035         wm8994_write(0x200, 0x0001);
1036         wm8994_write(0x204, 0x0001);
1037         wm8994_write(0x208, 0x0007);
1038         wm8994_write(0x520, 0x0000);
1039         wm8994_write(0x601, 0x0004);
1040         wm8994_write(0x602, 0x0004);
1041
1042         wm8994_write(0x610, 0x01C0);
1043         wm8994_write(0x611, 0x01C0);
1044         wm8994_write(0x612, 0x01C0);
1045         wm8994_write(0x613, 0x01C0);
1046
1047         wm8994_write(0x700, 0x8141);
1048         wm8994_write(0x702, 0xC100);
1049         wm8994_write(0x703, 0xC100);
1050         wm8994_write(0x704, 0xC100);
1051         wm8994_write(0x706, 0x4100);
1052         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1053         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1054         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1055         wm8994_write(0x313, 0x00F0);
1056         wm8994_write(0x314, 0x0020);
1057         wm8994_write(0x315, 0x0020);
1058
1059         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1060         wm8994_write(0x604, 0x0010);
1061         wm8994_write(0x605, 0x0010);
1062         wm8994_write(0x621, 0x0001);
1063 //      wm8994_write(0x317, 0x0003);
1064 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1065         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1066 #endif
1067 }
1068
1069 void  MainMIC_to_PCMBaseband_to_Earpiece_and_Record(void)
1070 {
1071         DBG("Enter::%s----line->%d-- MainMIC_to_PCMBaseband_to_Earpiece_and_Record\n",__FUNCTION__,__LINE__);
1072         wm8994_mode=wm8994_MainMIC_to_PCMBaseband_to_Earpiece_and_Record;
1073         wm8994_reset();
1074         mdelay(50);
1075
1076         wm8994_write(0x01,  0x0013);
1077         mdelay(50);
1078         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1079         wm8994_write(0x222, 0x3127);
1080         wm8994_write(0x223, 0x0100);
1081         wm8994_write(0x220, 0x0004);
1082         mdelay(50);
1083         wm8994_write(0x220, 0x0005);
1084
1085         wm8994_write(0x01,  0x0813);
1086         wm8994_write(0x02,  0x0110);
1087         wm8994_write(0x03,  0x00F0);
1088         wm8994_write(0x04,  0x3003);
1089         wm8994_write(0x05,  0x3003);
1090         wm8994_write(0x1A,  0x010B);
1091         wm8994_write(0x1F,  0x0000);
1092         wm8994_write(0x28,  0x0003);
1093         wm8994_write(0x2A,  0x0020);
1094         wm8994_write(0x2D,  0x0001);
1095         wm8994_write(0x2E,  0x0001);
1096         wm8994_write(0x33,  0x0018);
1097 //      wm8994_write(0x4C,  0x9F25);
1098 //      wm8994_write(0x60,  0x00EE);
1099         wm8994_write(0x200, 0x0001);
1100         wm8994_write(0x204, 0x0001);
1101         wm8994_write(0x208, 0x0007);
1102         wm8994_write(0x520, 0x0000);
1103         wm8994_write(0x601, 0x0004);
1104         wm8994_write(0x602, 0x0004);
1105
1106         wm8994_write(0x610, 0x01C0);
1107         wm8994_write(0x611, 0x01C0);
1108         wm8994_write(0x612, 0x01C0);
1109         wm8994_write(0x613, 0x01C0);
1110
1111         wm8994_write(0x702, 0xC100);
1112         wm8994_write(0x703, 0xC100);
1113         wm8994_write(0x704, 0xC100);
1114         wm8994_write(0x706, 0x4100);
1115         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1116         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1117         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1118         wm8994_write(0x313, 0x00F0);
1119         wm8994_write(0x314, 0x0020);
1120         wm8994_write(0x315, 0x0020);
1121
1122         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1123         wm8994_write(0x604, 0x0010);
1124         wm8994_write(0x605, 0x0010);
1125         wm8994_write(0x621, 0x0001);
1126 //      wm8994_write(0x317, 0x0003);
1127 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1128         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1129 #endif
1130
1131 ////AIF1
1132         wm8994_write(0x04,   0x3303);
1133         wm8994_write(0x200,  0x0001);
1134         wm8994_write(0x208,  0x000F);
1135         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1136         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1137         wm8994_write(0x606,  0x0003);
1138         wm8994_write(0x607,  0x0003);
1139
1140 ////AIF1 Master Clock(SR=8KHz)
1141         wm8994_write(0x200,  0x0011);
1142 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1143         wm8994_write(0x302,  0x4000);
1144 #endif
1145         wm8994_write(0x303,  0x00F0);
1146         wm8994_write(0x304,  0x0020);
1147         wm8994_write(0x305,  0x0020);
1148
1149 ////AIF1 DAC1 HP
1150         wm8994_write(0x05,   0x3303);
1151         wm8994_write(0x420,  0x0000);
1152         wm8994_write(0x601,  0x0001);
1153         wm8994_write(0x602,  0x0001);
1154         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1155 }
1156
1157 void  MainMIC_to_PCMBaseband_to_Speakers(void)
1158 {
1159         DBG("Enter::%s----line->%d-- MainMIC_to_PCMBaseband_to_Speakers\n",__FUNCTION__,__LINE__);
1160         wm8994_mode=wm8994_MainMIC_to_PCMBaseband_to_Speakers;
1161         wm8994_reset();
1162         mdelay(50);
1163 #if 1
1164         wm8994_write(0x01,  0x0013);
1165         mdelay(50);
1166         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1167         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1168         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1169         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1170         mdelay(50);
1171         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1172
1173         wm8994_write(0x01,  0x3013);
1174         wm8994_write(0x02,  0x0110);
1175         wm8994_write(0x03,  0x0330);
1176         wm8994_write(0x04,  0x3003);
1177         wm8994_write(0x05,  0x3003);
1178         wm8994_write(0x1A,  0x011F);
1179         wm8994_write(0x22,  0x0000);
1180         wm8994_write(0x23,  0x0000);
1181         wm8994_write(0x28,  0x0003);
1182         wm8994_write(0x2A,  0x0020);
1183         wm8994_write(0x2D,  0x0001);
1184         wm8994_write(0x2E,  0x0001);
1185         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1186 //      wm8994_write(0x4C,  0x9F25);
1187 //      wm8994_write(0x60,  0x00EE);
1188         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1189         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1190         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1191         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1192         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1193         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1194
1195         wm8994_write(0x610, 0x01C0);  //DAC1L_VOLUME
1196         wm8994_write(0x611, 0x01C0);  //DAC1R_VOLUME
1197         wm8994_write(0x612, 0x01C0);  //DAC2L_VOLUME
1198         wm8994_write(0x613, 0x01C0);  //DAC2R_VOLUME
1199
1200         wm8994_write(0x702, 0xC100);  //GPIO3
1201         wm8994_write(0x703, 0xC100);  //GPIO4
1202         wm8994_write(0x704, 0xC100);  //GPIO5
1203         wm8994_write(0x706, 0x4100);  //GPIO7
1204         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1205         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1206         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1207         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1208         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1209         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1210
1211         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1212         wm8994_write(0x604, 0x0010);  //ADC2_TO_DAC2L
1213         wm8994_write(0x605, 0x0010);  //ADC2_TO_DAC2R
1214         wm8994_write(0x621, 0x0001);
1215 //      wm8994_write(0x317, 0x0003);
1216 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1217         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1218 #endif
1219 #endif
1220 }
1221
1222 void  MainMIC_to_PCMBaseband_to_Speakers_and_Record(void)
1223 {
1224         DBG("Enter::%s----line->%d-- MainMIC_to_PCMBaseband_to_Speakers_and_Record\n",__FUNCTION__,__LINE__);
1225         wm8994_mode=wm8994_MainMIC_to_PCMBaseband_to_Speakers_and_Record;
1226         wm8994_reset();
1227         mdelay(50);
1228
1229         wm8994_write(0x01,  0x0013);
1230         mdelay(50);
1231         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1232         wm8994_write(0x222, 0x3127);
1233         wm8994_write(0x223, 0x0100);
1234         wm8994_write(0x220, 0x0004);
1235         mdelay(50);
1236         wm8994_write(0x220, 0x0005);
1237
1238         wm8994_write(0x01,  0x3013);
1239         wm8994_write(0x02,  0x0110);
1240         wm8994_write(0x03,  0x0330);
1241         wm8994_write(0x04,  0x3003);
1242         wm8994_write(0x05,  0x3003);
1243         wm8994_write(0x1A,  0x010B);
1244         wm8994_write(0x22,  0x0000);
1245         wm8994_write(0x23,  0x0000);
1246         wm8994_write(0x28,  0x0003);
1247         wm8994_write(0x2A,  0x0020);
1248         wm8994_write(0x2D,  0x0001);
1249         wm8994_write(0x2E,  0x0001);
1250         wm8994_write(0x36,  0x000C);
1251 //      wm8994_write(0x4C,  0x9F25);
1252 //      wm8994_write(0x60,  0x00EE);
1253         wm8994_write(0x200, 0x0001);
1254         wm8994_write(0x204, 0x0001);
1255         wm8994_write(0x208, 0x0007);
1256         wm8994_write(0x520, 0x0000);
1257         wm8994_write(0x601, 0x0004);
1258         wm8994_write(0x602, 0x0004);
1259
1260         wm8994_write(0x610, 0x01C0);
1261         wm8994_write(0x611, 0x01C0);
1262         wm8994_write(0x612, 0x01C0);
1263         wm8994_write(0x613, 0x01C0);
1264
1265         wm8994_write(0x700, 0x8141);
1266         wm8994_write(0x702, 0xC100);
1267         wm8994_write(0x703, 0xC100);
1268         wm8994_write(0x704, 0xC100);
1269         wm8994_write(0x706, 0x4100);
1270         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1271         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1272         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1273         wm8994_write(0x313, 0x00F0);
1274         wm8994_write(0x314, 0x0020);
1275         wm8994_write(0x315, 0x0020);
1276
1277         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1278         wm8994_write(0x604, 0x0010);
1279         wm8994_write(0x605, 0x0010);
1280         wm8994_write(0x621, 0x0001);
1281 //      wm8994_write(0x317, 0x0003);
1282 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1283         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1284 #endif
1285
1286 ////AIF1
1287         wm8994_write(0x04,   0x3303);
1288         wm8994_write(0x200,  0x0001);
1289         wm8994_write(0x208,  0x000F);
1290         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1291         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1292         wm8994_write(0x606,  0x0003);
1293         wm8994_write(0x607,  0x0003);
1294
1295 ////AIF1 Master Clock(SR=8KHz)
1296         wm8994_write(0x200,  0x0011);
1297 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1298         wm8994_write(0x302,  0x4000);
1299 #endif
1300         wm8994_write(0x303,  0x00F0);
1301         wm8994_write(0x304,  0x0020);
1302         wm8994_write(0x305,  0x0020);
1303
1304 ////AIF1 DAC1 HP
1305         wm8994_write(0x05,   0x3303);
1306         wm8994_write(0x420,  0x0000);
1307         wm8994_write(0x601,  0x0001);
1308         wm8994_write(0x602,  0x0001);
1309         wm8994_write(0x700,  0x8140);  //SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1310 }
1311
1312 void  BT_PCMBaseband(void)
1313 {
1314         DBG("Enter::%s----line->%d-- BT_PCMBaseband\n",__FUNCTION__,__LINE__);
1315         wm8994_mode=wm8994_BT_PCMBaseband;
1316         wm8994_reset();
1317         mdelay(50);
1318
1319         wm8994_write(0x01  ,0x0003);
1320         mdelay (50);
1321
1322         wm8994_write(0x200 ,0x0001);
1323         wm8994_write(0x221 ,0x0700);  //MCLK=12MHz
1324         wm8994_write(0x222 ,0x3127);
1325         wm8994_write(0x223 ,0x0100);
1326         wm8994_write(0x220 ,0x0004);
1327         mdelay (50);
1328         wm8994_write(0x220 ,0x0005);
1329
1330         wm8994_write(0x02  ,0x0000);
1331         wm8994_write(0x200 ,0x0011);  // AIF1 MCLK=FLL1
1332         wm8994_write(0x210 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1333         wm8994_write(0x300 ,0x4018);  // DSP/PCM 16bits
1334
1335         wm8994_write(0x204 ,0x0011);  // AIF2 MCLK=FLL1
1336         wm8994_write(0x211 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1337         wm8994_write(0x310 ,0x4118);  // DSP/PCM 16bits
1338         wm8994_write(0x208 ,0x000F);
1339
1340 /////AIF1
1341         wm8994_write(0x700 ,0x8101);
1342 /////AIF2
1343         wm8994_write(0x702 ,0xC100);
1344         wm8994_write(0x703 ,0xC100);
1345         wm8994_write(0x704 ,0xC100);
1346         wm8994_write(0x706 ,0x4100);
1347 /////AIF3
1348         wm8994_write(0x707 ,0xA100);
1349         wm8994_write(0x708 ,0xA100);
1350         wm8994_write(0x709 ,0xA100);
1351         wm8994_write(0x70A ,0xA100);
1352
1353         wm8994_write(0x06 ,0x0001);
1354
1355         wm8994_write(0x02 ,0x0300);
1356         wm8994_write(0x03 ,0x0030);
1357         wm8994_write(0x04 ,0x3301);  //ADCL off
1358         wm8994_write(0x05 ,0x3301);  //DACL off
1359
1360 //      wm8994_write(0x29 ,0x0005);
1361         wm8994_write(0x2A ,0x0005);
1362
1363         wm8994_write(0x313 ,0x00F0);
1364         wm8994_write(0x314 ,0x0020);
1365         wm8994_write(0x315 ,0x0020);
1366
1367 //      wm8994_write(0x2D  ,0x0001);
1368         wm8994_write(0x2E  ,0x0001);
1369         wm8994_write(0x420 ,0x0000);
1370         wm8994_write(0x520 ,0x0000);
1371 //      wm8994_write(0x601 ,0x0001);
1372         wm8994_write(0x602 ,0x0001);
1373         wm8994_write(0x604 ,0x0001);
1374         wm8994_write(0x605 ,0x0001);
1375 //      wm8994_write(0x606 ,0x0002);
1376         wm8994_write(0x607 ,0x0002);
1377 //      wm8994_write(0x610 ,0x01C0);
1378         wm8994_write(0x611 ,0x01C0);
1379         wm8994_write(0x612 ,0x01C0);
1380         wm8994_write(0x613 ,0x01C0);
1381
1382 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1383         wm8994_write(0x312 ,0x4000);
1384 #endif
1385
1386         wm8994_write(0x606 ,0x0001);
1387         wm8994_write(0x607 ,0x0003);  //R channel for data mix/CPU record data
1388
1389 ////////////HP output test
1390         wm8994_write(0x01  ,0x0303);
1391         wm8994_write(0x4C  ,0x9F25);
1392         wm8994_write(0x60  ,0x00EE);
1393 ///////////end HP test
1394 }
1395
1396 void  BT_PCMBaseband_and_record(void)
1397 {
1398         DBG("Enter::%s----line->%d-- BT_PCMBaseband_and_record\n",__FUNCTION__,__LINE__);
1399         wm8994_mode=wm8994_BT_PCMBaseband_and_record;
1400         wm8994_reset();
1401         mdelay(50);
1402
1403         wm8994_write(0x01  ,0x0003);
1404         mdelay (50);
1405
1406         wm8994_write(0x200 ,0x0001);
1407         wm8994_write(0x221 ,0x0700);  //MCLK=12MHz
1408         wm8994_write(0x222 ,0x3127);
1409         wm8994_write(0x223 ,0x0100);
1410         wm8994_write(0x220 ,0x0004);
1411         mdelay (50);
1412         wm8994_write(0x220 ,0x0005);
1413
1414         wm8994_write(0x02  ,0x0000);
1415         wm8994_write(0x200 ,0x0011);  // AIF1 MCLK=FLL1
1416         wm8994_write(0x210 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1417         wm8994_write(0x300 ,0x4018);  // DSP/PCM 16bits
1418
1419         wm8994_write(0x204 ,0x0011);  // AIF2 MCLK=FLL1
1420         wm8994_write(0x211 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1421         wm8994_write(0x310 ,0x4118);  // DSP/PCM 16bits
1422         wm8994_write(0x208 ,0x000F);
1423
1424 /////AIF1
1425         wm8994_write(0x700 ,0x8101);
1426 /////AIF2
1427         wm8994_write(0x702 ,0xC100);
1428         wm8994_write(0x703 ,0xC100);
1429         wm8994_write(0x704 ,0xC100);
1430         wm8994_write(0x706 ,0x4100);
1431 /////AIF3
1432         wm8994_write(0x707 ,0xA100);
1433         wm8994_write(0x708 ,0xA100);
1434         wm8994_write(0x709 ,0xA100);
1435         wm8994_write(0x70A ,0xA100);
1436
1437         wm8994_write(0x06  ,0x0001);
1438
1439         wm8994_write(0x02  ,0x0300);
1440         wm8994_write(0x03  ,0x0030);
1441         wm8994_write(0x04  ,0x3301);  //ADCL off
1442         wm8994_write(0x05  ,0x3301);  //DACL off
1443
1444 //      wm8994_write(0x29  ,0x0005);
1445         wm8994_write(0x2A  ,0x0005);
1446
1447         wm8994_write(0x313 ,0x00F0);
1448         wm8994_write(0x314 ,0x0020);
1449         wm8994_write(0x315 ,0x0020);
1450
1451 //      wm8994_write(0x2D  ,0x0001);
1452         wm8994_write(0x2E  ,0x0001);
1453         wm8994_write(0x420 ,0x0000);
1454         wm8994_write(0x520 ,0x0000);
1455 //      wm8994_write(0x601 ,0x0001);
1456         wm8994_write(0x602 ,0x0001);
1457         wm8994_write(0x604 ,0x0001);
1458         wm8994_write(0x605 ,0x0001);
1459 //      wm8994_write(0x606 ,0x0002);
1460         wm8994_write(0x607 ,0x0002);
1461 //      wm8994_write(0x610 ,0x01C0);
1462         wm8994_write(0x611 ,0x01C0);
1463         wm8994_write(0x612 ,0x01C0);
1464         wm8994_write(0x613 ,0x01C0);
1465
1466 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1467         wm8994_write(0x312 ,0x4000);
1468 #endif
1469
1470         wm8994_write(0x606 ,0x0001);
1471         wm8994_write(0x607 ,0x0003);  //R channel for data mix/CPU record data
1472
1473 ////////////HP output test
1474         wm8994_write(0x01  ,0x0303);
1475         wm8994_write(0x4C  ,0x9F25);
1476         wm8994_write(0x60  ,0x00EE);
1477 ///////////end HP test
1478 }
1479
1480
1481 typedef void (wm8994_codec_fnc_t) (void);
1482
1483 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
1484         AP_to_Headset,
1485         AP_to_Speakers,
1486         Recorder,
1487         FM_to_Headset,
1488         FM_to_Headset_and_Record,
1489         FM_to_Speakers,
1490         FM_to_Speakers_and_Record,
1491         HandsetMIC_to_Baseband_to_Headset,
1492         HandsetMIC_to_Baseband_to_Headset_and_Record,
1493         MainMIC_to_Baseband_to_Earpiece,
1494         MainMIC_to_Baseband_to_Earpiece_and_Record,
1495         MainMIC_to_Baseband_to_Speakers,
1496         MainMIC_to_Baseband_to_Speakers_and_Record,
1497         BT_Baseband,
1498         BT_Baseband_and_record,
1499 ///PCM BB BEGIN
1500         HandsetMIC_to_PCMBaseband_to_Headset,
1501         HandsetMIC_to_PCMBaseband_to_Headset_and_Record,
1502         MainMIC_to_PCMBaseband_to_Earpiece,
1503         MainMIC_to_PCMBaseband_to_Earpiece_and_Record,
1504         MainMIC_to_PCMBaseband_to_Speakers,
1505         MainMIC_to_PCMBaseband_to_Speakers_and_Record,
1506         BT_PCMBaseband,
1507         BT_PCMBaseband_and_record
1508 ///PCM BB END
1509 };
1510
1511 /********************set wm8994 volume*****volume=0\1\2\3\4\5\6\7*******************/
1512
1513 unsigned char Handset_maxvol=0x3f,VRX_maxvol=0x07,Speaker_maxvol=0x3f,AP_maxvol=0xff,Recorder_maxvol=0x1f,FM_maxvol=0x1f;
1514
1515 void wm8994_codec_set_volume(unsigned char mode,unsigned char volume)
1516 {
1517         unsigned short lvol=0,rvol=0;
1518
1519         if(wm8994_mode==wm8994_HandsetMIC_to_Baseband_to_Headset_and_Record||
1520         wm8994_mode==wm8994_HandsetMIC_to_Baseband_to_Headset)
1521         {
1522                 wm8994_read(0x001c, &lvol);
1523                 wm8994_read(0x001d, &rvol);
1524                 wm8994_write(0x001c ,(0x0100|(lvol&0xffc0))|(0x003f&(Handset_maxvol*volume/7)));//bit 0~5  -57dB~6dB
1525                 wm8994_write(0x001d ,(0x0100|(rvol&0xffc0))|(0x003f&(Handset_maxvol*volume/7)));//bit 0~5 / -57dB~6dB
1526         }
1527         else if(wm8994_mode==wm8994_BT_Baseband_and_record||wm8994_mode==wm8994_BT_Baseband||
1528         wm8994_mode==wm8994_MainMIC_to_Baseband_to_Earpiece_and_Record||
1529         wm8994_mode==wm8994_MainMIC_to_Baseband_to_Earpiece)
1530         {
1531                 wm8994_read(0x002b, &lvol);
1532                 wm8994_write(0x002b ,(0x0100|(lvol&0xfff8))|(0x0007&(VRX_maxvol*volume/7))); //bit 0~2 / -12dB~6dB
1533         }
1534         else if(wm8994_mode==wm8994_MainMIC_to_Baseband_to_Speakers_and_Record||
1535         wm8994_mode==wm8994_MainMIC_to_Baseband_to_Speakers)
1536         {
1537                 wm8994_read(0x0026, &lvol);
1538                 wm8994_write(0x0026 ,(0x0100|(lvol&0xffc0))|(0x003f&(Speaker_maxvol*volume/7))); //bit0~5 / -57dB~6dB
1539         }
1540         else if(wm8994_mode==wm8994_AP_to_Headset||wm8994_mode==wm8994_AP_to_Speakers)
1541         {
1542                 wm8994_read(0x0610, &lvol);
1543                 wm8994_read(0x0611, &rvol);
1544                 wm8994_write(0x0610 ,(0x0100|(lvol&0xff00))|(0x00ff&(AP_maxvol*volume/7))); //bit 0~7 / -71.625dB~0dB
1545                 wm8994_write(0x0611 ,(0x0100|(rvol&0xff00))|(0x00ff&(AP_maxvol*volume/7))); //bit 0~7 / -71.625dB~0dB
1546         }
1547         else if(wm8994_mode==wm8994_Recorder)
1548         {
1549                 wm8994_read(0x001a, &lvol);
1550                 wm8994_write(0x001a ,(0x0100|(lvol&0xffe0))|(0x001f&(Recorder_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1551         }
1552         else if(wm8994_mode==wm8994_FM_to_Headset||wm8994_mode==wm8994_FM_to_Headset_and_Record||
1553         wm8994_mode==wm8994_FM_to_Speakers||wm8994_mode==wm8994_FM_to_Speakers_and_Record)
1554         {
1555                 wm8994_read(0x0019, &lvol);
1556                 wm8994_read(0x001b, &rvol);
1557                 wm8994_write(0x0019 ,(0x0100|(lvol&0xffe0))|(0x001f&(FM_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1558                 wm8994_write(0x001b ,(0x0100|(rvol&0xffe0))|(0x001f&(FM_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1559         }
1560 }
1561
1562
1563 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
1564 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
1565         .info = snd_soc_info_route, \
1566         .get = snd_soc_get_route, .put = snd_soc_put_route, \
1567         .private_value = route }
1568
1569 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
1570         struct snd_ctl_elem_info *uinfo)
1571 {
1572
1573         //uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1574         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1575
1576         uinfo->count = 1;
1577         uinfo->value.integer.min = 0;
1578         uinfo->value.integer.max = 0;
1579         return 0;
1580 }
1581
1582 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
1583         struct snd_ctl_elem_value *ucontrol)
1584 {
1585         DBG("@@@Enter::%s----line->%d\n",__FUNCTION__,__LINE__);
1586         return 0;
1587 }
1588
1589 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
1590         struct snd_ctl_elem_value *ucontrol)
1591 {
1592
1593         DBG("@@@Enter::%s----line->%d\n",__FUNCTION__,__LINE__);
1594         int route = kcontrol->private_value & 0xff;
1595
1596         switch(route)
1597         {
1598                 /* Speaker*/
1599                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
1600 #ifndef WM8994_TEST
1601                     AP_to_Speakers();
1602 #endif
1603                     break;
1604                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
1605                     MainMIC_to_Baseband_to_Speakers();
1606                     break;
1607
1608                 /* Headset */
1609                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
1610                     AP_to_Headset();
1611                     break;
1612                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
1613                     HandsetMIC_to_Baseband_to_Headset();
1614                     break;
1615
1616                 /* Earpiece*/
1617                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
1618                     MainMIC_to_Baseband_to_Earpiece();
1619                     break;
1620
1621                 /* BLUETOOTH_SCO*/
1622                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
1623                     BT_Baseband();
1624                     break;
1625
1626                 /* BLUETOOTH_A2DP*/
1627                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
1628                     break;
1629
1630                 case MIC_CAPTURE:  //
1631                     Recorder();
1632                     break;
1633                 default:
1634                     //codec_daout_route();
1635                     break;
1636         }
1637         return 0;
1638 }
1639
1640 /*
1641  * WM8994 Controls
1642  */
1643
1644 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
1645 static const struct soc_enum bass_boost =
1646         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
1647
1648 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
1649 static const struct soc_enum bass_filter =
1650         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
1651
1652 static const char *treble_txt[] = {"8kHz", "4kHz"};
1653 static const struct soc_enum treble =
1654         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
1655
1656 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
1657 static const struct soc_enum stereo_3d_lc =
1658         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
1659
1660 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
1661 static const struct soc_enum stereo_3d_uc =
1662         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
1663
1664 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
1665 static const struct soc_enum stereo_3d_func =
1666         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
1667
1668 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
1669 static const struct soc_enum alc_func =
1670         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
1671
1672 static const char *ng_type_txt[] = {"Constant PGA Gain",
1673                                     "Mute ADC Output"};
1674 static const struct soc_enum ng_type =
1675         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
1676
1677 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
1678 static const struct soc_enum deemph =
1679         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
1680
1681 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
1682                                    "L + R Invert"};
1683 static const struct soc_enum adcpol =
1684         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
1685
1686 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
1687 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
1688 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
1689 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1690 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1691
1692 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
1693
1694 /* 鍠囧彮 */
1695 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
1696 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
1697 /* 鍚瓛 */
1698 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
1699 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
1700 /* 鑰虫満 */
1701 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
1702 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
1703 /* 钃濈墮SCO */
1704 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
1705 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
1706 /* 钃濈墮A2DP */
1707 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
1708 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
1709 /* 鑰抽害 */
1710 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
1711
1712 };
1713
1714 /*
1715  * DAPM Controls
1716  */
1717
1718 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
1719                               struct snd_kcontrol *kcontrol, int event)
1720 {
1721         struct snd_soc_codec *codec = w->codec;
1722         u16 adctl2 = snd_soc_read(codec, WM8994_ADCTL2);
1723
1724         /* Use the DAC to gate LRC if active, otherwise use ADC */
1725         if (snd_soc_read(codec, WM8994_PWR2) & 0x180)
1726                 adctl2 &= ~0x4;
1727         else
1728                 adctl2 |= 0x4;
1729
1730         DBG("Enter::%s----line->%d, adctl2 = %x\n",__FUNCTION__,__LINE__,adctl2);
1731
1732         return snd_soc_write(codec, WM8994_ADCTL2, adctl2);
1733 }
1734
1735 static const char *wm8994_line_texts[] = {
1736         "Line 1", "Line 2", "PGA", "Differential"};
1737
1738 static const unsigned int wm8994_line_values[] = {
1739         0, 1, 3, 4};
1740
1741 static const struct soc_enum wm8994_lline_enum =
1742         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
1743                               ARRAY_SIZE(wm8994_line_texts),
1744                               wm8994_line_texts,
1745                               wm8994_line_values);
1746 static const struct snd_kcontrol_new wm8994_left_line_controls =
1747         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
1748
1749 static const struct soc_enum wm8994_rline_enum =
1750         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
1751                               ARRAY_SIZE(wm8994_line_texts),
1752                               wm8994_line_texts,
1753                               wm8994_line_values);
1754 static const struct snd_kcontrol_new wm8994_right_line_controls =
1755         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
1756
1757 /* Left Mixer */
1758 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
1759         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
1760         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
1761         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
1762         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
1763 };
1764
1765 /* Right Mixer */
1766 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
1767         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
1768         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
1769         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
1770         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
1771 };
1772
1773 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
1774 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
1775
1776 /* Left PGA Mux */
1777 static const struct soc_enum wm8994_lpga_enum =
1778         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
1779                               ARRAY_SIZE(wm8994_pga_sel),
1780                               wm8994_pga_sel,
1781                               wm8994_pga_val);
1782 static const struct snd_kcontrol_new wm8994_left_pga_controls =
1783         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
1784
1785 /* Right PGA Mux */
1786 static const struct soc_enum wm8994_rpga_enum =
1787         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
1788                               ARRAY_SIZE(wm8994_pga_sel),
1789                               wm8994_pga_sel,
1790                               wm8994_pga_val);
1791 static const struct snd_kcontrol_new wm8994_right_pga_controls =
1792         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
1793
1794 /* Differential Mux */
1795 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
1796 static const struct soc_enum diffmux =
1797         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
1798 static const struct snd_kcontrol_new wm8994_diffmux_controls =
1799         SOC_DAPM_ENUM("Route", diffmux);
1800
1801 /* Mono ADC Mux */
1802 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
1803         "Mono (Right)", "Digital Mono"};
1804 static const struct soc_enum monomux =
1805         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
1806 static const struct snd_kcontrol_new wm8994_monomux_controls =
1807         SOC_DAPM_ENUM("Route", monomux);
1808
1809 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1810         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
1811
1812         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
1813                 &wm8994_diffmux_controls),
1814         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
1815                 &wm8994_monomux_controls),
1816         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
1817                 &wm8994_monomux_controls),
1818
1819         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
1820                 &wm8994_left_pga_controls),
1821         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
1822                 &wm8994_right_pga_controls),
1823
1824         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
1825                 &wm8994_left_line_controls),
1826         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
1827                 &wm8994_right_line_controls),
1828
1829         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
1830         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
1831
1832         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
1833         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
1834
1835         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
1836                 &wm8994_left_mixer_controls[0],
1837                 ARRAY_SIZE(wm8994_left_mixer_controls)),
1838         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
1839                 &wm8994_right_mixer_controls[0],
1840                 ARRAY_SIZE(wm8994_right_mixer_controls)),
1841
1842         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
1843         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
1844         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
1845         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
1846
1847         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
1848
1849         SND_SOC_DAPM_OUTPUT("LOUT1"),
1850         SND_SOC_DAPM_OUTPUT("ROUT1"),
1851         SND_SOC_DAPM_OUTPUT("LOUT2"),
1852         SND_SOC_DAPM_OUTPUT("ROUT2"),
1853         SND_SOC_DAPM_OUTPUT("VREF"),
1854
1855         SND_SOC_DAPM_INPUT("LINPUT1"),
1856         SND_SOC_DAPM_INPUT("LINPUT2"),
1857         SND_SOC_DAPM_INPUT("RINPUT1"),
1858         SND_SOC_DAPM_INPUT("RINPUT2"),
1859 };
1860
1861 static const struct snd_soc_dapm_route audio_map[] = {
1862
1863         { "Left Line Mux", "Line 1", "LINPUT1" },
1864         { "Left Line Mux", "Line 2", "LINPUT2" },
1865         { "Left Line Mux", "PGA", "Left PGA Mux" },
1866         { "Left Line Mux", "Differential", "Differential Mux" },
1867
1868         { "Right Line Mux", "Line 1", "RINPUT1" },
1869         { "Right Line Mux", "Line 2", "RINPUT2" },
1870         { "Right Line Mux", "PGA", "Right PGA Mux" },
1871         { "Right Line Mux", "Differential", "Differential Mux" },
1872
1873         { "Left PGA Mux", "Line 1", "LINPUT1" },
1874         { "Left PGA Mux", "Line 2", "LINPUT2" },
1875         { "Left PGA Mux", "Differential", "Differential Mux" },
1876
1877         { "Right PGA Mux", "Line 1", "RINPUT1" },
1878         { "Right PGA Mux", "Line 2", "RINPUT2" },
1879         { "Right PGA Mux", "Differential", "Differential Mux" },
1880
1881         { "Differential Mux", "Line 1", "LINPUT1" },
1882         { "Differential Mux", "Line 1", "RINPUT1" },
1883         { "Differential Mux", "Line 2", "LINPUT2" },
1884         { "Differential Mux", "Line 2", "RINPUT2" },
1885
1886         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
1887         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
1888         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
1889
1890         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
1891         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
1892         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
1893
1894         { "Left ADC", NULL, "Left ADC Mux" },
1895         { "Right ADC", NULL, "Right ADC Mux" },
1896
1897         { "Left Line Mux", "Line 1", "LINPUT1" },
1898         { "Left Line Mux", "Line 2", "LINPUT2" },
1899         { "Left Line Mux", "PGA", "Left PGA Mux" },
1900         { "Left Line Mux", "Differential", "Differential Mux" },
1901
1902         { "Right Line Mux", "Line 1", "RINPUT1" },
1903         { "Right Line Mux", "Line 2", "RINPUT2" },
1904         { "Right Line Mux", "PGA", "Right PGA Mux" },
1905         { "Right Line Mux", "Differential", "Differential Mux" },
1906
1907         { "Left Mixer", "Playback Switch", "Left DAC" },
1908         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
1909         { "Left Mixer", "Right Playback Switch", "Right DAC" },
1910         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
1911
1912         { "Right Mixer", "Left Playback Switch", "Left DAC" },
1913         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
1914         { "Right Mixer", "Playback Switch", "Right DAC" },
1915         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
1916
1917         { "Left Out 1", NULL, "Left Mixer" },
1918         { "LOUT1", NULL, "Left Out 1" },
1919         { "Right Out 1", NULL, "Right Mixer" },
1920         { "ROUT1", NULL, "Right Out 1" },
1921
1922         { "Left Out 2", NULL, "Left Mixer" },
1923         { "LOUT2", NULL, "Left Out 2" },
1924         { "Right Out 2", NULL, "Right Mixer" },
1925         { "ROUT2", NULL, "Right Out 2" },
1926 };
1927
1928 struct _coeff_div {
1929         u32 mclk;
1930         u32 rate;
1931         u16 fs;
1932         u8 sr:5;
1933         u8 usb:1;
1934 };
1935
1936 /* codec hifi mclk clock divider coefficients */
1937 static const struct _coeff_div coeff_div[] = {
1938         /* 8k */
1939         {12288000, 8000, 1536, 0x6, 0x0},
1940         {11289600, 8000, 1408, 0x16, 0x0},
1941         {18432000, 8000, 2304, 0x7, 0x0},
1942         {16934400, 8000, 2112, 0x17, 0x0},
1943         {12000000, 8000, 1500, 0x6, 0x1},
1944
1945         /* 11.025k */
1946         {11289600, 11025, 1024, 0x18, 0x0},
1947         {16934400, 11025, 1536, 0x19, 0x0},
1948         {12000000, 11025, 1088, 0x19, 0x1},
1949
1950         /* 16k */
1951         {12288000, 16000, 768, 0xa, 0x0},
1952         {18432000, 16000, 1152, 0xb, 0x0},
1953         {12000000, 16000, 750, 0xa, 0x1},
1954
1955         /* 22.05k */
1956         {11289600, 22050, 512, 0x1a, 0x0},
1957         {16934400, 22050, 768, 0x1b, 0x0},
1958         {12000000, 22050, 544, 0x1b, 0x1},
1959
1960         /* 32k */
1961         {12288000, 32000, 384, 0xc, 0x0},
1962         {18432000, 32000, 576, 0xd, 0x0},
1963         {12000000, 32000, 375, 0xa, 0x1},
1964
1965         /* 44.1k */
1966         {11289600, 44100, 256, 0x10, 0x0},
1967         {16934400, 44100, 384, 0x11, 0x0},
1968         {12000000, 44100, 272, 0x11, 0x1},
1969
1970         /* 48k */
1971         {12288000, 48000, 256, 0x0, 0x0},
1972         {18432000, 48000, 384, 0x1, 0x0},
1973         {12000000, 48000, 250, 0x0, 0x1},
1974
1975         /* 88.2k */
1976         {11289600, 88200, 128, 0x1e, 0x0},
1977         {16934400, 88200, 192, 0x1f, 0x0},
1978         {12000000, 88200, 136, 0x1f, 0x1},
1979
1980         /* 96k */
1981         {12288000, 96000, 128, 0xe, 0x0},
1982         {18432000, 96000, 192, 0xf, 0x0},
1983         {12000000, 96000, 125, 0xe, 0x1},
1984 };
1985
1986
1987 static inline int get_coeff(int mclk, int rate)
1988 {
1989         int i;
1990
1991         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
1992                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
1993                         return i;
1994         }
1995
1996         return -EINVAL;
1997 }
1998
1999 /* The set of rates we can generate from the above for each SYSCLK */
2000
2001 static unsigned int rates_12288[] = {
2002         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
2003 };
2004
2005 static struct snd_pcm_hw_constraint_list constraints_12288 = {
2006         .count  = ARRAY_SIZE(rates_12288),
2007         .list   = rates_12288,
2008 };
2009
2010 static unsigned int rates_112896[] = {
2011         8000, 11025, 22050, 44100,
2012 };
2013
2014 static struct snd_pcm_hw_constraint_list constraints_112896 = {
2015         .count  = ARRAY_SIZE(rates_112896),
2016         .list   = rates_112896,
2017 };
2018
2019 static unsigned int rates_12[] = {
2020         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
2021         48000, 88235, 96000,
2022 };
2023
2024 static struct snd_pcm_hw_constraint_list constraints_12 = {
2025         .count  = ARRAY_SIZE(rates_12),
2026         .list   = rates_12,
2027 };
2028
2029 /*
2030  * Note that this should be called from init rather than from hw_params.
2031  */
2032 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2033                 int clk_id, unsigned int freq, int dir)
2034 {
2035         struct snd_soc_codec *codec = codec_dai->codec;
2036         struct wm8994_priv *wm8994 = codec->private_data;
2037
2038         DBG("Enter::%s----line->%d\n",__FUNCTION__,__LINE__);
2039
2040         switch (freq) {
2041         case 11289600:
2042         case 18432000:
2043         case 22579200:
2044         case 36864000:
2045                 wm8994->sysclk_constraints = &constraints_112896;
2046                 wm8994->sysclk = freq;
2047                 return 0;
2048
2049         case 12288000:
2050         case 16934400:
2051         case 24576000:
2052         case 33868800:
2053                 wm8994->sysclk_constraints = &constraints_12288;
2054                 wm8994->sysclk = freq;
2055                 return 0;
2056
2057         case 12000000:
2058         case 24000000:
2059                 wm8994->sysclk_constraints = &constraints_12;
2060                 wm8994->sysclk = freq;
2061                 return 0;
2062         }
2063         return -EINVAL;
2064 }
2065
2066 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
2067                 unsigned int fmt)
2068 {
2069         struct snd_soc_codec *codec = codec_dai->codec;
2070         u16 iface = 0;
2071
2072         /* set master/slave audio interface */
2073         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2074         case SND_SOC_DAIFMT_CBM_CFM:
2075                 iface = 0x0040;
2076                 break;
2077         case SND_SOC_DAIFMT_CBS_CFS:
2078                 break;
2079         default:
2080                 return -EINVAL;
2081         }
2082
2083         /* interface format */
2084         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2085         case SND_SOC_DAIFMT_I2S:
2086                 iface |= 0x0002;
2087                 break;
2088         case SND_SOC_DAIFMT_RIGHT_J:
2089                 break;
2090         case SND_SOC_DAIFMT_LEFT_J:
2091                 iface |= 0x0001;
2092                 break;
2093         case SND_SOC_DAIFMT_DSP_A:
2094                 iface |= 0x0003;
2095                 break;
2096         case SND_SOC_DAIFMT_DSP_B:
2097                 iface |= 0x0013;
2098                 break;
2099         default:
2100                 return -EINVAL;
2101         }
2102
2103         /* clock inversion */
2104         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2105         case SND_SOC_DAIFMT_NB_NF:
2106                 break;
2107         case SND_SOC_DAIFMT_IB_IF:
2108                 iface |= 0x0090;
2109                 break;
2110         case SND_SOC_DAIFMT_IB_NF:
2111                 iface |= 0x0080;
2112                 break;
2113         case SND_SOC_DAIFMT_NB_IF:
2114                 iface |= 0x0010;
2115                 break;
2116         default:
2117                 return -EINVAL;
2118         }
2119
2120         DBG("Enter::%s----line->%d  iface=%x\n",__FUNCTION__,__LINE__,iface);
2121         snd_soc_write(codec, WM8994_IFACE, iface);
2122         return 0;
2123 }
2124
2125 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
2126                               struct snd_soc_dai *dai)
2127 {
2128         struct snd_soc_codec *codec = dai->codec;
2129         struct wm8994_priv *wm8994 = codec->private_data;
2130
2131         /* The set of sample rates that can be supported depends on the
2132          * MCLK supplied to the CODEC - enforce this.
2133          */
2134         DBG("Enter::%s----line->%d  wm8994->sysclk=%d\n",__FUNCTION__,__LINE__,wm8994->sysclk);
2135         if (!wm8994->sysclk) {
2136                 dev_err(codec->dev,
2137                         "No MCLK configured, call set_sysclk() on init\n");
2138                 return -EINVAL;
2139         }
2140
2141         snd_pcm_hw_constraint_list(substream->runtime, 0,
2142                                    SNDRV_PCM_HW_PARAM_RATE,
2143                                    wm8994->sysclk_constraints);
2144
2145         return 0;
2146 }
2147
2148 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
2149                                 struct snd_pcm_hw_params *params,
2150                                 struct snd_soc_dai *dai)
2151 {
2152         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2153         struct snd_soc_device *socdev = rtd->socdev;
2154         struct snd_soc_codec *codec = socdev->card->codec;
2155         struct wm8994_priv *wm8994 = codec->private_data;
2156         u16 iface = snd_soc_read(codec, WM8994_IFACE) & 0x1f3;
2157         u16 srate = snd_soc_read(codec, WM8994_SRATE) & 0x180;
2158         int coeff;
2159
2160         coeff = get_coeff(wm8994->sysclk, params_rate(params));
2161         if (coeff < 0) {
2162                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
2163                 srate |= 0x40;
2164         }
2165         if (coeff < 0) {
2166                 dev_err(codec->dev,
2167                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
2168                         params_rate(params), wm8994->sysclk);
2169                 return coeff;
2170         }
2171
2172         /* bit size */
2173         switch (params_format(params)) {
2174         case SNDRV_PCM_FORMAT_S16_LE:
2175                 break;
2176         case SNDRV_PCM_FORMAT_S20_3LE:
2177                 iface |= 0x0004;
2178                 break;
2179         case SNDRV_PCM_FORMAT_S24_LE:
2180                 iface |= 0x0008;
2181                 break;
2182         case SNDRV_PCM_FORMAT_S32_LE:
2183                 iface |= 0x000c;
2184                 break;
2185         }
2186         DBG("Enter::%s----line->%d  iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
2187
2188         /* set iface & srate */
2189         snd_soc_write(codec, WM8994_IFACE, iface);
2190         if (coeff >= 0)
2191                 snd_soc_write(codec, WM8994_SRATE, srate |
2192                         (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
2193
2194         return 0;
2195 }
2196
2197 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
2198 {
2199         return 0;
2200 }
2201
2202 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2203                                  enum snd_soc_bias_level level)
2204 {
2205         u16 pwr_reg = snd_soc_read(codec, WM8994_PWR1) & ~0x1c1;
2206         DBG("Enter::%s----line->%d level =%d\n",__FUNCTION__,__LINE__,level);
2207         switch (level) {
2208         case SND_SOC_BIAS_ON:
2209                 break;
2210
2211         case SND_SOC_BIAS_PREPARE:
2212                 /* VREF, VMID=2x50k, digital enabled */
2213                 snd_soc_write(codec, WM8994_PWR1, pwr_reg | 0x00c0);
2214                 break;
2215
2216         case SND_SOC_BIAS_STANDBY:
2217                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
2218                         /* VREF, VMID=2x5k */
2219                         snd_soc_write(codec, WM8994_PWR1, pwr_reg | 0x1c1);
2220
2221                         /* Charge caps */
2222                         msleep(100);
2223                 }
2224
2225                 /* VREF, VMID=2*500k, digital stopped */
2226                 snd_soc_write(codec, WM8994_PWR1, pwr_reg | 0x0141);
2227                 break;
2228
2229         case SND_SOC_BIAS_OFF:
2230                 snd_soc_write(codec, WM8994_PWR1, 0x0000);
2231                 break;
2232         }
2233         codec->bias_level = level;
2234         return 0;
2235 }
2236
2237 //#define WM8994_RATES SNDRV_PCM_RATE_8000_96000//cjq
2238
2239 #define WM8994_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
2240
2241 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2242         SNDRV_PCM_FMTBIT_S24_LE)
2243
2244 static struct snd_soc_dai_ops wm8994_ops = {
2245         .startup = wm8994_pcm_startup,
2246         .hw_params = wm8994_pcm_hw_params,
2247         .set_fmt = wm8994_set_dai_fmt,
2248         .set_sysclk = wm8994_set_dai_sysclk,
2249         .digital_mute = wm8994_mute,
2250 };
2251
2252 struct snd_soc_dai wm8994_dai = {
2253         .name = "WM8994",
2254         .playback = {
2255                 .stream_name = "Playback",
2256                 .channels_min = 1,
2257                 .channels_max = 2,
2258                 .rates = WM8994_RATES,
2259                 .formats = WM8994_FORMATS,
2260         },
2261         .capture = {
2262                 .stream_name = "Capture",
2263                 .channels_min = 2,
2264                 .channels_max = 2,
2265                 .rates = WM8994_RATES,
2266                 .formats = WM8994_FORMATS,
2267          },
2268         .ops = &wm8994_ops,
2269         .symmetric_rates = 1,
2270 };
2271 EXPORT_SYMBOL_GPL(wm8994_dai);
2272
2273 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
2274 {
2275         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2276         struct snd_soc_codec *codec = socdev->card->codec;
2277         DBG("Enter::%s----line->%d\n",__FUNCTION__,__LINE__);
2278         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2279         wm8994_reset();
2280         mdelay(50);
2281         return 0;
2282 }
2283
2284 static int wm8994_resume(struct platform_device *pdev)
2285 {
2286         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2287         struct snd_soc_codec *codec = socdev->card->codec;
2288         int i;
2289         u8 data[2];
2290         u16 *cache = codec->reg_cache;
2291         wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
2292         DBG("Enter::%s----line->%d\n",__FUNCTION__,__LINE__);
2293         /* Sync reg_cache with the hardware */
2294         for (i = 0; i < WM8994_NUM_REG; i++) {
2295                 if (i == WM8994_RESET)
2296                         continue;
2297                 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
2298                 data[1] = cache[i] & 0x00ff;
2299                 codec->hw_write(codec->control_data, data, 2);
2300         }
2301
2302         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2303         if(wm8994_mode<=wm8994_AP_to_Speakers)
2304         {
2305                 wm8994_fnc_ptr+=wm8994_mode;
2306                 (*wm8994_fnc_ptr)() ;
2307         }
2308         else
2309         {
2310                 wm8994_fnc_ptr+=wm8994_mode;
2311                 (*wm8994_fnc_ptr)() ;
2312                 printk("%s----line->%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
2313         }
2314
2315         return 0;
2316 }
2317
2318 static struct snd_soc_codec *wm8994_codec;
2319
2320 static int wm8994_probe(struct platform_device *pdev)
2321 {
2322         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2323         struct snd_soc_codec *codec;
2324         int ret = 0;
2325
2326         if (wm8994_codec == NULL) {
2327                 dev_err(&pdev->dev, "Codec device not registered\n");
2328                 return -ENODEV;
2329         }
2330
2331         socdev->card->codec = wm8994_codec;
2332         codec = wm8994_codec;
2333
2334         /* register pcms */
2335         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2336         if (ret < 0) {
2337                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2338                 goto pcm_err;
2339         }
2340
2341         snd_soc_add_controls(codec, wm8994_snd_controls,
2342                                 ARRAY_SIZE(wm8994_snd_controls));
2343         snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
2344                                   ARRAY_SIZE(wm8994_dapm_widgets));
2345         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
2346         snd_soc_dapm_new_widgets(codec);
2347
2348         ret = snd_soc_init_card(socdev);
2349         if (ret < 0) {
2350                 dev_err(codec->dev, "failed to register card: %d\n", ret);
2351                 goto card_err;
2352         }
2353
2354         return ret;
2355
2356 card_err:
2357         snd_soc_free_pcms(socdev);
2358         snd_soc_dapm_free(socdev);
2359 pcm_err:
2360         return ret;
2361 }
2362
2363 static int wm8994_remove(struct platform_device *pdev)
2364 {
2365         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2366
2367         snd_soc_free_pcms(socdev);
2368         snd_soc_dapm_free(socdev);
2369
2370         return 0;
2371 }
2372
2373 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
2374         .probe =        wm8994_probe,
2375         .remove =       wm8994_remove,
2376         .suspend =      wm8994_suspend,
2377         .resume =       wm8994_resume,
2378 };
2379 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
2380
2381 static int wm8994_register(struct wm8994_priv *wm8994,
2382                            enum snd_soc_control_type control)
2383 {
2384         struct snd_soc_codec *codec = &wm8994->codec;
2385         int ret;
2386         u16 reg;
2387
2388         /*************text----------cjq**************/
2389         DBG("\n\n\nEnter::%s----line->%d-- WM8994 test begin\n",__FUNCTION__,__LINE__);
2390         AP_to_Headset();
2391         //HandsetMIC_to_Baseband_to_Headset();
2392         DBG("Enter::%s----line->%d-- WM8994 test end\n\n\n\n",__FUNCTION__,__LINE__);
2393
2394         if (wm8994_codec) {
2395                 dev_err(codec->dev, "Another WM8994 is registered\n");
2396                 ret = -EINVAL;
2397                 goto err;
2398         }
2399
2400         mutex_init(&codec->mutex);
2401         INIT_LIST_HEAD(&codec->dapm_widgets);
2402         INIT_LIST_HEAD(&codec->dapm_paths);
2403
2404         codec->private_data = wm8994;
2405         codec->name = "WM8994";
2406         codec->owner = THIS_MODULE;
2407         codec->dai = &wm8994_dai;
2408         codec->num_dai = 1;
2409         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
2410         codec->reg_cache = &wm8994->reg_cache;
2411         codec->bias_level = SND_SOC_BIAS_OFF;
2412         codec->set_bias_level = wm8994_set_bias_level;
2413
2414         memcpy(codec->reg_cache, wm8994_reg,
2415                sizeof(wm8994_reg));
2416
2417         ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
2418         if (ret < 0) {
2419                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2420                 goto err;
2421         }
2422
2423         ret = 0;//wm8994_reset(); cjq
2424         if (ret < 0) {
2425                 dev_err(codec->dev, "Failed to issue reset\n");
2426                 goto err;
2427         }
2428 #if 1
2429                 /*disable speaker */
2430                 gpio_request(RK2818_PIN_PF7, "WM8994");
2431                 rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_GPIO1_A3B7);
2432                 gpio_direction_output(RK2818_PIN_PF7,GPIO_HIGH);
2433
2434 #endif
2435         /* set the update bits (we always update left then right) */
2436         reg = snd_soc_read(codec, WM8994_RADC);
2437         snd_soc_write(codec, WM8994_RADC, reg | 0x100);
2438         reg = snd_soc_read(codec, WM8994_RDAC);
2439         snd_soc_write(codec, WM8994_RDAC, reg | 0x0100);
2440         reg = snd_soc_read(codec, WM8994_ROUT1V);
2441         snd_soc_write(codec, WM8994_ROUT1V, reg | 0x0100);
2442         reg = snd_soc_read(codec, WM8994_ROUT2V);
2443         snd_soc_write(codec, WM8994_ROUT2V, reg | 0x0100);
2444         reg = snd_soc_read(codec, WM8994_RINVOL);
2445         snd_soc_write(codec, WM8994_RINVOL, reg | 0x0100);
2446
2447         snd_soc_write(codec, WM8994_LOUTM1, 0x120);
2448         snd_soc_write(codec, WM8994_ROUTM2, 0x120);
2449         snd_soc_write(codec, WM8994_LOUTM2, 0x0070);
2450         snd_soc_write(codec, WM8994_ROUTM1, 0x0070);
2451
2452         snd_soc_write(codec, WM8994_LOUT1V, 0x017f);
2453         snd_soc_write(codec, WM8994_ROUT1V, 0x017f);
2454         snd_soc_write(codec, WM8994_LDAC, 0xff);
2455         snd_soc_write(codec, WM8994_RDAC, 0x1ff);//vol set
2456
2457         snd_soc_write(codec, WM8994_SRATE,0x100);  ///SET MCLK/8
2458         snd_soc_write(codec, WM8994_PWR1, 0x1cc);  ///(0x80|0x40|0x20|0x08|0x04|0x10|0x02));
2459         snd_soc_write(codec, WM8994_PWR2, 0x1e0);  //power r l out1
2460
2461
2462         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
2463
2464         wm8994_dai.dev = codec->dev;
2465
2466         wm8994_codec = codec;
2467
2468         ret = snd_soc_register_codec(codec);
2469         if (ret != 0) {
2470                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2471                 goto err;
2472         }
2473
2474         ret = snd_soc_register_dai(&wm8994_dai);
2475         if (ret != 0) {
2476                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2477                 snd_soc_unregister_codec(codec);
2478                 goto err_codec;
2479         }
2480         return 0;
2481
2482 err_codec:
2483         snd_soc_unregister_codec(codec);
2484 err:
2485         kfree(wm8994);
2486         return ret;
2487 }
2488
2489 static void wm8994_unregister(struct wm8994_priv *wm8994)
2490 {
2491         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
2492         snd_soc_unregister_dai(&wm8994_dai);
2493         snd_soc_unregister_codec(&wm8994->codec);
2494         kfree(wm8994);
2495         wm8994_codec = NULL;
2496 }
2497
2498 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2499 static int wm8994_i2c_probe(struct i2c_client *i2c,
2500                             const struct i2c_device_id *id)
2501 {
2502         struct wm8994_priv *wm8994;
2503         struct snd_soc_codec *codec;
2504         wm8994_client=i2c;
2505         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2506         if (wm8994 == NULL)
2507                 return -ENOMEM;
2508
2509         codec = &wm8994->codec;
2510
2511         i2c_set_clientdata(i2c, wm8994);
2512         codec->control_data = i2c;
2513
2514         codec->dev = &i2c->dev;
2515
2516         return wm8994_register(wm8994, SND_SOC_I2C);
2517 }
2518
2519 static int wm8994_i2c_remove(struct i2c_client *client)
2520 {
2521         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
2522         wm8994_unregister(wm8994);
2523         return 0;
2524 }
2525
2526 #ifdef CONFIG_PM
2527 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
2528 {
2529         return snd_soc_suspend_device(&client->dev);
2530 }
2531
2532 static int wm8994_i2c_resume(struct i2c_client *client)
2533 {
2534         return snd_soc_resume_device(&client->dev);
2535 }
2536 #else
2537 #define wm8994_i2c_suspend NULL
2538 #define wm8994_i2c_resume NULL
2539 #endif
2540
2541 static const struct i2c_device_id wm8994_i2c_id[] = {
2542         { "wm8994", 0 },
2543         { }
2544 };
2545 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
2546
2547 static struct i2c_driver wm8994_i2c_driver = {
2548         .driver = {
2549                 .name = "WM8994",
2550                 .owner = THIS_MODULE,
2551         },
2552         .probe = wm8994_i2c_probe,
2553         .remove = wm8994_i2c_remove,
2554         .suspend = wm8994_i2c_suspend,
2555         .resume = wm8994_i2c_resume,
2556         .id_table = wm8994_i2c_id,
2557 };
2558
2559 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
2560 {
2561         int ret;
2562         struct i2c_adapter *adap = client->adapter;
2563         struct i2c_msg msg;
2564         char tx_buf[4];
2565
2566         memcpy(tx_buf, reg, 2);
2567         memcpy(tx_buf+2, data, 2);
2568         msg.addr = client->addr;
2569         msg.buf = tx_buf;
2570         msg.len = 4;
2571         msg.flags = client->flags;
2572         msg.scl_rate = scl_rate;
2573
2574         ret = i2c_transfer(adap, &msg, 1);
2575
2576         return ret;
2577 }
2578
2579 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
2580 {
2581         int ret;
2582         struct i2c_adapter *adap = client->adapter;
2583         struct i2c_msg msgs[2];
2584
2585         msgs[0].addr = client->addr;
2586         msgs[0].buf = (char *)reg;
2587         msgs[0].flags = client->flags;
2588         msgs[0].len = 2;
2589         msgs[0].scl_rate = scl_rate;
2590
2591         msgs[1].addr = client->addr;
2592         msgs[1].buf = (char *)buf;
2593         msgs[1].flags = client->flags | I2C_M_RD;
2594         msgs[1].len = 2;
2595         msgs[1].scl_rate = scl_rate;
2596
2597         ret = i2c_transfer(adap, msgs, 2);
2598
2599         return ret;
2600 }
2601
2602 #endif
2603
2604 #if defined(CONFIG_SPI_MASTER)
2605 static int __devinit wm8994_spi_probe(struct spi_device *spi)
2606 {
2607         struct wm8994_priv *wm8994;
2608         struct snd_soc_codec *codec;
2609
2610         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2611         if (wm8994 == NULL)
2612                 return -ENOMEM;
2613
2614         codec = &wm8994->codec;
2615         codec->control_data = spi;
2616         codec->dev = &spi->dev;
2617
2618         dev_set_drvdata(&spi->dev, wm8994);
2619
2620         return wm8994_register(wm8994, SND_SOC_SPI);
2621 }
2622
2623 static int __devexit wm8994_spi_remove(struct spi_device *spi)
2624 {
2625         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
2626
2627         wm8994_unregister(wm8994);
2628
2629         return 0;
2630 }
2631
2632 #ifdef CONFIG_PM
2633 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
2634 {
2635         return snd_soc_suspend_device(&spi->dev);
2636 }
2637
2638 static int wm8994_spi_resume(struct spi_device *spi)
2639 {
2640         return snd_soc_resume_device(&spi->dev);
2641 }
2642 #else
2643 #define wm8994_spi_suspend NULL
2644 #define wm8994_spi_resume NULL
2645 #endif
2646
2647 static struct spi_driver wm8994_spi_driver = {
2648         .driver = {
2649                 .name   = "wm8994",
2650                 .bus    = &spi_bus_type,
2651                 .owner  = THIS_MODULE,
2652         },
2653         .probe          = wm8994_spi_probe,
2654         .remove         = __devexit_p(wm8994_spi_remove),
2655         .suspend        = wm8994_spi_suspend,
2656         .resume         = wm8994_spi_resume,
2657 };
2658 #endif
2659
2660 static int __init wm8994_modinit(void)
2661 {
2662         int ret;
2663
2664 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2665         ret = i2c_add_driver(&wm8994_i2c_driver);
2666         if (ret != 0)
2667                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
2668 #endif
2669 #if defined(CONFIG_SPI_MASTER)
2670         ret = spi_register_driver(&wm8994_spi_driver);
2671         if (ret != 0)
2672                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
2673 #endif
2674         return ret;
2675 }
2676 module_init(wm8994_modinit);
2677
2678 static void __exit wm8994_exit(void)
2679 {
2680 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2681         i2c_del_driver(&wm8994_i2c_driver);
2682 #endif
2683 #if defined(CONFIG_SPI_MASTER)
2684         spi_unregister_driver(&wm8994_spi_driver);
2685 #endif
2686 }
2687 module_exit(wm8994_exit);
2688
2689
2690 MODULE_DESCRIPTION("ASoC WM8994 driver");
2691 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2692 MODULE_LICENSE("GPL");
2693