2 * wm8996.c - WM8996 audio codec interface
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <trace/events/asoc.h>
35 #include <sound/wm8996.h>
45 #define WM8996_NUM_SUPPLIES 3
46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
54 struct regmap *regmap;
55 struct snd_soc_codec *codec;
66 struct completion fll_lock;
69 struct completion dcs_done;
74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
78 struct wm8996_pdata pdata;
80 int rx_rate[WM8996_AIFS];
81 int bclk_rate[WM8996_AIFS];
83 /* Platform dependant ReTune mobile configuration */
84 int num_retune_mobile_texts;
85 const char **retune_mobile_texts;
86 int retune_mobile_cfg[2];
87 struct soc_enum retune_mobile_enum;
89 struct snd_soc_jack *jack;
93 wm8996_polarity_fn polarity_cb;
96 struct gpio_chip gpio_chip;
100 /* We can't use the same notifier block for more than one supply and
101 * there's no way I can see to get from a callback to the caller
102 * except container_of().
104 #define WM8996_REGULATOR_EVENT(n) \
105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
106 unsigned long event, void *data) \
108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
110 if (event & REGULATOR_EVENT_DISABLE) { \
111 regcache_mark_dirty(wm8996->regmap); \
116 WM8996_REGULATOR_EVENT(0)
117 WM8996_REGULATOR_EVENT(1)
118 WM8996_REGULATOR_EVENT(2)
120 static struct reg_default wm8996_reg[] = {
121 { WM8996_POWER_MANAGEMENT_1, 0x0 },
122 { WM8996_POWER_MANAGEMENT_2, 0x0 },
123 { WM8996_POWER_MANAGEMENT_3, 0x0 },
124 { WM8996_POWER_MANAGEMENT_4, 0x0 },
125 { WM8996_POWER_MANAGEMENT_5, 0x0 },
126 { WM8996_POWER_MANAGEMENT_6, 0x0 },
127 { WM8996_POWER_MANAGEMENT_7, 0x10 },
128 { WM8996_POWER_MANAGEMENT_8, 0x0 },
129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
131 { WM8996_LINE_INPUT_CONTROL, 0x0 },
132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
142 { WM8996_MICBIAS_1, 0x39 },
143 { WM8996_MICBIAS_2, 0x39 },
144 { WM8996_LDO_1, 0x3 },
145 { WM8996_LDO_2, 0x13 },
146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
148 { WM8996_HEADPHONE_DETECT_1, 0x20 },
149 { WM8996_HEADPHONE_DETECT_2, 0x0 },
150 { WM8996_MIC_DETECT_1, 0x7600 },
151 { WM8996_MIC_DETECT_2, 0xbf },
152 { WM8996_CHARGE_PUMP_1, 0x1f25 },
153 { WM8996_CHARGE_PUMP_2, 0xab19 },
154 { WM8996_DC_SERVO_1, 0x0 },
155 { WM8996_DC_SERVO_3, 0x0 },
156 { WM8996_DC_SERVO_5, 0x2a2a },
157 { WM8996_DC_SERVO_6, 0x0 },
158 { WM8996_DC_SERVO_7, 0x0 },
159 { WM8996_ANALOGUE_HP_1, 0x0 },
160 { WM8996_ANALOGUE_HP_2, 0x0 },
161 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
164 { WM8996_AIF_CLOCKING_1, 0x0 },
165 { WM8996_AIF_CLOCKING_2, 0x0 },
166 { WM8996_CLOCKING_1, 0x10 },
167 { WM8996_CLOCKING_2, 0x0 },
168 { WM8996_AIF_RATE, 0x83 },
169 { WM8996_FLL_CONTROL_1, 0x0 },
170 { WM8996_FLL_CONTROL_2, 0x0 },
171 { WM8996_FLL_CONTROL_3, 0x0 },
172 { WM8996_FLL_CONTROL_4, 0x5dc0 },
173 { WM8996_FLL_CONTROL_5, 0xc84 },
174 { WM8996_FLL_EFS_1, 0x0 },
175 { WM8996_FLL_EFS_2, 0x2 },
176 { WM8996_AIF1_CONTROL, 0x0 },
177 { WM8996_AIF1_BCLK, 0x0 },
178 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
179 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
180 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
181 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
198 { WM8996_AIF1TX_TEST, 0x7 },
199 { WM8996_AIF2_CONTROL, 0x0 },
200 { WM8996_AIF2_BCLK, 0x0 },
201 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
202 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
203 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
204 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
213 { WM8996_AIF2TX_TEST, 0x1 },
214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
218 { WM8996_DSP1_TX_FILTERS, 0x2000 },
219 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
220 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
221 { WM8996_DSP1_DRC_1, 0x98 },
222 { WM8996_DSP1_DRC_2, 0x845 },
223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
247 { WM8996_DSP2_TX_FILTERS, 0x2000 },
248 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
249 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
250 { WM8996_DSP2_DRC_1, 0x98 },
251 { WM8996_DSP2_DRC_2, 0x845 },
252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
283 { WM8996_DAC_SOFTMUTE, 0x0 },
284 { WM8996_OVERSAMPLING, 0xd },
285 { WM8996_SIDETONE, 0x1040 },
286 { WM8996_GPIO_1, 0xa101 },
287 { WM8996_GPIO_2, 0xa101 },
288 { WM8996_GPIO_3, 0xa101 },
289 { WM8996_GPIO_4, 0xa101 },
290 { WM8996_GPIO_5, 0xa101 },
291 { WM8996_PULL_CONTROL_1, 0x0 },
292 { WM8996_PULL_CONTROL_2, 0x140 },
293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
295 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
299 { WM8996_WRITE_SEQUENCER_0, 0x1 },
300 { WM8996_WRITE_SEQUENCER_1, 0x1 },
301 { WM8996_WRITE_SEQUENCER_3, 0x6 },
302 { WM8996_WRITE_SEQUENCER_4, 0x40 },
303 { WM8996_WRITE_SEQUENCER_5, 0x1 },
304 { WM8996_WRITE_SEQUENCER_6, 0xf },
305 { WM8996_WRITE_SEQUENCER_7, 0x6 },
306 { WM8996_WRITE_SEQUENCER_8, 0x1 },
307 { WM8996_WRITE_SEQUENCER_9, 0x3 },
308 { WM8996_WRITE_SEQUENCER_10, 0x104 },
309 { WM8996_WRITE_SEQUENCER_12, 0x60 },
310 { WM8996_WRITE_SEQUENCER_13, 0x11 },
311 { WM8996_WRITE_SEQUENCER_14, 0x401 },
312 { WM8996_WRITE_SEQUENCER_16, 0x50 },
313 { WM8996_WRITE_SEQUENCER_17, 0x3 },
314 { WM8996_WRITE_SEQUENCER_18, 0x100 },
315 { WM8996_WRITE_SEQUENCER_20, 0x51 },
316 { WM8996_WRITE_SEQUENCER_21, 0x3 },
317 { WM8996_WRITE_SEQUENCER_22, 0x104 },
318 { WM8996_WRITE_SEQUENCER_23, 0xa },
319 { WM8996_WRITE_SEQUENCER_24, 0x60 },
320 { WM8996_WRITE_SEQUENCER_25, 0x3b },
321 { WM8996_WRITE_SEQUENCER_26, 0x502 },
322 { WM8996_WRITE_SEQUENCER_27, 0x100 },
323 { WM8996_WRITE_SEQUENCER_28, 0x2fff },
324 { WM8996_WRITE_SEQUENCER_32, 0x2fff },
325 { WM8996_WRITE_SEQUENCER_36, 0x2fff },
326 { WM8996_WRITE_SEQUENCER_40, 0x2fff },
327 { WM8996_WRITE_SEQUENCER_44, 0x2fff },
328 { WM8996_WRITE_SEQUENCER_48, 0x2fff },
329 { WM8996_WRITE_SEQUENCER_52, 0x2fff },
330 { WM8996_WRITE_SEQUENCER_56, 0x2fff },
331 { WM8996_WRITE_SEQUENCER_60, 0x2fff },
332 { WM8996_WRITE_SEQUENCER_64, 0x1 },
333 { WM8996_WRITE_SEQUENCER_65, 0x1 },
334 { WM8996_WRITE_SEQUENCER_67, 0x6 },
335 { WM8996_WRITE_SEQUENCER_68, 0x40 },
336 { WM8996_WRITE_SEQUENCER_69, 0x1 },
337 { WM8996_WRITE_SEQUENCER_70, 0xf },
338 { WM8996_WRITE_SEQUENCER_71, 0x6 },
339 { WM8996_WRITE_SEQUENCER_72, 0x1 },
340 { WM8996_WRITE_SEQUENCER_73, 0x3 },
341 { WM8996_WRITE_SEQUENCER_74, 0x104 },
342 { WM8996_WRITE_SEQUENCER_76, 0x60 },
343 { WM8996_WRITE_SEQUENCER_77, 0x11 },
344 { WM8996_WRITE_SEQUENCER_78, 0x401 },
345 { WM8996_WRITE_SEQUENCER_80, 0x50 },
346 { WM8996_WRITE_SEQUENCER_81, 0x3 },
347 { WM8996_WRITE_SEQUENCER_82, 0x100 },
348 { WM8996_WRITE_SEQUENCER_84, 0x60 },
349 { WM8996_WRITE_SEQUENCER_85, 0x3b },
350 { WM8996_WRITE_SEQUENCER_86, 0x502 },
351 { WM8996_WRITE_SEQUENCER_87, 0x100 },
352 { WM8996_WRITE_SEQUENCER_88, 0x2fff },
353 { WM8996_WRITE_SEQUENCER_92, 0x2fff },
354 { WM8996_WRITE_SEQUENCER_96, 0x2fff },
355 { WM8996_WRITE_SEQUENCER_100, 0x2fff },
356 { WM8996_WRITE_SEQUENCER_104, 0x2fff },
357 { WM8996_WRITE_SEQUENCER_108, 0x2fff },
358 { WM8996_WRITE_SEQUENCER_112, 0x2fff },
359 { WM8996_WRITE_SEQUENCER_116, 0x2fff },
360 { WM8996_WRITE_SEQUENCER_120, 0x2fff },
361 { WM8996_WRITE_SEQUENCER_124, 0x2fff },
362 { WM8996_WRITE_SEQUENCER_128, 0x1 },
363 { WM8996_WRITE_SEQUENCER_129, 0x1 },
364 { WM8996_WRITE_SEQUENCER_131, 0x6 },
365 { WM8996_WRITE_SEQUENCER_132, 0x40 },
366 { WM8996_WRITE_SEQUENCER_133, 0x1 },
367 { WM8996_WRITE_SEQUENCER_134, 0xf },
368 { WM8996_WRITE_SEQUENCER_135, 0x6 },
369 { WM8996_WRITE_SEQUENCER_136, 0x1 },
370 { WM8996_WRITE_SEQUENCER_137, 0x3 },
371 { WM8996_WRITE_SEQUENCER_138, 0x106 },
372 { WM8996_WRITE_SEQUENCER_140, 0x61 },
373 { WM8996_WRITE_SEQUENCER_141, 0x11 },
374 { WM8996_WRITE_SEQUENCER_142, 0x401 },
375 { WM8996_WRITE_SEQUENCER_144, 0x50 },
376 { WM8996_WRITE_SEQUENCER_145, 0x3 },
377 { WM8996_WRITE_SEQUENCER_146, 0x102 },
378 { WM8996_WRITE_SEQUENCER_148, 0x51 },
379 { WM8996_WRITE_SEQUENCER_149, 0x3 },
380 { WM8996_WRITE_SEQUENCER_150, 0x106 },
381 { WM8996_WRITE_SEQUENCER_151, 0xa },
382 { WM8996_WRITE_SEQUENCER_152, 0x61 },
383 { WM8996_WRITE_SEQUENCER_153, 0x3b },
384 { WM8996_WRITE_SEQUENCER_154, 0x502 },
385 { WM8996_WRITE_SEQUENCER_155, 0x100 },
386 { WM8996_WRITE_SEQUENCER_156, 0x2fff },
387 { WM8996_WRITE_SEQUENCER_160, 0x2fff },
388 { WM8996_WRITE_SEQUENCER_164, 0x2fff },
389 { WM8996_WRITE_SEQUENCER_168, 0x2fff },
390 { WM8996_WRITE_SEQUENCER_172, 0x2fff },
391 { WM8996_WRITE_SEQUENCER_176, 0x2fff },
392 { WM8996_WRITE_SEQUENCER_180, 0x2fff },
393 { WM8996_WRITE_SEQUENCER_184, 0x2fff },
394 { WM8996_WRITE_SEQUENCER_188, 0x2fff },
395 { WM8996_WRITE_SEQUENCER_192, 0x1 },
396 { WM8996_WRITE_SEQUENCER_193, 0x1 },
397 { WM8996_WRITE_SEQUENCER_195, 0x6 },
398 { WM8996_WRITE_SEQUENCER_196, 0x40 },
399 { WM8996_WRITE_SEQUENCER_197, 0x1 },
400 { WM8996_WRITE_SEQUENCER_198, 0xf },
401 { WM8996_WRITE_SEQUENCER_199, 0x6 },
402 { WM8996_WRITE_SEQUENCER_200, 0x1 },
403 { WM8996_WRITE_SEQUENCER_201, 0x3 },
404 { WM8996_WRITE_SEQUENCER_202, 0x106 },
405 { WM8996_WRITE_SEQUENCER_204, 0x61 },
406 { WM8996_WRITE_SEQUENCER_205, 0x11 },
407 { WM8996_WRITE_SEQUENCER_206, 0x401 },
408 { WM8996_WRITE_SEQUENCER_208, 0x50 },
409 { WM8996_WRITE_SEQUENCER_209, 0x3 },
410 { WM8996_WRITE_SEQUENCER_210, 0x102 },
411 { WM8996_WRITE_SEQUENCER_212, 0x61 },
412 { WM8996_WRITE_SEQUENCER_213, 0x3b },
413 { WM8996_WRITE_SEQUENCER_214, 0x502 },
414 { WM8996_WRITE_SEQUENCER_215, 0x100 },
415 { WM8996_WRITE_SEQUENCER_216, 0x2fff },
416 { WM8996_WRITE_SEQUENCER_220, 0x2fff },
417 { WM8996_WRITE_SEQUENCER_224, 0x2fff },
418 { WM8996_WRITE_SEQUENCER_228, 0x2fff },
419 { WM8996_WRITE_SEQUENCER_232, 0x2fff },
420 { WM8996_WRITE_SEQUENCER_236, 0x2fff },
421 { WM8996_WRITE_SEQUENCER_240, 0x2fff },
422 { WM8996_WRITE_SEQUENCER_244, 0x2fff },
423 { WM8996_WRITE_SEQUENCER_248, 0x2fff },
424 { WM8996_WRITE_SEQUENCER_252, 0x2fff },
425 { WM8996_WRITE_SEQUENCER_256, 0x60 },
426 { WM8996_WRITE_SEQUENCER_258, 0x601 },
427 { WM8996_WRITE_SEQUENCER_260, 0x50 },
428 { WM8996_WRITE_SEQUENCER_262, 0x100 },
429 { WM8996_WRITE_SEQUENCER_264, 0x1 },
430 { WM8996_WRITE_SEQUENCER_266, 0x104 },
431 { WM8996_WRITE_SEQUENCER_267, 0x100 },
432 { WM8996_WRITE_SEQUENCER_268, 0x2fff },
433 { WM8996_WRITE_SEQUENCER_272, 0x2fff },
434 { WM8996_WRITE_SEQUENCER_276, 0x2fff },
435 { WM8996_WRITE_SEQUENCER_280, 0x2fff },
436 { WM8996_WRITE_SEQUENCER_284, 0x2fff },
437 { WM8996_WRITE_SEQUENCER_288, 0x2fff },
438 { WM8996_WRITE_SEQUENCER_292, 0x2fff },
439 { WM8996_WRITE_SEQUENCER_296, 0x2fff },
440 { WM8996_WRITE_SEQUENCER_300, 0x2fff },
441 { WM8996_WRITE_SEQUENCER_304, 0x2fff },
442 { WM8996_WRITE_SEQUENCER_308, 0x2fff },
443 { WM8996_WRITE_SEQUENCER_312, 0x2fff },
444 { WM8996_WRITE_SEQUENCER_316, 0x2fff },
445 { WM8996_WRITE_SEQUENCER_320, 0x61 },
446 { WM8996_WRITE_SEQUENCER_322, 0x601 },
447 { WM8996_WRITE_SEQUENCER_324, 0x50 },
448 { WM8996_WRITE_SEQUENCER_326, 0x102 },
449 { WM8996_WRITE_SEQUENCER_328, 0x1 },
450 { WM8996_WRITE_SEQUENCER_330, 0x106 },
451 { WM8996_WRITE_SEQUENCER_331, 0x100 },
452 { WM8996_WRITE_SEQUENCER_332, 0x2fff },
453 { WM8996_WRITE_SEQUENCER_336, 0x2fff },
454 { WM8996_WRITE_SEQUENCER_340, 0x2fff },
455 { WM8996_WRITE_SEQUENCER_344, 0x2fff },
456 { WM8996_WRITE_SEQUENCER_348, 0x2fff },
457 { WM8996_WRITE_SEQUENCER_352, 0x2fff },
458 { WM8996_WRITE_SEQUENCER_356, 0x2fff },
459 { WM8996_WRITE_SEQUENCER_360, 0x2fff },
460 { WM8996_WRITE_SEQUENCER_364, 0x2fff },
461 { WM8996_WRITE_SEQUENCER_368, 0x2fff },
462 { WM8996_WRITE_SEQUENCER_372, 0x2fff },
463 { WM8996_WRITE_SEQUENCER_376, 0x2fff },
464 { WM8996_WRITE_SEQUENCER_380, 0x2fff },
465 { WM8996_WRITE_SEQUENCER_384, 0x60 },
466 { WM8996_WRITE_SEQUENCER_386, 0x601 },
467 { WM8996_WRITE_SEQUENCER_388, 0x61 },
468 { WM8996_WRITE_SEQUENCER_390, 0x601 },
469 { WM8996_WRITE_SEQUENCER_392, 0x50 },
470 { WM8996_WRITE_SEQUENCER_394, 0x300 },
471 { WM8996_WRITE_SEQUENCER_396, 0x1 },
472 { WM8996_WRITE_SEQUENCER_398, 0x304 },
473 { WM8996_WRITE_SEQUENCER_400, 0x40 },
474 { WM8996_WRITE_SEQUENCER_402, 0xf },
475 { WM8996_WRITE_SEQUENCER_404, 0x1 },
476 { WM8996_WRITE_SEQUENCER_407, 0x100 },
479 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
480 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
481 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
482 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
483 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
484 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
485 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
486 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
488 static const char *sidetone_hpf_text[] = {
489 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
492 static const struct soc_enum sidetone_hpf =
493 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
495 static const char *hpf_mode_text[] = {
496 "HiFi", "Custom", "Voice"
499 static const struct soc_enum dsp1tx_hpf_mode =
500 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
502 static const struct soc_enum dsp2tx_hpf_mode =
503 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
505 static const char *hpf_cutoff_text[] = {
506 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
509 static const struct soc_enum dsp1tx_hpf_cutoff =
510 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
512 static const struct soc_enum dsp2tx_hpf_cutoff =
513 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
515 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
517 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
518 struct wm8996_pdata *pdata = &wm8996->pdata;
519 int base, best, best_val, save, i, cfg, iface;
521 if (!wm8996->num_retune_mobile_texts)
526 base = WM8996_DSP1_RX_EQ_GAINS_1;
527 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
534 base = WM8996_DSP1_RX_EQ_GAINS_2;
535 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
545 /* Find the version of the currently selected configuration
546 * with the nearest sample rate. */
547 cfg = wm8996->retune_mobile_cfg[block];
550 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
551 if (strcmp(pdata->retune_mobile_cfgs[i].name,
552 wm8996->retune_mobile_texts[cfg]) == 0 &&
553 abs(pdata->retune_mobile_cfgs[i].rate
554 - wm8996->rx_rate[iface]) < best_val) {
556 best_val = abs(pdata->retune_mobile_cfgs[i].rate
557 - wm8996->rx_rate[iface]);
561 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
563 pdata->retune_mobile_cfgs[best].name,
564 pdata->retune_mobile_cfgs[best].rate,
565 wm8996->rx_rate[iface]);
567 /* The EQ will be disabled while reconfiguring it, remember the
568 * current configuration.
570 save = snd_soc_read(codec, base);
571 save &= WM8996_DSP1RX_EQ_ENA;
573 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
574 snd_soc_update_bits(codec, base + i, 0xffff,
575 pdata->retune_mobile_cfgs[best].regs[i]);
577 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
580 /* Icky as hell but saves code duplication */
581 static int wm8996_get_retune_mobile_block(const char *name)
583 if (strcmp(name, "DSP1 EQ Mode") == 0)
585 if (strcmp(name, "DSP2 EQ Mode") == 0)
590 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
591 struct snd_ctl_elem_value *ucontrol)
593 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
594 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
595 struct wm8996_pdata *pdata = &wm8996->pdata;
596 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
597 int value = ucontrol->value.integer.value[0];
602 if (value >= pdata->num_retune_mobile_cfgs)
605 wm8996->retune_mobile_cfg[block] = value;
607 wm8996_set_retune_mobile(codec, block);
612 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
613 struct snd_ctl_elem_value *ucontrol)
615 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
616 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
617 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
619 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
624 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
625 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
626 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
627 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
628 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
630 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
631 0, 5, 24, 0, sidetone_tlv),
632 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
633 0, 5, 24, 0, sidetone_tlv),
634 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
635 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
636 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
638 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
639 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
640 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
641 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
643 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
645 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
646 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
647 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
649 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
651 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
652 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
653 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
655 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
656 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
657 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
659 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
660 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
661 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
663 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
664 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
665 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
666 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
668 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
669 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
670 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
671 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
673 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
674 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
675 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
676 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
678 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
679 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
681 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
682 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
684 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
685 0, threedstereo_tlv),
686 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
687 0, threedstereo_tlv),
689 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
690 8, 0, out_digital_tlv),
691 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
692 8, 0, out_digital_tlv),
694 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
695 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
696 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
697 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
699 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
700 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
701 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
702 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
704 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
706 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
707 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
708 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
709 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
711 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
712 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
714 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
715 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
716 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
717 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
718 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
719 WM8996_DSP1TXR_DRC_ENA),
721 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
722 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
723 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
724 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
725 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
726 WM8996_DSP2TXR_DRC_ENA),
729 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
730 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
732 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
734 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
736 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
738 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
741 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
743 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
745 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
747 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
749 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
753 static void wm8996_bg_enable(struct snd_soc_codec *codec)
755 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
758 if (wm8996->bg_ena == 1) {
759 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
760 WM8996_BG_ENA, WM8996_BG_ENA);
765 static void wm8996_bg_disable(struct snd_soc_codec *codec)
767 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
771 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
775 static int bg_event(struct snd_soc_dapm_widget *w,
776 struct snd_kcontrol *kcontrol, int event)
778 struct snd_soc_codec *codec = w->codec;
782 case SND_SOC_DAPM_PRE_PMU:
783 wm8996_bg_enable(codec);
785 case SND_SOC_DAPM_POST_PMD:
786 wm8996_bg_disable(codec);
796 static int cp_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
802 case SND_SOC_DAPM_POST_PMU:
813 static int rmv_short_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
816 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
818 /* Record which outputs we enabled */
820 case SND_SOC_DAPM_PRE_PMD:
821 wm8996->hpout_pending &= ~w->shift;
823 case SND_SOC_DAPM_PRE_PMU:
824 wm8996->hpout_pending |= w->shift;
834 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
836 struct i2c_client *i2c = to_i2c_client(codec->dev);
837 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
839 unsigned long timeout = 200;
841 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
843 /* Use the interrupt if possible */
846 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
847 msecs_to_jiffies(200));
849 dev_err(codec->dev, "DC servo timed out\n");
856 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
857 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
858 } while (timeout && ret & mask);
861 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
863 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
866 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
867 enum snd_soc_dapm_type event, int subseq)
869 struct snd_soc_codec *codec = container_of(dapm,
870 struct snd_soc_codec, dapm);
871 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
874 /* Complete any pending DC servo starts */
875 if (wm8996->dcs_pending) {
876 dev_dbg(codec->dev, "Starting DC servo for %x\n",
877 wm8996->dcs_pending);
879 /* Trigger a startup sequence */
880 wait_for_dc_servo(codec, wm8996->dcs_pending
881 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
883 wm8996->dcs_pending = 0;
886 if (wm8996->hpout_pending != wm8996->hpout_ena) {
887 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
888 wm8996->hpout_ena, wm8996->hpout_pending);
892 if (wm8996->hpout_pending & HPOUT1L) {
893 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
894 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
896 mask |= WM8996_HPOUT1L_RMV_SHORT |
897 WM8996_HPOUT1L_OUTP |
901 if (wm8996->hpout_pending & HPOUT1R) {
902 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
903 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
905 mask |= WM8996_HPOUT1R_RMV_SHORT |
906 WM8996_HPOUT1R_OUTP |
910 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
914 if (wm8996->hpout_pending & HPOUT2L) {
915 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
916 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
918 mask |= WM8996_HPOUT2L_RMV_SHORT |
919 WM8996_HPOUT2L_OUTP |
923 if (wm8996->hpout_pending & HPOUT2R) {
924 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
925 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
927 mask |= WM8996_HPOUT2R_RMV_SHORT |
928 WM8996_HPOUT2R_OUTP |
932 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
934 wm8996->hpout_ena = wm8996->hpout_pending;
938 static int dcs_start(struct snd_soc_dapm_widget *w,
939 struct snd_kcontrol *kcontrol, int event)
941 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
944 case SND_SOC_DAPM_POST_PMU:
945 wm8996->dcs_pending |= 1 << w->shift;
955 static const char *sidetone_text[] = {
959 static const struct soc_enum left_sidetone_enum =
960 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
962 static const struct snd_kcontrol_new left_sidetone =
963 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
965 static const struct soc_enum right_sidetone_enum =
966 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
968 static const struct snd_kcontrol_new right_sidetone =
969 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
971 static const char *spk_text[] = {
972 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
975 static const struct soc_enum spkl_enum =
976 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
978 static const struct snd_kcontrol_new spkl_mux =
979 SOC_DAPM_ENUM("SPKL", spkl_enum);
981 static const struct soc_enum spkr_enum =
982 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
984 static const struct snd_kcontrol_new spkr_mux =
985 SOC_DAPM_ENUM("SPKR", spkr_enum);
987 static const char *dsp1rx_text[] = {
991 static const struct soc_enum dsp1rx_enum =
992 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
994 static const struct snd_kcontrol_new dsp1rx =
995 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
997 static const char *dsp2rx_text[] = {
1001 static const struct soc_enum dsp2rx_enum =
1002 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
1004 static const struct snd_kcontrol_new dsp2rx =
1005 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1007 static const char *aif2tx_text[] = {
1008 "DSP2", "DSP1", "AIF1"
1011 static const struct soc_enum aif2tx_enum =
1012 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1014 static const struct snd_kcontrol_new aif2tx =
1015 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1017 static const char *inmux_text[] = {
1018 "ADC", "DMIC1", "DMIC2"
1021 static const struct soc_enum in1_enum =
1022 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1024 static const struct snd_kcontrol_new in1_mux =
1025 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1027 static const struct soc_enum in2_enum =
1028 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1030 static const struct snd_kcontrol_new in2_mux =
1031 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1033 static const struct snd_kcontrol_new dac2r_mix[] = {
1034 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1036 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1038 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1039 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1042 static const struct snd_kcontrol_new dac2l_mix[] = {
1043 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1045 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1047 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1048 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1051 static const struct snd_kcontrol_new dac1r_mix[] = {
1052 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1054 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1056 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1057 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1060 static const struct snd_kcontrol_new dac1l_mix[] = {
1061 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1063 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1065 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1066 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1069 static const struct snd_kcontrol_new dsp1txl[] = {
1070 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1072 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1076 static const struct snd_kcontrol_new dsp1txr[] = {
1077 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1079 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1083 static const struct snd_kcontrol_new dsp2txl[] = {
1084 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1086 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1090 static const struct snd_kcontrol_new dsp2txr[] = {
1091 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1093 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1098 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1099 SND_SOC_DAPM_INPUT("IN1LN"),
1100 SND_SOC_DAPM_INPUT("IN1LP"),
1101 SND_SOC_DAPM_INPUT("IN1RN"),
1102 SND_SOC_DAPM_INPUT("IN1RP"),
1104 SND_SOC_DAPM_INPUT("IN2LN"),
1105 SND_SOC_DAPM_INPUT("IN2LP"),
1106 SND_SOC_DAPM_INPUT("IN2RN"),
1107 SND_SOC_DAPM_INPUT("IN2RP"),
1109 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1110 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1112 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20),
1113 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1114 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1115 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1116 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
1117 SND_SOC_DAPM_POST_PMU),
1118 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1119 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1120 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1121 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1122 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
1123 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1124 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1126 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1127 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1129 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1130 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1131 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1132 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
1134 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1135 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1137 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1138 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1139 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1140 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1142 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1143 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1145 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1146 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1148 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1149 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1150 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1151 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1153 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1154 dsp2txl, ARRAY_SIZE(dsp2txl)),
1155 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1156 dsp2txr, ARRAY_SIZE(dsp2txr)),
1157 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1158 dsp1txl, ARRAY_SIZE(dsp1txl)),
1159 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1160 dsp1txr, ARRAY_SIZE(dsp1txr)),
1162 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1163 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1164 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1165 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1166 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1167 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1168 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1169 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1171 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1172 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1173 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1174 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1176 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
1177 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
1179 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
1180 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
1182 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1183 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1184 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1185 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1186 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1187 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1189 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1190 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1191 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1192 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1193 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1194 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1196 /* We route as stereo pairs so define some dummy widgets to squash
1197 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1198 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1199 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1200 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1201 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1202 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1204 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1205 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1206 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1208 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1209 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1210 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1211 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1213 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1214 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1215 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1216 SND_SOC_DAPM_POST_PMU),
1217 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1219 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1221 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1222 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1223 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1224 SND_SOC_DAPM_POST_PMU),
1225 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1227 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1229 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1230 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1231 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1232 SND_SOC_DAPM_POST_PMU),
1233 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1235 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1237 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1238 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1239 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1240 SND_SOC_DAPM_POST_PMU),
1241 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1243 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1245 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1246 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1247 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1248 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1249 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1252 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1253 { "AIFCLK", NULL, "SYSCLK" },
1254 { "SYSDSPCLK", NULL, "SYSCLK" },
1255 { "Charge Pump", NULL, "SYSCLK" },
1256 { "Charge Pump", NULL, "CPVDD" },
1258 { "MICB1", NULL, "LDO2" },
1259 { "MICB1", NULL, "MICB1 Audio" },
1260 { "MICB1", NULL, "Bandgap" },
1261 { "MICB2", NULL, "LDO2" },
1262 { "MICB2", NULL, "MICB2 Audio" },
1263 { "MICB2", NULL, "Bandgap" },
1265 { "AIF1RX0", NULL, "AIF1 Playback" },
1266 { "AIF1RX1", NULL, "AIF1 Playback" },
1267 { "AIF1RX2", NULL, "AIF1 Playback" },
1268 { "AIF1RX3", NULL, "AIF1 Playback" },
1269 { "AIF1RX4", NULL, "AIF1 Playback" },
1270 { "AIF1RX5", NULL, "AIF1 Playback" },
1272 { "AIF2RX0", NULL, "AIF2 Playback" },
1273 { "AIF2RX1", NULL, "AIF2 Playback" },
1275 { "AIF1 Capture", NULL, "AIF1TX0" },
1276 { "AIF1 Capture", NULL, "AIF1TX1" },
1277 { "AIF1 Capture", NULL, "AIF1TX2" },
1278 { "AIF1 Capture", NULL, "AIF1TX3" },
1279 { "AIF1 Capture", NULL, "AIF1TX4" },
1280 { "AIF1 Capture", NULL, "AIF1TX5" },
1282 { "AIF2 Capture", NULL, "AIF2TX0" },
1283 { "AIF2 Capture", NULL, "AIF2TX1" },
1285 { "IN1L PGA", NULL, "IN2LN" },
1286 { "IN1L PGA", NULL, "IN2LP" },
1287 { "IN1L PGA", NULL, "IN1LN" },
1288 { "IN1L PGA", NULL, "IN1LP" },
1289 { "IN1L PGA", NULL, "Bandgap" },
1291 { "IN1R PGA", NULL, "IN2RN" },
1292 { "IN1R PGA", NULL, "IN2RP" },
1293 { "IN1R PGA", NULL, "IN1RN" },
1294 { "IN1R PGA", NULL, "IN1RP" },
1295 { "IN1R PGA", NULL, "Bandgap" },
1297 { "ADCL", NULL, "IN1L PGA" },
1299 { "ADCR", NULL, "IN1R PGA" },
1301 { "DMIC1L", NULL, "DMIC1DAT" },
1302 { "DMIC1R", NULL, "DMIC1DAT" },
1303 { "DMIC2L", NULL, "DMIC2DAT" },
1304 { "DMIC2R", NULL, "DMIC2DAT" },
1306 { "DMIC2L", NULL, "DMIC2" },
1307 { "DMIC2R", NULL, "DMIC2" },
1308 { "DMIC1L", NULL, "DMIC1" },
1309 { "DMIC1R", NULL, "DMIC1" },
1311 { "IN1L Mux", "ADC", "ADCL" },
1312 { "IN1L Mux", "DMIC1", "DMIC1L" },
1313 { "IN1L Mux", "DMIC2", "DMIC2L" },
1315 { "IN1R Mux", "ADC", "ADCR" },
1316 { "IN1R Mux", "DMIC1", "DMIC1R" },
1317 { "IN1R Mux", "DMIC2", "DMIC2R" },
1319 { "IN2L Mux", "ADC", "ADCL" },
1320 { "IN2L Mux", "DMIC1", "DMIC1L" },
1321 { "IN2L Mux", "DMIC2", "DMIC2L" },
1323 { "IN2R Mux", "ADC", "ADCR" },
1324 { "IN2R Mux", "DMIC1", "DMIC1R" },
1325 { "IN2R Mux", "DMIC2", "DMIC2R" },
1327 { "Left Sidetone", "IN1", "IN1L Mux" },
1328 { "Left Sidetone", "IN2", "IN2L Mux" },
1330 { "Right Sidetone", "IN1", "IN1R Mux" },
1331 { "Right Sidetone", "IN2", "IN2R Mux" },
1333 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1334 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1336 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1337 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1339 { "AIF1TX0", NULL, "DSP1TXL" },
1340 { "AIF1TX1", NULL, "DSP1TXR" },
1341 { "AIF1TX2", NULL, "DSP2TXL" },
1342 { "AIF1TX3", NULL, "DSP2TXR" },
1343 { "AIF1TX4", NULL, "AIF2RX0" },
1344 { "AIF1TX5", NULL, "AIF2RX1" },
1346 { "AIF1RX0", NULL, "AIFCLK" },
1347 { "AIF1RX1", NULL, "AIFCLK" },
1348 { "AIF1RX2", NULL, "AIFCLK" },
1349 { "AIF1RX3", NULL, "AIFCLK" },
1350 { "AIF1RX4", NULL, "AIFCLK" },
1351 { "AIF1RX5", NULL, "AIFCLK" },
1353 { "AIF2RX0", NULL, "AIFCLK" },
1354 { "AIF2RX1", NULL, "AIFCLK" },
1356 { "AIF1TX0", NULL, "AIFCLK" },
1357 { "AIF1TX1", NULL, "AIFCLK" },
1358 { "AIF1TX2", NULL, "AIFCLK" },
1359 { "AIF1TX3", NULL, "AIFCLK" },
1360 { "AIF1TX4", NULL, "AIFCLK" },
1361 { "AIF1TX5", NULL, "AIFCLK" },
1363 { "AIF2TX0", NULL, "AIFCLK" },
1364 { "AIF2TX1", NULL, "AIFCLK" },
1366 { "DSP1RXL", NULL, "SYSDSPCLK" },
1367 { "DSP1RXR", NULL, "SYSDSPCLK" },
1368 { "DSP2RXL", NULL, "SYSDSPCLK" },
1369 { "DSP2RXR", NULL, "SYSDSPCLK" },
1370 { "DSP1TXL", NULL, "SYSDSPCLK" },
1371 { "DSP1TXR", NULL, "SYSDSPCLK" },
1372 { "DSP2TXL", NULL, "SYSDSPCLK" },
1373 { "DSP2TXR", NULL, "SYSDSPCLK" },
1375 { "AIF1RXA", NULL, "AIF1RX0" },
1376 { "AIF1RXA", NULL, "AIF1RX1" },
1377 { "AIF1RXB", NULL, "AIF1RX2" },
1378 { "AIF1RXB", NULL, "AIF1RX3" },
1379 { "AIF1RXC", NULL, "AIF1RX4" },
1380 { "AIF1RXC", NULL, "AIF1RX5" },
1382 { "AIF2RX", NULL, "AIF2RX0" },
1383 { "AIF2RX", NULL, "AIF2RX1" },
1385 { "AIF2TX", "DSP2", "DSP2TX" },
1386 { "AIF2TX", "DSP1", "DSP1RX" },
1387 { "AIF2TX", "AIF1", "AIF1RXC" },
1389 { "DSP1RXL", NULL, "DSP1RX" },
1390 { "DSP1RXR", NULL, "DSP1RX" },
1391 { "DSP2RXL", NULL, "DSP2RX" },
1392 { "DSP2RXR", NULL, "DSP2RX" },
1394 { "DSP2TX", NULL, "DSP2TXL" },
1395 { "DSP2TX", NULL, "DSP2TXR" },
1397 { "DSP1RX", "AIF1", "AIF1RXA" },
1398 { "DSP1RX", "AIF2", "AIF2RX" },
1400 { "DSP2RX", "AIF1", "AIF1RXB" },
1401 { "DSP2RX", "AIF2", "AIF2RX" },
1403 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1404 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1405 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1406 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1408 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1409 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1410 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1411 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1413 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1414 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1415 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1416 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1418 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1419 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1420 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1421 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1423 { "DAC1L", NULL, "DAC1L Mixer" },
1424 { "DAC1R", NULL, "DAC1R Mixer" },
1425 { "DAC2L", NULL, "DAC2L Mixer" },
1426 { "DAC2R", NULL, "DAC2R Mixer" },
1428 { "HPOUT2L PGA", NULL, "Charge Pump" },
1429 { "HPOUT2L PGA", NULL, "Bandgap" },
1430 { "HPOUT2L PGA", NULL, "DAC2L" },
1431 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1432 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1433 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1435 { "HPOUT2R PGA", NULL, "Charge Pump" },
1436 { "HPOUT2R PGA", NULL, "Bandgap" },
1437 { "HPOUT2R PGA", NULL, "DAC2R" },
1438 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1439 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1440 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1442 { "HPOUT1L PGA", NULL, "Charge Pump" },
1443 { "HPOUT1L PGA", NULL, "Bandgap" },
1444 { "HPOUT1L PGA", NULL, "DAC1L" },
1445 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1446 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1447 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1449 { "HPOUT1R PGA", NULL, "Charge Pump" },
1450 { "HPOUT1R PGA", NULL, "Bandgap" },
1451 { "HPOUT1R PGA", NULL, "DAC1R" },
1452 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1453 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1454 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1456 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1457 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1458 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1459 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1461 { "SPKL", "DAC1L", "DAC1L" },
1462 { "SPKL", "DAC1R", "DAC1R" },
1463 { "SPKL", "DAC2L", "DAC2L" },
1464 { "SPKL", "DAC2R", "DAC2R" },
1466 { "SPKR", "DAC1L", "DAC1L" },
1467 { "SPKR", "DAC1R", "DAC1R" },
1468 { "SPKR", "DAC2L", "DAC2L" },
1469 { "SPKR", "DAC2R", "DAC2R" },
1471 { "SPKL PGA", NULL, "SPKL" },
1472 { "SPKR PGA", NULL, "SPKR" },
1474 { "SPKDAT", NULL, "SPKL PGA" },
1475 { "SPKDAT", NULL, "SPKR PGA" },
1478 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1480 /* Due to the sparseness of the register map the compiler
1481 * output from an explicit switch statement ends up being much
1482 * more efficient than a table.
1485 case WM8996_SOFTWARE_RESET:
1486 case WM8996_POWER_MANAGEMENT_1:
1487 case WM8996_POWER_MANAGEMENT_2:
1488 case WM8996_POWER_MANAGEMENT_3:
1489 case WM8996_POWER_MANAGEMENT_4:
1490 case WM8996_POWER_MANAGEMENT_5:
1491 case WM8996_POWER_MANAGEMENT_6:
1492 case WM8996_POWER_MANAGEMENT_7:
1493 case WM8996_POWER_MANAGEMENT_8:
1494 case WM8996_LEFT_LINE_INPUT_VOLUME:
1495 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1496 case WM8996_LINE_INPUT_CONTROL:
1497 case WM8996_DAC1_HPOUT1_VOLUME:
1498 case WM8996_DAC2_HPOUT2_VOLUME:
1499 case WM8996_DAC1_LEFT_VOLUME:
1500 case WM8996_DAC1_RIGHT_VOLUME:
1501 case WM8996_DAC2_LEFT_VOLUME:
1502 case WM8996_DAC2_RIGHT_VOLUME:
1503 case WM8996_OUTPUT1_LEFT_VOLUME:
1504 case WM8996_OUTPUT1_RIGHT_VOLUME:
1505 case WM8996_OUTPUT2_LEFT_VOLUME:
1506 case WM8996_OUTPUT2_RIGHT_VOLUME:
1507 case WM8996_MICBIAS_1:
1508 case WM8996_MICBIAS_2:
1511 case WM8996_ACCESSORY_DETECT_MODE_1:
1512 case WM8996_ACCESSORY_DETECT_MODE_2:
1513 case WM8996_HEADPHONE_DETECT_1:
1514 case WM8996_HEADPHONE_DETECT_2:
1515 case WM8996_MIC_DETECT_1:
1516 case WM8996_MIC_DETECT_2:
1517 case WM8996_MIC_DETECT_3:
1518 case WM8996_CHARGE_PUMP_1:
1519 case WM8996_CHARGE_PUMP_2:
1520 case WM8996_DC_SERVO_1:
1521 case WM8996_DC_SERVO_2:
1522 case WM8996_DC_SERVO_3:
1523 case WM8996_DC_SERVO_5:
1524 case WM8996_DC_SERVO_6:
1525 case WM8996_DC_SERVO_7:
1526 case WM8996_DC_SERVO_READBACK_0:
1527 case WM8996_ANALOGUE_HP_1:
1528 case WM8996_ANALOGUE_HP_2:
1529 case WM8996_CHIP_REVISION:
1530 case WM8996_CONTROL_INTERFACE_1:
1531 case WM8996_WRITE_SEQUENCER_CTRL_1:
1532 case WM8996_WRITE_SEQUENCER_CTRL_2:
1533 case WM8996_AIF_CLOCKING_1:
1534 case WM8996_AIF_CLOCKING_2:
1535 case WM8996_CLOCKING_1:
1536 case WM8996_CLOCKING_2:
1537 case WM8996_AIF_RATE:
1538 case WM8996_FLL_CONTROL_1:
1539 case WM8996_FLL_CONTROL_2:
1540 case WM8996_FLL_CONTROL_3:
1541 case WM8996_FLL_CONTROL_4:
1542 case WM8996_FLL_CONTROL_5:
1543 case WM8996_FLL_CONTROL_6:
1544 case WM8996_FLL_EFS_1:
1545 case WM8996_FLL_EFS_2:
1546 case WM8996_AIF1_CONTROL:
1547 case WM8996_AIF1_BCLK:
1548 case WM8996_AIF1_TX_LRCLK_1:
1549 case WM8996_AIF1_TX_LRCLK_2:
1550 case WM8996_AIF1_RX_LRCLK_1:
1551 case WM8996_AIF1_RX_LRCLK_2:
1552 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1553 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1554 case WM8996_AIF1RX_DATA_CONFIGURATION:
1555 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1556 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1557 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1558 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1559 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1560 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1561 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1562 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1563 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1564 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1565 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1566 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1567 case WM8996_AIF1RX_MONO_CONFIGURATION:
1568 case WM8996_AIF1TX_TEST:
1569 case WM8996_AIF2_CONTROL:
1570 case WM8996_AIF2_BCLK:
1571 case WM8996_AIF2_TX_LRCLK_1:
1572 case WM8996_AIF2_TX_LRCLK_2:
1573 case WM8996_AIF2_RX_LRCLK_1:
1574 case WM8996_AIF2_RX_LRCLK_2:
1575 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1576 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1577 case WM8996_AIF2RX_DATA_CONFIGURATION:
1578 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1579 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1580 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1581 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1582 case WM8996_AIF2RX_MONO_CONFIGURATION:
1583 case WM8996_AIF2TX_TEST:
1584 case WM8996_DSP1_TX_LEFT_VOLUME:
1585 case WM8996_DSP1_TX_RIGHT_VOLUME:
1586 case WM8996_DSP1_RX_LEFT_VOLUME:
1587 case WM8996_DSP1_RX_RIGHT_VOLUME:
1588 case WM8996_DSP1_TX_FILTERS:
1589 case WM8996_DSP1_RX_FILTERS_1:
1590 case WM8996_DSP1_RX_FILTERS_2:
1591 case WM8996_DSP1_DRC_1:
1592 case WM8996_DSP1_DRC_2:
1593 case WM8996_DSP1_DRC_3:
1594 case WM8996_DSP1_DRC_4:
1595 case WM8996_DSP1_DRC_5:
1596 case WM8996_DSP1_RX_EQ_GAINS_1:
1597 case WM8996_DSP1_RX_EQ_GAINS_2:
1598 case WM8996_DSP1_RX_EQ_BAND_1_A:
1599 case WM8996_DSP1_RX_EQ_BAND_1_B:
1600 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1601 case WM8996_DSP1_RX_EQ_BAND_2_A:
1602 case WM8996_DSP1_RX_EQ_BAND_2_B:
1603 case WM8996_DSP1_RX_EQ_BAND_2_C:
1604 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1605 case WM8996_DSP1_RX_EQ_BAND_3_A:
1606 case WM8996_DSP1_RX_EQ_BAND_3_B:
1607 case WM8996_DSP1_RX_EQ_BAND_3_C:
1608 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1609 case WM8996_DSP1_RX_EQ_BAND_4_A:
1610 case WM8996_DSP1_RX_EQ_BAND_4_B:
1611 case WM8996_DSP1_RX_EQ_BAND_4_C:
1612 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1613 case WM8996_DSP1_RX_EQ_BAND_5_A:
1614 case WM8996_DSP1_RX_EQ_BAND_5_B:
1615 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1616 case WM8996_DSP2_TX_LEFT_VOLUME:
1617 case WM8996_DSP2_TX_RIGHT_VOLUME:
1618 case WM8996_DSP2_RX_LEFT_VOLUME:
1619 case WM8996_DSP2_RX_RIGHT_VOLUME:
1620 case WM8996_DSP2_TX_FILTERS:
1621 case WM8996_DSP2_RX_FILTERS_1:
1622 case WM8996_DSP2_RX_FILTERS_2:
1623 case WM8996_DSP2_DRC_1:
1624 case WM8996_DSP2_DRC_2:
1625 case WM8996_DSP2_DRC_3:
1626 case WM8996_DSP2_DRC_4:
1627 case WM8996_DSP2_DRC_5:
1628 case WM8996_DSP2_RX_EQ_GAINS_1:
1629 case WM8996_DSP2_RX_EQ_GAINS_2:
1630 case WM8996_DSP2_RX_EQ_BAND_1_A:
1631 case WM8996_DSP2_RX_EQ_BAND_1_B:
1632 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1633 case WM8996_DSP2_RX_EQ_BAND_2_A:
1634 case WM8996_DSP2_RX_EQ_BAND_2_B:
1635 case WM8996_DSP2_RX_EQ_BAND_2_C:
1636 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1637 case WM8996_DSP2_RX_EQ_BAND_3_A:
1638 case WM8996_DSP2_RX_EQ_BAND_3_B:
1639 case WM8996_DSP2_RX_EQ_BAND_3_C:
1640 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1641 case WM8996_DSP2_RX_EQ_BAND_4_A:
1642 case WM8996_DSP2_RX_EQ_BAND_4_B:
1643 case WM8996_DSP2_RX_EQ_BAND_4_C:
1644 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1645 case WM8996_DSP2_RX_EQ_BAND_5_A:
1646 case WM8996_DSP2_RX_EQ_BAND_5_B:
1647 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1648 case WM8996_DAC1_MIXER_VOLUMES:
1649 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1650 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1651 case WM8996_DAC2_MIXER_VOLUMES:
1652 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1653 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1654 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1655 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1656 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1657 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1658 case WM8996_DSP_TX_MIXER_SELECT:
1659 case WM8996_DAC_SOFTMUTE:
1660 case WM8996_OVERSAMPLING:
1661 case WM8996_SIDETONE:
1667 case WM8996_PULL_CONTROL_1:
1668 case WM8996_PULL_CONTROL_2:
1669 case WM8996_INTERRUPT_STATUS_1:
1670 case WM8996_INTERRUPT_STATUS_2:
1671 case WM8996_INTERRUPT_RAW_STATUS_2:
1672 case WM8996_INTERRUPT_STATUS_1_MASK:
1673 case WM8996_INTERRUPT_STATUS_2_MASK:
1674 case WM8996_INTERRUPT_CONTROL:
1675 case WM8996_LEFT_PDM_SPEAKER:
1676 case WM8996_RIGHT_PDM_SPEAKER:
1677 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1678 case WM8996_PDM_SPEAKER_VOLUME:
1685 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1688 case WM8996_SOFTWARE_RESET:
1689 case WM8996_CHIP_REVISION:
1692 case WM8996_INTERRUPT_STATUS_1:
1693 case WM8996_INTERRUPT_STATUS_2:
1694 case WM8996_INTERRUPT_RAW_STATUS_2:
1695 case WM8996_DC_SERVO_READBACK_0:
1696 case WM8996_DC_SERVO_2:
1697 case WM8996_DC_SERVO_6:
1698 case WM8996_DC_SERVO_7:
1699 case WM8996_FLL_CONTROL_6:
1700 case WM8996_MIC_DETECT_3:
1701 case WM8996_HEADPHONE_DETECT_1:
1702 case WM8996_HEADPHONE_DETECT_2:
1709 static int wm8996_reset(struct wm8996_priv *wm8996)
1711 if (wm8996->pdata.ldo_ena > 0) {
1712 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1713 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
1716 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
1721 static const int bclk_divs[] = {
1722 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1725 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1727 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1728 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1730 /* Don't bother if we're in a low frequency idle mode that
1731 * can't support audio.
1733 if (wm8996->sysclk < 64000)
1736 for (aif = 0; aif < WM8996_AIFS; aif++) {
1739 bclk_reg = WM8996_AIF1_BCLK;
1742 bclk_reg = WM8996_AIF2_BCLK;
1746 bclk_rate = wm8996->bclk_rate[aif];
1748 /* Pick a divisor for BCLK as close as we can get to ideal */
1750 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1751 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1752 if (cur_val < 0) /* BCLK table is sorted */
1756 bclk_rate = wm8996->sysclk / bclk_divs[best];
1757 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1758 bclk_divs[best], bclk_rate);
1760 snd_soc_update_bits(codec, bclk_reg,
1761 WM8996_AIF1_BCLK_DIV_MASK, best);
1765 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1766 enum snd_soc_bias_level level)
1768 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1772 case SND_SOC_BIAS_ON:
1773 case SND_SOC_BIAS_PREPARE:
1776 case SND_SOC_BIAS_STANDBY:
1777 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1778 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1782 "Failed to enable supplies: %d\n",
1787 if (wm8996->pdata.ldo_ena >= 0) {
1788 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1793 regcache_cache_only(codec->control_data, false);
1794 regcache_sync(codec->control_data);
1798 case SND_SOC_BIAS_OFF:
1799 regcache_cache_only(codec->control_data, true);
1800 if (wm8996->pdata.ldo_ena >= 0)
1801 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1802 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1807 codec->dapm.bias_level = level;
1812 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1814 struct snd_soc_codec *codec = dai->codec;
1819 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1823 aifctrl_reg = WM8996_AIF1_CONTROL;
1824 bclk_reg = WM8996_AIF1_BCLK;
1825 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1826 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1829 aifctrl_reg = WM8996_AIF2_CONTROL;
1830 bclk_reg = WM8996_AIF2_BCLK;
1831 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1832 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1839 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1840 case SND_SOC_DAIFMT_NB_NF:
1842 case SND_SOC_DAIFMT_IB_NF:
1843 bclk |= WM8996_AIF1_BCLK_INV;
1845 case SND_SOC_DAIFMT_NB_IF:
1846 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1847 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1849 case SND_SOC_DAIFMT_IB_IF:
1850 bclk |= WM8996_AIF1_BCLK_INV;
1851 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1852 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1856 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1857 case SND_SOC_DAIFMT_CBS_CFS:
1859 case SND_SOC_DAIFMT_CBS_CFM:
1860 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1861 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1863 case SND_SOC_DAIFMT_CBM_CFS:
1864 bclk |= WM8996_AIF1_BCLK_MSTR;
1866 case SND_SOC_DAIFMT_CBM_CFM:
1867 bclk |= WM8996_AIF1_BCLK_MSTR;
1868 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1869 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1875 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1876 case SND_SOC_DAIFMT_DSP_A:
1878 case SND_SOC_DAIFMT_DSP_B:
1881 case SND_SOC_DAIFMT_I2S:
1884 case SND_SOC_DAIFMT_LEFT_J:
1891 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1892 snd_soc_update_bits(codec, bclk_reg,
1893 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1895 snd_soc_update_bits(codec, lrclk_tx_reg,
1896 WM8996_AIF1TX_LRCLK_INV |
1897 WM8996_AIF1TX_LRCLK_MSTR,
1899 snd_soc_update_bits(codec, lrclk_rx_reg,
1900 WM8996_AIF1RX_LRCLK_INV |
1901 WM8996_AIF1RX_LRCLK_MSTR,
1907 static const int dsp_divs[] = {
1908 48000, 32000, 16000, 8000
1911 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1912 struct snd_pcm_hw_params *params,
1913 struct snd_soc_dai *dai)
1915 struct snd_soc_codec *codec = dai->codec;
1916 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1917 int bits, i, bclk_rate, best;
1921 int aifdata_reg, lrclk_reg, dsp_shift;
1925 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1926 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1927 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1928 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1930 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1931 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1936 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1937 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1938 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1939 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1941 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1942 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1944 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1951 bclk_rate = snd_soc_params_to_bclk(params);
1952 if (bclk_rate < 0) {
1953 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1957 wm8996->bclk_rate[dai->id] = bclk_rate;
1958 wm8996->rx_rate[dai->id] = params_rate(params);
1960 /* Needs looking at for TDM */
1961 bits = snd_pcm_format_width(params_format(params));
1964 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1967 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1968 if (abs(dsp_divs[i] - params_rate(params)) <
1969 abs(dsp_divs[best] - params_rate(params)))
1972 dsp |= i << dsp_shift;
1974 wm8996_update_bclk(codec);
1976 lrclk = bclk_rate / params_rate(params);
1977 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1978 lrclk, bclk_rate / lrclk);
1980 snd_soc_update_bits(codec, aifdata_reg,
1981 WM8996_AIF1TX_WL_MASK |
1982 WM8996_AIF1TX_SLOT_LEN_MASK,
1984 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1986 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1987 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1992 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1993 int clk_id, unsigned int freq, int dir)
1995 struct snd_soc_codec *codec = dai->codec;
1996 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1999 int sync = WM8996_REG_SYNC;
2003 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2006 /* Disable SYSCLK while we reconfigure */
2007 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2008 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2009 WM8996_SYSCLK_ENA, 0);
2012 case WM8996_SYSCLK_MCLK1:
2013 wm8996->sysclk = freq;
2016 case WM8996_SYSCLK_MCLK2:
2017 wm8996->sysclk = freq;
2020 case WM8996_SYSCLK_FLL:
2021 wm8996->sysclk = freq;
2025 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2029 switch (wm8996->sysclk) {
2032 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2033 WM8996_SYSCLK_RATE, 0);
2037 ratediv = WM8996_SYSCLK_DIV;
2038 wm8996->sysclk /= 2;
2041 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2042 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2046 lfclk = WM8996_LFCLK_ENA;
2050 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2055 wm8996_update_bclk(codec);
2057 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2058 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2059 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2060 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
2061 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
2062 WM8996_REG_SYNC, sync);
2063 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2064 WM8996_SYSCLK_ENA, old);
2066 wm8996->sysclk_src = clk_id;
2088 { 0, 64000, 4, 16 },
2089 { 64000, 128000, 3, 8 },
2090 { 128000, 256000, 2, 4 },
2091 { 256000, 1000000, 1, 2 },
2092 { 1000000, 13500000, 0, 1 },
2095 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2098 unsigned int target;
2100 unsigned int fratio, gcd_fll;
2103 /* Fref must be <=13.5MHz */
2105 fll_div->fll_refclk_div = 0;
2106 while ((Fref / div) > 13500000) {
2108 fll_div->fll_refclk_div++;
2111 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2117 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2119 /* Apply the division for our remaining calculations */
2122 if (Fref >= 3000000)
2123 fll_div->fll_loop_gain = 5;
2125 fll_div->fll_loop_gain = 0;
2128 fll_div->fll_ref_freq = 0;
2130 fll_div->fll_ref_freq = 1;
2132 /* Fvco should be 90-100MHz; don't check the upper bound */
2134 while (Fout * div < 90000000) {
2137 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2142 target = Fout * div;
2143 fll_div->fll_outdiv = div - 1;
2145 pr_debug("FLL Fvco=%dHz\n", target);
2147 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2148 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2149 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2150 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2151 fratio = fll_fratios[i].ratio;
2155 if (i == ARRAY_SIZE(fll_fratios)) {
2156 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2160 fll_div->n = target / (fratio * Fref);
2162 if (target % Fref == 0) {
2164 fll_div->lambda = 0;
2166 gcd_fll = gcd(target, fratio * Fref);
2168 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2170 fll_div->lambda = (fratio * Fref) / gcd_fll;
2173 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2174 fll_div->n, fll_div->theta, fll_div->lambda);
2175 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2176 fll_div->fll_fratio, fll_div->fll_outdiv,
2177 fll_div->fll_refclk_div);
2182 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2183 unsigned int Fref, unsigned int Fout)
2185 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2186 struct i2c_client *i2c = to_i2c_client(codec->dev);
2187 struct _fll_div fll_div;
2188 unsigned long timeout;
2189 int ret, reg, retry;
2192 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2193 Fout == wm8996->fll_fout)
2197 dev_dbg(codec->dev, "FLL disabled\n");
2199 wm8996->fll_fref = 0;
2200 wm8996->fll_fout = 0;
2202 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2205 wm8996_bg_disable(codec);
2210 ret = fll_factors(&fll_div, Fref, Fout);
2215 case WM8996_FLL_MCLK1:
2218 case WM8996_FLL_MCLK2:
2221 case WM8996_FLL_DACLRCLK1:
2224 case WM8996_FLL_BCLK1:
2228 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2232 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2233 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2235 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2236 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2237 WM8996_FLL_REFCLK_SRC_MASK, reg);
2240 if (fll_div.theta || fll_div.lambda)
2241 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2243 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2244 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2246 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2247 WM8996_FLL_OUTDIV_MASK |
2248 WM8996_FLL_FRATIO_MASK,
2249 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2250 (fll_div.fll_fratio));
2252 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2254 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2255 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2256 (fll_div.n << WM8996_FLL_N_SHIFT) |
2257 fll_div.fll_loop_gain);
2259 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2261 /* Enable the bandgap if it's not already enabled */
2262 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2263 if (!(ret & WM8996_FLL_ENA))
2264 wm8996_bg_enable(codec);
2266 /* Clear any pending completions (eg, from failed startups) */
2267 try_wait_for_completion(&wm8996->fll_lock);
2269 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2270 WM8996_FLL_ENA, WM8996_FLL_ENA);
2272 /* The FLL supports live reconfiguration - kick that in case we were
2275 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2277 /* Wait for the FLL to lock, using the interrupt if possible */
2279 timeout = usecs_to_jiffies(300);
2281 timeout = msecs_to_jiffies(2);
2283 /* Allow substantially longer if we've actually got the IRQ, poll
2284 * at a slightly higher rate if we don't.
2291 for (retry = 0; retry < 10; retry++) {
2292 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2299 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2300 if (ret & WM8996_FLL_LOCK_STS)
2304 dev_err(codec->dev, "Timed out waiting for FLL\n");
2308 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2310 wm8996->fll_fref = Fref;
2311 wm8996->fll_fout = Fout;
2312 wm8996->fll_src = source;
2317 #ifdef CONFIG_GPIOLIB
2318 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2320 return container_of(chip, struct wm8996_priv, gpio_chip);
2323 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2325 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2327 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2328 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2331 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2332 unsigned offset, int value)
2334 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2337 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2339 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2340 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2341 WM8996_GP1_LVL, val);
2344 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2346 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2350 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®);
2354 return (reg & WM8996_GP1_LVL) != 0;
2357 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2359 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2361 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2362 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2363 (1 << WM8996_GP1_FN_SHIFT) |
2364 (1 << WM8996_GP1_DIR_SHIFT));
2367 static struct gpio_chip wm8996_template_chip = {
2369 .owner = THIS_MODULE,
2370 .direction_output = wm8996_gpio_direction_out,
2371 .set = wm8996_gpio_set,
2372 .direction_input = wm8996_gpio_direction_in,
2373 .get = wm8996_gpio_get,
2377 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2381 wm8996->gpio_chip = wm8996_template_chip;
2382 wm8996->gpio_chip.ngpio = 5;
2383 wm8996->gpio_chip.dev = wm8996->dev;
2385 if (wm8996->pdata.gpio_base)
2386 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2388 wm8996->gpio_chip.base = -1;
2390 ret = gpiochip_add(&wm8996->gpio_chip);
2392 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2395 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2399 ret = gpiochip_remove(&wm8996->gpio_chip);
2401 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
2404 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2408 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2414 * wm8996_detect - Enable default WM8996 jack detection
2416 * The WM8996 has advanced accessory detection support for headsets.
2417 * This function provides a default implementation which integrates
2418 * the majority of this functionality with minimal user configuration.
2420 * This will detect headset, headphone and short circuit button and
2421 * will also detect inverted microphone ground connections and update
2422 * the polarity of the connections.
2424 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2425 wm8996_polarity_fn polarity_cb)
2427 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2429 wm8996->jack = jack;
2430 wm8996->detecting = true;
2431 wm8996->polarity_cb = polarity_cb;
2432 wm8996->jack_flips = 0;
2434 if (wm8996->polarity_cb)
2435 wm8996->polarity_cb(codec, 0);
2437 /* Clear discarge to avoid noise during detection */
2438 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2439 WM8996_MICB1_DISCH, 0);
2440 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2441 WM8996_MICB2_DISCH, 0);
2443 /* LDO2 powers the microphones, SYSCLK clocks detection */
2444 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2445 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2447 /* We start off just enabling microphone detection - even a
2448 * plain headphone will trigger detection.
2450 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2451 WM8996_MICD_ENA, WM8996_MICD_ENA);
2453 /* Slowest detection rate, gives debounce for initial detection */
2454 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2455 WM8996_MICD_RATE_MASK,
2456 WM8996_MICD_RATE_MASK);
2458 /* Enable interrupts and we're off */
2459 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2460 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2464 EXPORT_SYMBOL_GPL(wm8996_detect);
2466 static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2468 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2469 int val, reg, report;
2471 /* Assume headphone in error conditions; we need to report
2472 * something or we stall our state machine.
2474 report = SND_JACK_HEADPHONE;
2476 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2478 dev_err(codec->dev, "Failed to read HPDET status\n");
2482 if (!(reg & WM8996_HP_DONE)) {
2483 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2487 val = reg & WM8996_HP_LVL_MASK;
2489 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2491 /* If we've got high enough impedence then report as line,
2492 * otherwise assume headphone.
2495 report = SND_JACK_LINEOUT;
2497 report = SND_JACK_HEADPHONE;
2500 if (wm8996->jack_mic)
2501 report |= SND_JACK_MICROPHONE;
2503 snd_soc_jack_report(wm8996->jack, report,
2504 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2506 wm8996->detecting = false;
2508 /* If the output isn't running re-clamp it */
2509 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2510 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2511 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2512 WM8996_HPOUT1L_RMV_SHORT |
2513 WM8996_HPOUT1R_RMV_SHORT, 0);
2515 /* Go back to looking at the microphone */
2516 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2517 WM8996_JD_MODE_MASK, 0);
2518 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2521 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2522 snd_soc_dapm_sync(&codec->dapm);
2525 static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2527 /* Unclamp the output, we can't measure while we're shorting it */
2528 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2529 WM8996_HPOUT1L_RMV_SHORT |
2530 WM8996_HPOUT1R_RMV_SHORT,
2531 WM8996_HPOUT1L_RMV_SHORT |
2532 WM8996_HPOUT1R_RMV_SHORT);
2534 /* We need bandgap for HPDET */
2535 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2536 snd_soc_dapm_sync(&codec->dapm);
2538 /* Go into headphone detect left mode */
2539 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2540 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2541 WM8996_JD_MODE_MASK, 1);
2543 /* Trigger a measurement */
2544 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2545 WM8996_HP_POLL, WM8996_HP_POLL);
2548 static void wm8996_report_headphone(struct snd_soc_codec *codec)
2550 dev_dbg(codec->dev, "Headphone detected\n");
2551 wm8996_hpdet_start(codec);
2553 /* Increase the detection rate a bit for responsiveness. */
2554 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2555 WM8996_MICD_RATE_MASK |
2556 WM8996_MICD_BIAS_STARTTIME_MASK,
2557 7 << WM8996_MICD_RATE_SHIFT |
2558 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2561 static void wm8996_micd(struct snd_soc_codec *codec)
2563 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2566 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2568 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2570 if (!(val & WM8996_MICD_VALID)) {
2571 dev_warn(codec->dev, "Microphone detection state invalid\n");
2575 /* No accessory, reset everything and report removal */
2576 if (!(val & WM8996_MICD_STS)) {
2577 dev_dbg(codec->dev, "Jack removal detected\n");
2578 wm8996->jack_mic = false;
2579 wm8996->detecting = true;
2580 wm8996->jack_flips = 0;
2581 snd_soc_jack_report(wm8996->jack, 0,
2582 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2585 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2586 WM8996_MICD_RATE_MASK |
2587 WM8996_MICD_BIAS_STARTTIME_MASK,
2588 WM8996_MICD_RATE_MASK |
2589 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2593 /* If the measurement is very high we've got a microphone,
2594 * either we just detected one or if we already reported then
2595 * we've got a button release event.
2598 if (wm8996->detecting) {
2599 dev_dbg(codec->dev, "Microphone detected\n");
2600 wm8996->jack_mic = true;
2601 wm8996_hpdet_start(codec);
2603 /* Increase poll rate to give better responsiveness
2605 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2606 WM8996_MICD_RATE_MASK |
2607 WM8996_MICD_BIAS_STARTTIME_MASK,
2608 5 << WM8996_MICD_RATE_SHIFT |
2609 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2611 dev_dbg(codec->dev, "Mic button up\n");
2612 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2618 /* If we detected a lower impedence during initial startup
2619 * then we probably have the wrong polarity, flip it. Don't
2620 * do this for the lowest impedences to speed up detection of
2621 * plain headphones. If both polarities report a low
2622 * impedence then give up and report headphones.
2624 if (wm8996->detecting && (val & 0x3f0)) {
2625 wm8996->jack_flips++;
2627 if (wm8996->jack_flips > 1) {
2628 wm8996_report_headphone(codec);
2632 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2633 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2634 WM8996_MICD_BIAS_SRC;
2635 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2636 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2637 WM8996_MICD_BIAS_SRC, reg);
2639 if (wm8996->polarity_cb)
2640 wm8996->polarity_cb(codec,
2641 (reg & WM8996_MICD_SRC) != 0);
2643 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2644 (reg & WM8996_MICD_SRC) != 0);
2649 /* Don't distinguish between buttons, just report any low
2650 * impedence as BTN_0.
2653 if (wm8996->jack_mic) {
2654 dev_dbg(codec->dev, "Mic button detected\n");
2655 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2657 } else if (wm8996->detecting) {
2658 wm8996_report_headphone(codec);
2663 static irqreturn_t wm8996_irq(int irq, void *data)
2665 struct snd_soc_codec *codec = data;
2666 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2669 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2671 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2675 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2680 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2682 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2683 dev_dbg(codec->dev, "DC servo IRQ\n");
2684 complete(&wm8996->dcs_done);
2687 if (irq_val & WM8996_FIFOS_ERR_EINT)
2688 dev_err(codec->dev, "Digital core FIFO error\n");
2690 if (irq_val & WM8996_FLL_LOCK_EINT) {
2691 dev_dbg(codec->dev, "FLL locked\n");
2692 complete(&wm8996->fll_lock);
2695 if (irq_val & WM8996_MICD_EINT)
2698 if (irq_val & WM8996_HP_DONE_EINT)
2699 wm8996_hpdet_irq(codec);
2704 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2706 irqreturn_t ret = IRQ_NONE;
2710 val = wm8996_irq(irq, data);
2711 if (val != IRQ_NONE)
2713 } while (val != IRQ_NONE);
2718 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2720 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2721 struct wm8996_pdata *pdata = &wm8996->pdata;
2723 struct snd_kcontrol_new controls[] = {
2724 SOC_ENUM_EXT("DSP1 EQ Mode",
2725 wm8996->retune_mobile_enum,
2726 wm8996_get_retune_mobile_enum,
2727 wm8996_put_retune_mobile_enum),
2728 SOC_ENUM_EXT("DSP2 EQ Mode",
2729 wm8996->retune_mobile_enum,
2730 wm8996_get_retune_mobile_enum,
2731 wm8996_put_retune_mobile_enum),
2736 /* We need an array of texts for the enum API but the number
2737 * of texts is likely to be less than the number of
2738 * configurations due to the sample rate dependency of the
2739 * configurations. */
2740 wm8996->num_retune_mobile_texts = 0;
2741 wm8996->retune_mobile_texts = NULL;
2742 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2743 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2744 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2745 wm8996->retune_mobile_texts[j]) == 0)
2749 if (j != wm8996->num_retune_mobile_texts)
2752 /* Expand the array... */
2753 t = krealloc(wm8996->retune_mobile_texts,
2755 (wm8996->num_retune_mobile_texts + 1),
2760 /* ...store the new entry... */
2761 t[wm8996->num_retune_mobile_texts] =
2762 pdata->retune_mobile_cfgs[i].name;
2764 /* ...and remember the new version. */
2765 wm8996->num_retune_mobile_texts++;
2766 wm8996->retune_mobile_texts = t;
2769 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2770 wm8996->num_retune_mobile_texts);
2772 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2773 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2775 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2778 "Failed to add ReTune Mobile controls: %d\n", ret);
2781 static const struct regmap_config wm8996_regmap = {
2785 .max_register = WM8996_MAX_REGISTER,
2786 .reg_defaults = wm8996_reg,
2787 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2788 .volatile_reg = wm8996_volatile_register,
2789 .readable_reg = wm8996_readable_register,
2790 .cache_type = REGCACHE_RBTREE,
2793 static int wm8996_probe(struct snd_soc_codec *codec)
2796 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2797 struct i2c_client *i2c = to_i2c_client(codec->dev);
2800 wm8996->codec = codec;
2802 init_completion(&wm8996->dcs_done);
2803 init_completion(&wm8996->fll_lock);
2805 codec->control_data = wm8996->regmap;
2807 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2809 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2813 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2814 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2815 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2817 /* This should really be moved into the regulator core */
2818 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2819 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2820 &wm8996->disable_nb[i]);
2823 "Failed to register regulator notifier: %d\n",
2828 regcache_cache_only(codec->control_data, true);
2830 /* Apply platform data settings */
2831 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2832 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2833 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2834 wm8996->pdata.inr_mode);
2836 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2837 if (!wm8996->pdata.gpio_default[i])
2840 snd_soc_write(codec, WM8996_GPIO_1 + i,
2841 wm8996->pdata.gpio_default[i] & 0xffff);
2844 if (wm8996->pdata.spkmute_seq)
2845 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2846 WM8996_SPK_MUTE_ENDIAN |
2847 WM8996_SPK_MUTE_SEQ1_MASK,
2848 wm8996->pdata.spkmute_seq);
2850 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2851 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2852 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2854 /* Latch volume update bits */
2855 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2856 WM8996_IN1_VU, WM8996_IN1_VU);
2857 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2858 WM8996_IN1_VU, WM8996_IN1_VU);
2860 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2861 WM8996_DAC1_VU, WM8996_DAC1_VU);
2862 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2863 WM8996_DAC1_VU, WM8996_DAC1_VU);
2864 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2865 WM8996_DAC2_VU, WM8996_DAC2_VU);
2866 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2867 WM8996_DAC2_VU, WM8996_DAC2_VU);
2869 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2870 WM8996_DAC1_VU, WM8996_DAC1_VU);
2871 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2872 WM8996_DAC1_VU, WM8996_DAC1_VU);
2873 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2874 WM8996_DAC2_VU, WM8996_DAC2_VU);
2875 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2876 WM8996_DAC2_VU, WM8996_DAC2_VU);
2878 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2879 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2880 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2881 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2882 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2883 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2884 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2885 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2887 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2888 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2889 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2890 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2891 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2892 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2893 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2894 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2896 /* No support currently for the underclocked TDM modes and
2897 * pick a default TDM layout with each channel pair working with
2899 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2900 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2901 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2902 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2903 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2904 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2905 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2906 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2907 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2908 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2909 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2910 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2911 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2912 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2913 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2914 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2915 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2916 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2917 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2918 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2919 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2920 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2921 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2922 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2924 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2925 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2926 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2927 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2928 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2929 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2930 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2931 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2933 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2934 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2935 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2936 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2937 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2938 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2939 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2940 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2941 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2942 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2943 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2944 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2945 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2946 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2947 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2948 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2949 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2950 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2951 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2952 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2953 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2954 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2955 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2956 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2958 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2959 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2960 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2961 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2962 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2963 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2964 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2965 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2967 if (wm8996->pdata.num_retune_mobile_cfgs)
2968 wm8996_retune_mobile_pdata(codec);
2970 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2971 ARRAY_SIZE(wm8996_eq_controls));
2973 /* If the TX LRCLK pins are not in LRCLK mode configure the
2974 * AIFs to source their clocks from the RX LRCLKs.
2976 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2977 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2978 WM8996_AIF1TX_LRCLK_MODE,
2979 WM8996_AIF1TX_LRCLK_MODE);
2981 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2982 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2983 WM8996_AIF2TX_LRCLK_MODE,
2984 WM8996_AIF2TX_LRCLK_MODE);
2987 if (wm8996->pdata.irq_flags)
2988 irq_flags = wm8996->pdata.irq_flags;
2990 irq_flags = IRQF_TRIGGER_LOW;
2992 irq_flags |= IRQF_ONESHOT;
2994 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2995 ret = request_threaded_irq(i2c->irq, NULL,
2997 irq_flags, "wm8996", codec);
2999 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
3000 irq_flags, "wm8996", codec);
3003 /* Unmask the interrupt */
3004 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3007 /* Enable error reporting and DC servo status */
3008 snd_soc_update_bits(codec,
3009 WM8996_INTERRUPT_STATUS_2_MASK,
3010 WM8996_IM_DCS_DONE_23_EINT |
3011 WM8996_IM_DCS_DONE_01_EINT |
3012 WM8996_IM_FLL_LOCK_EINT |
3013 WM8996_IM_FIFOS_ERR_EINT,
3016 dev_err(codec->dev, "Failed to request IRQ: %d\n",
3027 static int wm8996_remove(struct snd_soc_codec *codec)
3029 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3030 struct i2c_client *i2c = to_i2c_client(codec->dev);
3033 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3034 WM8996_IM_IRQ, WM8996_IM_IRQ);
3037 free_irq(i2c->irq, codec);
3039 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3040 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3041 &wm8996->disable_nb[i]);
3042 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3047 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3048 .probe = wm8996_probe,
3049 .remove = wm8996_remove,
3050 .set_bias_level = wm8996_set_bias_level,
3051 .idle_bias_off = true,
3052 .seq_notifier = wm8996_seq_notifier,
3053 .controls = wm8996_snd_controls,
3054 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3055 .dapm_widgets = wm8996_dapm_widgets,
3056 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3057 .dapm_routes = wm8996_dapm_routes,
3058 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3059 .set_pll = wm8996_set_fll,
3062 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3063 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
3064 SNDRV_PCM_RATE_48000)
3065 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3066 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3067 SNDRV_PCM_FMTBIT_S32_LE)
3069 static const struct snd_soc_dai_ops wm8996_dai_ops = {
3070 .set_fmt = wm8996_set_fmt,
3071 .hw_params = wm8996_hw_params,
3072 .set_sysclk = wm8996_set_sysclk,
3075 static struct snd_soc_dai_driver wm8996_dai[] = {
3077 .name = "wm8996-aif1",
3079 .stream_name = "AIF1 Playback",
3082 .rates = WM8996_RATES,
3083 .formats = WM8996_FORMATS,
3087 .stream_name = "AIF1 Capture",
3090 .rates = WM8996_RATES,
3091 .formats = WM8996_FORMATS,
3094 .ops = &wm8996_dai_ops,
3097 .name = "wm8996-aif2",
3099 .stream_name = "AIF2 Playback",
3102 .rates = WM8996_RATES,
3103 .formats = WM8996_FORMATS,
3107 .stream_name = "AIF2 Capture",
3110 .rates = WM8996_RATES,
3111 .formats = WM8996_FORMATS,
3114 .ops = &wm8996_dai_ops,
3118 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3119 const struct i2c_device_id *id)
3121 struct wm8996_priv *wm8996;
3125 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
3130 i2c_set_clientdata(i2c, wm8996);
3131 wm8996->dev = &i2c->dev;
3133 if (dev_get_platdata(&i2c->dev))
3134 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3135 sizeof(wm8996->pdata));
3137 if (wm8996->pdata.ldo_ena > 0) {
3138 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3139 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3141 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3142 wm8996->pdata.ldo_ena, ret);
3147 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3148 wm8996->supplies[i].supply = wm8996_supply_names[i];
3150 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
3153 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3157 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
3160 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3164 if (wm8996->pdata.ldo_ena > 0) {
3165 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
3169 wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap);
3170 if (IS_ERR(wm8996->regmap)) {
3171 ret = PTR_ERR(wm8996->regmap);
3172 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3176 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®);
3178 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
3181 if (reg != 0x8915) {
3182 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
3187 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®);
3189 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3194 dev_info(&i2c->dev, "revision %c\n",
3195 (reg & WM8996_CHIP_REV_MASK) + 'A');
3197 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3199 ret = wm8996_reset(wm8996);
3201 dev_err(&i2c->dev, "Failed to issue reset\n");
3205 wm8996_init_gpio(wm8996);
3207 ret = snd_soc_register_codec(&i2c->dev,
3208 &soc_codec_dev_wm8996, wm8996_dai,
3209 ARRAY_SIZE(wm8996_dai));
3216 wm8996_free_gpio(wm8996);
3218 regmap_exit(wm8996->regmap);
3220 if (wm8996->pdata.ldo_ena > 0)
3221 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3222 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3224 if (wm8996->pdata.ldo_ena > 0)
3225 gpio_free(wm8996->pdata.ldo_ena);
3231 static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3233 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3235 snd_soc_unregister_codec(&client->dev);
3236 wm8996_free_gpio(wm8996);
3237 regmap_exit(wm8996->regmap);
3238 if (wm8996->pdata.ldo_ena > 0) {
3239 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3240 gpio_free(wm8996->pdata.ldo_ena);
3245 static const struct i2c_device_id wm8996_i2c_id[] = {
3249 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3251 static struct i2c_driver wm8996_i2c_driver = {
3254 .owner = THIS_MODULE,
3256 .probe = wm8996_i2c_probe,
3257 .remove = __devexit_p(wm8996_i2c_remove),
3258 .id_table = wm8996_i2c_id,
3261 module_i2c_driver(wm8996_i2c_driver);
3263 MODULE_DESCRIPTION("ASoC WM8996 driver");
3264 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3265 MODULE_LICENSE("GPL");