2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
25 #include "davinci-pcm.h"
27 #define DAVINCI_MCBSP_DRR_REG 0x00
28 #define DAVINCI_MCBSP_DXR_REG 0x04
29 #define DAVINCI_MCBSP_SPCR_REG 0x08
30 #define DAVINCI_MCBSP_RCR_REG 0x0c
31 #define DAVINCI_MCBSP_XCR_REG 0x10
32 #define DAVINCI_MCBSP_SRGR_REG 0x14
33 #define DAVINCI_MCBSP_PCR_REG 0x24
35 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
36 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
37 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
38 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
39 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
40 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
41 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
43 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
44 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
45 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
46 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
48 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
49 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
50 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
51 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
52 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
54 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
55 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
56 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
58 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
59 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
60 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
61 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
62 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
63 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
64 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
65 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
66 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
68 #define MOD_REG_BIT(val, mask, set) do { \
77 DAVINCI_MCBSP_WORD_8 = 0,
78 DAVINCI_MCBSP_WORD_12,
79 DAVINCI_MCBSP_WORD_16,
80 DAVINCI_MCBSP_WORD_20,
81 DAVINCI_MCBSP_WORD_24,
82 DAVINCI_MCBSP_WORD_32,
85 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
86 .name = "I2S PCM Stereo out",
89 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
90 .name = "I2S PCM Stereo in",
93 struct davinci_mcbsp_dev {
96 struct davinci_pcm_dma_params *dma_params[2];
99 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
102 __raw_writel(val, dev->base + reg);
105 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
107 return __raw_readl(dev->base + reg);
110 static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
112 struct snd_soc_pcm_runtime *rtd = substream->private_data;
113 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
114 struct snd_soc_device *socdev = rtd->socdev;
115 struct snd_soc_platform *platform = socdev->platform;
119 /* Start the sample generator and enable transmitter/receiver */
120 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
121 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
122 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
124 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
125 /* Stop the DMA to avoid data loss */
126 /* while the transmitter is out of reset to handle XSYNCERR */
127 if (platform->pcm_ops->trigger) {
128 ret = platform->pcm_ops->trigger(substream,
129 SNDRV_PCM_TRIGGER_STOP);
131 printk(KERN_DEBUG "Playback DMA stop failed\n");
134 /* Enable the transmitter */
135 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
136 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
137 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
139 /* wait for any unexpected frame sync error to occur */
142 /* Disable the transmitter to clear any outstanding XSYNCERR */
143 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
144 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
145 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
147 /* Restart the DMA */
148 if (platform->pcm_ops->trigger) {
149 ret = platform->pcm_ops->trigger(substream,
150 SNDRV_PCM_TRIGGER_START);
152 printk(KERN_DEBUG "Playback DMA start failed\n");
154 /* Enable the transmitter */
155 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
156 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
157 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
161 /* Enable the reciever */
162 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
163 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
164 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
168 /* Start frame sync */
169 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
170 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
171 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
174 static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
177 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
180 /* Reset transmitter/receiver and sample rate/frame sync generators */
181 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
182 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
183 DAVINCI_MCBSP_SPCR_FRST, 0);
184 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
185 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
187 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
188 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
191 static int davinci_i2s_startup(struct snd_pcm_substream *substream)
193 struct snd_soc_pcm_runtime *rtd = substream->private_data;
194 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
195 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
197 cpu_dai->dma_data = dev->dma_params[substream->stream];
202 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
205 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
208 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
209 case SND_SOC_DAIFMT_CBS_CFS:
210 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
211 DAVINCI_MCBSP_PCR_FSXM |
212 DAVINCI_MCBSP_PCR_FSRM |
213 DAVINCI_MCBSP_PCR_CLKXM |
214 DAVINCI_MCBSP_PCR_CLKRM);
215 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
216 DAVINCI_MCBSP_SRGR_FSGM);
218 case SND_SOC_DAIFMT_CBM_CFS:
219 /* McBSP CLKR pin is the input for the Sample Rate Generator.
220 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
221 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
222 DAVINCI_MCBSP_PCR_SCLKME |
223 DAVINCI_MCBSP_PCR_FSXM |
224 DAVINCI_MCBSP_PCR_FSRM);
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
226 DAVINCI_MCBSP_SRGR_FSGM);
228 case SND_SOC_DAIFMT_CBM_CFM:
229 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
235 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
236 case SND_SOC_DAIFMT_IB_NF:
237 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
238 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
239 DAVINCI_MCBSP_PCR_CLKRP, 1);
240 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
242 case SND_SOC_DAIFMT_NB_IF:
243 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
244 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
245 DAVINCI_MCBSP_PCR_FSRP, 1);
246 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
248 case SND_SOC_DAIFMT_IB_IF:
249 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
250 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
251 DAVINCI_MCBSP_PCR_CLKRP |
252 DAVINCI_MCBSP_PCR_FSXP |
253 DAVINCI_MCBSP_PCR_FSRP, 1);
254 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
256 case SND_SOC_DAIFMT_NB_NF:
262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
263 case SND_SOC_DAIFMT_RIGHT_J:
264 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
265 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
266 DAVINCI_MCBSP_RCR_RDATDLY(0));
267 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
268 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
269 DAVINCI_MCBSP_XCR_XDATDLY(0) |
270 DAVINCI_MCBSP_XCR_XFIG);
272 case SND_SOC_DAIFMT_I2S:
274 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
275 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
276 DAVINCI_MCBSP_RCR_RDATDLY(1));
277 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
278 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
279 DAVINCI_MCBSP_XCR_XDATDLY(1) |
280 DAVINCI_MCBSP_XCR_XFIG);
287 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
288 struct snd_pcm_hw_params *params)
290 struct snd_soc_pcm_runtime *rtd = substream->private_data;
291 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
292 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
293 struct snd_interval *i = NULL;
294 int mcbsp_word_length;
297 /* general line settings */
298 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
299 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
300 w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
301 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
303 w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
304 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
307 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
308 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
309 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
310 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
312 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
313 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
314 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
315 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
317 /* Determine xfer data type */
318 switch (params_format(params)) {
319 case SNDRV_PCM_FORMAT_S8:
320 dma_params->data_type = 1;
321 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
323 case SNDRV_PCM_FORMAT_S16_LE:
324 dma_params->data_type = 2;
325 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
327 case SNDRV_PCM_FORMAT_S32_LE:
328 dma_params->data_type = 4;
329 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
332 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
336 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
337 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
338 MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
339 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
340 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
343 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
344 MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
345 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
346 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
352 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
357 case SNDRV_PCM_TRIGGER_START:
358 case SNDRV_PCM_TRIGGER_RESUME:
359 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
360 davinci_mcbsp_start(substream);
362 case SNDRV_PCM_TRIGGER_STOP:
363 case SNDRV_PCM_TRIGGER_SUSPEND:
364 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
365 davinci_mcbsp_stop(substream);
374 static int davinci_i2s_probe(struct platform_device *pdev,
375 struct snd_soc_dai *dai)
377 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
378 struct snd_soc_machine *machine = socdev->machine;
379 struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
380 struct davinci_mcbsp_dev *dev;
381 struct resource *mem, *ioarea;
382 struct evm_snd_platform_data *pdata;
385 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
387 dev_err(&pdev->dev, "no mem resource?\n");
391 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
394 dev_err(&pdev->dev, "McBSP region already claimed\n");
398 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
401 goto err_release_region;
404 cpu_dai->private_data = dev;
406 dev->clk = clk_get(&pdev->dev, "McBSPCLK");
407 if (IS_ERR(dev->clk)) {
411 clk_enable(dev->clk);
413 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
414 pdata = pdev->dev.platform_data;
416 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
417 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
418 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
419 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
421 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
422 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
423 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
424 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
431 release_mem_region(mem->start, (mem->end - mem->start) + 1);
436 static void davinci_i2s_remove(struct platform_device *pdev,
437 struct snd_soc_dai *dai)
439 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
440 struct snd_soc_machine *machine = socdev->machine;
441 struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
442 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
443 struct resource *mem;
445 clk_disable(dev->clk);
451 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 release_mem_region(mem->start, (mem->end - mem->start) + 1);
455 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
457 struct snd_soc_dai davinci_i2s_dai = {
458 .name = "davinci-i2s",
460 .type = SND_SOC_DAI_I2S,
461 .probe = davinci_i2s_probe,
462 .remove = davinci_i2s_remove,
466 .rates = DAVINCI_I2S_RATES,
467 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
471 .rates = DAVINCI_I2S_RATES,
472 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
474 .startup = davinci_i2s_startup,
475 .trigger = davinci_i2s_trigger,
476 .hw_params = davinci_i2s_hw_params,},
478 .set_fmt = davinci_i2s_set_dai_fmt,
481 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
483 MODULE_AUTHOR("Vladimir Barinov");
484 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
485 MODULE_LICENSE("GPL");