2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
38 #define DAVINCI_MCASP_NUM_SERIALIZER 16
40 struct davinci_audio_dev {
41 struct davinci_pcm_dma_params dma_params[2];
45 /* McASP specific data */
53 /* McASP FIFO related */
57 #ifdef CONFIG_PM_SLEEP
70 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
72 __raw_writel(__raw_readl(reg) | val, reg);
75 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
77 __raw_writel((__raw_readl(reg) & ~(val)), reg);
80 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
82 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
85 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
87 __raw_writel(val, reg);
90 static inline u32 mcasp_get_reg(void __iomem *reg)
92 return (unsigned int)__raw_readl(reg);
95 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
99 mcasp_set_bits(regs, val);
101 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
102 /* loop count is to avoid the lock-up */
103 for (i = 0; i < 1000; i++) {
104 if ((mcasp_get_reg(regs) & val) == val)
108 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
109 printk(KERN_ERR "GBLCTL write error\n");
112 static void mcasp_start_rx(struct davinci_audio_dev *dev)
114 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
115 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
116 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
117 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
119 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
120 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
121 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
123 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
124 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
127 static void mcasp_start_tx(struct davinci_audio_dev *dev)
132 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
133 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
134 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
135 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
137 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
138 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
139 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
140 for (i = 0; i < dev->num_serializer; i++) {
141 if (dev->serial_dir[i] == TX_MODE) {
147 /* wait for TX ready */
149 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
150 TXSTATE) && (cnt < 100000))
153 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
156 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
158 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
159 if (dev->txnumevt) { /* enable FIFO */
160 switch (dev->version) {
161 case MCASP_VERSION_3:
162 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
164 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
168 mcasp_clr_bits(dev->base +
169 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
170 mcasp_set_bits(dev->base +
171 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
176 if (dev->rxnumevt) { /* enable FIFO */
177 switch (dev->version) {
178 case MCASP_VERSION_3:
179 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
181 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
185 mcasp_clr_bits(dev->base +
186 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
187 mcasp_set_bits(dev->base +
188 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
195 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
197 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
198 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
201 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
203 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
204 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
207 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
209 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
210 if (dev->txnumevt) { /* disable FIFO */
211 switch (dev->version) {
212 case MCASP_VERSION_3:
213 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
217 mcasp_clr_bits(dev->base +
218 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
223 if (dev->rxnumevt) { /* disable FIFO */
224 switch (dev->version) {
225 case MCASP_VERSION_3:
226 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
231 mcasp_clr_bits(dev->base +
232 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
239 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
242 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
243 void __iomem *base = dev->base;
245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
246 case SND_SOC_DAIFMT_DSP_B:
247 case SND_SOC_DAIFMT_AC97:
248 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
249 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
252 /* configure a full-word SYNC pulse (LRCLK) */
253 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
254 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
256 /* make 1st data bit occur one ACLK cycle after the frame sync */
257 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
258 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
262 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
263 case SND_SOC_DAIFMT_CBS_CFS:
264 /* codec is clock and frame slave */
265 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
266 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
268 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
269 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
271 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
273 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
276 case SND_SOC_DAIFMT_CBM_CFS:
277 /* codec is clock master and frame slave */
278 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
279 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
281 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
282 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
284 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
286 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
289 case SND_SOC_DAIFMT_CBM_CFM:
290 /* codec is clock and frame master */
291 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
292 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
294 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
295 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
297 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
298 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
305 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
306 case SND_SOC_DAIFMT_IB_NF:
307 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
308 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
310 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
311 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
314 case SND_SOC_DAIFMT_NB_IF:
315 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
316 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
318 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
319 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
322 case SND_SOC_DAIFMT_IB_IF:
323 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
324 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
326 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
327 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
330 case SND_SOC_DAIFMT_NB_NF:
331 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
332 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
334 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
335 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
345 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
347 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
350 case 0: /* MCLK divider */
351 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
352 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
353 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
354 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
357 case 1: /* BCLK divider */
358 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
359 ACLKXDIV(div - 1), ACLKXDIV_MASK);
360 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
361 ACLKRDIV(div - 1), ACLKRDIV_MASK);
364 case 2: /* BCLK/LRCLK ratio */
365 dev->bclk_lrclk_ratio = div;
375 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
376 unsigned int freq, int dir)
378 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
380 if (dir == SND_SOC_CLOCK_OUT) {
381 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
382 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
383 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
385 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
386 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
387 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
393 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
397 u32 tx_rotate = (word_length / 4) & 0x7;
398 u32 rx_rotate = (32 - word_length) / 4;
399 u32 mask = (1ULL << word_length) - 1;
402 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
403 * callback, take it into account here. That allows us to for example
404 * send 32 bits per channel to the codec, while only 16 of them carry
406 * The clock ratio is given for a full period of data (for I2S format
407 * both left and right channels), so it has to be divided by number of
408 * tdm-slots (for I2S - divided by 2).
410 if (dev->bclk_lrclk_ratio)
411 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
413 /* mapping of the XSSZ bit-field as described in the datasheet */
414 fmt = (word_length >> 1) - 1;
416 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
417 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
418 RXSSZ(fmt), RXSSZ(0x0F));
419 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
420 TXSSZ(fmt), TXSSZ(0x0F));
421 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
422 TXROT(tx_rotate), TXROT(7));
423 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
424 RXROT(rx_rotate), RXROT(7));
425 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
429 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
434 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
441 u8 slots = dev->tdm_slots;
442 u8 max_active_serializers = (channels + slots - 1) / slots;
443 /* Default configuration */
444 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
446 /* All PINS as McASP */
447 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
449 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
450 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
451 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
454 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
455 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
459 for (i = 0; i < dev->num_serializer; i++) {
460 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
462 if (dev->serial_dir[i] == TX_MODE &&
463 tx_ser < max_active_serializers) {
464 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
467 } else if (dev->serial_dir[i] == RX_MODE &&
468 rx_ser < max_active_serializers) {
469 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
473 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
474 SRMOD_INACTIVE, SRMOD_MASK);
478 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
483 if (ser < max_active_serializers) {
484 dev_warn(dev->dev, "stream has more channels (%d) than are "
485 "enabled in mcasp (%d)\n", channels, ser * slots);
489 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
490 if (dev->txnumevt * tx_ser > 64)
493 switch (dev->version) {
494 case MCASP_VERSION_3:
495 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
497 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
498 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
501 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
502 tx_ser, NUMDMA_MASK);
503 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
504 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
508 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
509 if (dev->rxnumevt * rx_ser > 64)
511 switch (dev->version) {
512 case MCASP_VERSION_3:
513 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
515 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
516 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
519 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
520 rx_ser, NUMDMA_MASK);
521 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
522 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
529 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
534 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
535 for (i = 0; i < active_slots; i++)
538 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
540 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
541 /* bit stream is MSB first with no delay */
543 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
544 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
546 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
547 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
548 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
550 printk(KERN_ERR "playback tdm slot %d not supported\n",
553 /* bit stream is MSB first with no delay */
555 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
556 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
558 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
559 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
560 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
562 printk(KERN_ERR "capture tdm slot %d not supported\n",
568 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
570 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
572 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
573 TXROT(6) | TXSSZ(15));
575 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
576 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
577 AFSXE | FSXMOD(0x180));
579 /* Set the TX tdm : for all the slots */
580 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
582 /* Set the TX clock controls : div = 1 and internal */
583 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
586 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
588 /* Only 44100 and 48000 are valid, both have the same setting */
589 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
592 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
595 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
596 struct snd_pcm_hw_params *params,
597 struct snd_soc_dai *cpu_dai)
599 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
600 struct davinci_pcm_dma_params *dma_params =
601 &dev->dma_params[substream->stream];
604 u8 slots = dev->tdm_slots;
605 u8 active_serializers;
607 struct snd_interval *pcm_channels = hw_param_interval(params,
608 SNDRV_PCM_HW_PARAM_CHANNELS);
609 channels = pcm_channels->min;
611 active_serializers = (channels + slots - 1) / slots;
613 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
615 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
616 fifo_level = dev->txnumevt * active_serializers;
618 fifo_level = dev->rxnumevt * active_serializers;
620 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
621 davinci_hw_dit_param(dev);
623 davinci_hw_param(dev, substream->stream);
625 switch (params_format(params)) {
626 case SNDRV_PCM_FORMAT_U8:
627 case SNDRV_PCM_FORMAT_S8:
628 dma_params->data_type = 1;
632 case SNDRV_PCM_FORMAT_U16_LE:
633 case SNDRV_PCM_FORMAT_S16_LE:
634 dma_params->data_type = 2;
638 case SNDRV_PCM_FORMAT_U24_3LE:
639 case SNDRV_PCM_FORMAT_S24_3LE:
640 dma_params->data_type = 3;
644 case SNDRV_PCM_FORMAT_U24_LE:
645 case SNDRV_PCM_FORMAT_S24_LE:
646 case SNDRV_PCM_FORMAT_U32_LE:
647 case SNDRV_PCM_FORMAT_S32_LE:
648 dma_params->data_type = 4;
653 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
657 if (dev->version == MCASP_VERSION_2 && !fifo_level)
658 dma_params->acnt = 4;
660 dma_params->acnt = dma_params->data_type;
662 dma_params->fifo_level = fifo_level;
663 davinci_config_channel_size(dev, word_length);
668 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
669 int cmd, struct snd_soc_dai *cpu_dai)
671 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
675 case SNDRV_PCM_TRIGGER_RESUME:
676 case SNDRV_PCM_TRIGGER_START:
677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
678 ret = pm_runtime_get_sync(dev->dev);
679 if (IS_ERR_VALUE(ret))
680 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
681 davinci_mcasp_start(dev, substream->stream);
684 case SNDRV_PCM_TRIGGER_SUSPEND:
685 davinci_mcasp_stop(dev, substream->stream);
686 ret = pm_runtime_put_sync(dev->dev);
687 if (IS_ERR_VALUE(ret))
688 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
691 case SNDRV_PCM_TRIGGER_STOP:
692 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
693 davinci_mcasp_stop(dev, substream->stream);
703 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
704 struct snd_soc_dai *dai)
706 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
708 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
712 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
713 .startup = davinci_mcasp_startup,
714 .trigger = davinci_mcasp_trigger,
715 .hw_params = davinci_mcasp_hw_params,
716 .set_fmt = davinci_mcasp_set_dai_fmt,
717 .set_clkdiv = davinci_mcasp_set_clkdiv,
718 .set_sysclk = davinci_mcasp_set_sysclk,
721 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
723 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
724 SNDRV_PCM_FMTBIT_U8 | \
725 SNDRV_PCM_FMTBIT_S16_LE | \
726 SNDRV_PCM_FMTBIT_U16_LE | \
727 SNDRV_PCM_FMTBIT_S24_LE | \
728 SNDRV_PCM_FMTBIT_U24_LE | \
729 SNDRV_PCM_FMTBIT_S24_3LE | \
730 SNDRV_PCM_FMTBIT_U24_3LE | \
731 SNDRV_PCM_FMTBIT_S32_LE | \
732 SNDRV_PCM_FMTBIT_U32_LE)
734 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
736 .name = "davinci-mcasp.0",
739 .channels_max = 32 * 16,
740 .rates = DAVINCI_MCASP_RATES,
741 .formats = DAVINCI_MCASP_PCM_FMTS,
745 .channels_max = 32 * 16,
746 .rates = DAVINCI_MCASP_RATES,
747 .formats = DAVINCI_MCASP_PCM_FMTS,
749 .ops = &davinci_mcasp_dai_ops,
753 .name = "davinci-mcasp.1",
757 .rates = DAVINCI_MCASP_RATES,
758 .formats = DAVINCI_MCASP_PCM_FMTS,
760 .ops = &davinci_mcasp_dai_ops,
765 static const struct snd_soc_component_driver davinci_mcasp_component = {
766 .name = "davinci-mcasp",
769 /* Some HW specific values and defaults. The rest is filled in from DT. */
770 static struct snd_platform_data dm646x_mcasp_pdata = {
771 .tx_dma_offset = 0x400,
772 .rx_dma_offset = 0x400,
773 .asp_chan_q = EVENTQ_0,
774 .version = MCASP_VERSION_1,
777 static struct snd_platform_data da830_mcasp_pdata = {
778 .tx_dma_offset = 0x2000,
779 .rx_dma_offset = 0x2000,
780 .asp_chan_q = EVENTQ_0,
781 .version = MCASP_VERSION_2,
784 static struct snd_platform_data omap2_mcasp_pdata = {
787 .asp_chan_q = EVENTQ_0,
788 .version = MCASP_VERSION_3,
791 static const struct of_device_id mcasp_dt_ids[] = {
793 .compatible = "ti,dm646x-mcasp-audio",
794 .data = &dm646x_mcasp_pdata,
797 .compatible = "ti,da830-mcasp-audio",
798 .data = &da830_mcasp_pdata,
801 .compatible = "ti,am33xx-mcasp-audio",
802 .data = &omap2_mcasp_pdata,
806 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
808 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
809 struct platform_device *pdev)
811 struct device_node *np = pdev->dev.of_node;
812 struct snd_platform_data *pdata = NULL;
813 const struct of_device_id *match =
814 of_match_device(mcasp_dt_ids, &pdev->dev);
815 struct of_phandle_args dma_spec;
817 const u32 *of_serial_dir32;
821 if (pdev->dev.platform_data) {
822 pdata = pdev->dev.platform_data;
825 pdata = (struct snd_platform_data *) match->data;
827 /* control shouldn't reach here. something is wrong */
832 ret = of_property_read_u32(np, "op-mode", &val);
834 pdata->op_mode = val;
836 ret = of_property_read_u32(np, "tdm-slots", &val);
838 if (val < 2 || val > 32) {
840 "tdm-slots must be in rage [2-32]\n");
845 pdata->tdm_slots = val;
848 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
850 if (of_serial_dir32) {
851 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
852 (sizeof(*of_serial_dir) * val),
854 if (!of_serial_dir) {
859 for (i = 0; i < val; i++)
860 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
862 pdata->num_serializer = val;
863 pdata->serial_dir = of_serial_dir;
866 ret = of_property_match_string(np, "dma-names", "tx");
870 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
875 pdata->tx_dma_channel = dma_spec.args[0];
877 ret = of_property_match_string(np, "dma-names", "rx");
881 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
886 pdata->rx_dma_channel = dma_spec.args[0];
888 ret = of_property_read_u32(np, "tx-num-evt", &val);
890 pdata->txnumevt = val;
892 ret = of_property_read_u32(np, "rx-num-evt", &val);
894 pdata->rxnumevt = val;
896 ret = of_property_read_u32(np, "sram-size-playback", &val);
898 pdata->sram_size_playback = val;
900 ret = of_property_read_u32(np, "sram-size-capture", &val);
902 pdata->sram_size_capture = val;
908 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
915 static int davinci_mcasp_probe(struct platform_device *pdev)
917 struct davinci_pcm_dma_params *dma_data;
918 struct resource *mem, *ioarea, *res, *dat;
919 struct snd_platform_data *pdata;
920 struct davinci_audio_dev *dev;
923 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
924 dev_err(&pdev->dev, "No platform data supplied\n");
928 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
933 pdata = davinci_mcasp_set_pdata_from_of(pdev);
935 dev_err(&pdev->dev, "no platform data\n");
939 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
942 "\"mpu\" mem resource not found, using index 0\n");
943 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
945 dev_err(&pdev->dev, "no mem resource?\n");
950 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
951 resource_size(mem), pdev->name);
953 dev_err(&pdev->dev, "Audio region already claimed\n");
957 pm_runtime_enable(&pdev->dev);
959 ret = pm_runtime_get_sync(&pdev->dev);
960 if (IS_ERR_VALUE(ret)) {
961 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
965 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
967 dev_err(&pdev->dev, "ioremap failed\n");
969 goto err_release_clk;
972 dev->op_mode = pdata->op_mode;
973 dev->tdm_slots = pdata->tdm_slots;
974 dev->num_serializer = pdata->num_serializer;
975 dev->serial_dir = pdata->serial_dir;
976 dev->version = pdata->version;
977 dev->txnumevt = pdata->txnumevt;
978 dev->rxnumevt = pdata->rxnumevt;
979 dev->dev = &pdev->dev;
981 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
985 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
986 dma_data->asp_chan_q = pdata->asp_chan_q;
987 dma_data->ram_chan_q = pdata->ram_chan_q;
988 dma_data->sram_pool = pdata->sram_pool;
989 dma_data->sram_size = pdata->sram_size_playback;
990 dma_data->dma_addr = dat->start + pdata->tx_dma_offset;
992 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
994 dma_data->channel = res->start;
996 dma_data->channel = pdata->tx_dma_channel;
998 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
999 dma_data->asp_chan_q = pdata->asp_chan_q;
1000 dma_data->ram_chan_q = pdata->ram_chan_q;
1001 dma_data->sram_pool = pdata->sram_pool;
1002 dma_data->sram_size = pdata->sram_size_capture;
1003 dma_data->dma_addr = dat->start + pdata->rx_dma_offset;
1005 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1007 dma_data->channel = res->start;
1009 dma_data->channel = pdata->rx_dma_channel;
1011 dev_set_drvdata(&pdev->dev, dev);
1012 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1013 &davinci_mcasp_dai[pdata->op_mode], 1);
1016 goto err_release_clk;
1018 ret = davinci_soc_platform_register(&pdev->dev);
1020 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1021 goto err_unregister_component;
1026 err_unregister_component:
1027 snd_soc_unregister_component(&pdev->dev);
1029 pm_runtime_put_sync(&pdev->dev);
1030 pm_runtime_disable(&pdev->dev);
1034 static int davinci_mcasp_remove(struct platform_device *pdev)
1037 snd_soc_unregister_component(&pdev->dev);
1038 davinci_soc_platform_unregister(&pdev->dev);
1040 pm_runtime_put_sync(&pdev->dev);
1041 pm_runtime_disable(&pdev->dev);
1046 #ifdef CONFIG_PM_SLEEP
1047 static int davinci_mcasp_suspend(struct device *dev)
1049 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1050 void __iomem *base = a->base;
1052 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
1053 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
1054 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
1055 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
1056 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
1057 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
1058 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1063 static int davinci_mcasp_resume(struct device *dev)
1065 struct davinci_audio_dev *a = dev_get_drvdata(dev);
1066 void __iomem *base = a->base;
1068 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl);
1069 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl);
1070 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt);
1071 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt);
1072 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl);
1073 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl);
1074 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
1080 SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1081 davinci_mcasp_suspend,
1082 davinci_mcasp_resume);
1084 static struct platform_driver davinci_mcasp_driver = {
1085 .probe = davinci_mcasp_probe,
1086 .remove = davinci_mcasp_remove,
1088 .name = "davinci-mcasp",
1089 .owner = THIS_MODULE,
1090 .pm = &davinci_mcasp_pm_ops,
1091 .of_match_table = mcasp_dt_ids,
1095 module_platform_driver(davinci_mcasp_driver);
1097 MODULE_AUTHOR("Steve Chen");
1098 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1099 MODULE_LICENSE("GPL");