2 * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * Author: Nicolin Chen <nicoleotsuka@gmail.com>
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/module.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_data/dma-imx.h>
19 #include <linux/pm_runtime.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
25 #define IDEAL_RATIO_DECIMAL_DEPTH 26
27 #define pair_err(fmt, ...) \
28 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
30 #define pair_dbg(fmt, ...) \
31 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
33 /* Sample rates are aligned with that defined in pcm.h file */
34 static const u8 process_option[][8][2] = {
35 /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
36 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
37 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
38 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
39 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
40 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
41 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
42 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
43 {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
44 {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
45 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
46 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
47 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
48 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
51 /* Corresponding to process_option */
52 static int supported_input_rate[] = {
53 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
54 96000, 176400, 192000,
57 static int supported_asrc_rate[] = {
58 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
62 * The following tables map the relationship between asrc_inclk/asrc_outclk in
63 * fsl_asrc.h and the registers of ASRCSR
65 static unsigned char input_clk_map_imx35[] = {
66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
69 static unsigned char output_clk_map_imx35[] = {
70 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
73 /* i.MX53 uses the same map for input and output */
74 static unsigned char input_clk_map_imx53[] = {
75 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
76 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
79 static unsigned char output_clk_map_imx53[] = {
80 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
81 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
84 static unsigned char *clk_map[2];
89 * It assigns pair by the order of A->C->B because allocation of pair B,
90 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
91 * while pair A and pair C are comparatively independent.
93 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
95 enum asrc_pair_index index = ASRC_INVALID_PAIR;
96 struct fsl_asrc *asrc_priv = pair->asrc_priv;
97 struct device *dev = &asrc_priv->pdev->dev;
98 unsigned long lock_flags;
101 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
103 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
104 if (asrc_priv->pair[i] != NULL)
109 if (i != ASRC_PAIR_B)
113 if (index == ASRC_INVALID_PAIR) {
114 dev_err(dev, "all pairs are busy now\n");
116 } else if (asrc_priv->channel_avail < channels) {
117 dev_err(dev, "can't afford required channels: %d\n", channels);
120 asrc_priv->channel_avail -= channels;
121 asrc_priv->pair[index] = pair;
122 pair->channels = channels;
126 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
134 * It clears the resource from asrc_priv and releases the occupied channels.
136 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
138 struct fsl_asrc *asrc_priv = pair->asrc_priv;
139 enum asrc_pair_index index = pair->index;
140 unsigned long lock_flags;
142 /* Make sure the pair is disabled */
143 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
144 ASRCTR_ASRCEi_MASK(index), 0);
146 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
148 asrc_priv->channel_avail += pair->channels;
149 asrc_priv->pair[index] = NULL;
152 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
156 * Configure input and output thresholds
158 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
160 struct fsl_asrc *asrc_priv = pair->asrc_priv;
161 enum asrc_pair_index index = pair->index;
163 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
164 ASRMCRi_EXTTHRSHi_MASK |
165 ASRMCRi_INFIFO_THRESHOLD_MASK |
166 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
168 ASRMCRi_INFIFO_THRESHOLD(in) |
169 ASRMCRi_OUTFIFO_THRESHOLD(out));
173 * Calculate the total divisor between asrck clock rate and sample rate
175 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
177 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
181 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
182 for (ps = 0; div > 8; ps++)
185 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
189 * Calculate and set the ratio for Ideal Ratio mode only
191 * The ratio is a 32-bit fixed point value with 26 fractional bits.
193 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
194 int inrate, int outrate)
196 struct fsl_asrc *asrc_priv = pair->asrc_priv;
197 enum asrc_pair_index index = pair->index;
202 pair_err("output rate should not be zero\n");
206 /* Calculate the intergal part of the ratio */
207 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
209 /* ... and then the 26 depth decimal part */
212 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
215 if (inrate < outrate)
218 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
225 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
226 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
232 * Configure the assigned ASRC pair
234 * It configures those ASRC registers according to a configuration instance
235 * of struct asrc_config which includes in/output sample rate, width, channel
236 * and clock settings.
238 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
240 struct asrc_config *config = pair->config;
241 struct fsl_asrc *asrc_priv = pair->asrc_priv;
242 enum asrc_pair_index index = pair->index;
243 u32 inrate = config->input_sample_rate, indiv;
244 u32 outrate = config->output_sample_rate, outdiv;
245 bool ideal = config->inclk == INCLK_NONE;
246 u32 clk_index[2], div[2];
247 int in, out, channels;
251 pair_err("invalid pair config\n");
255 /* Validate channels */
256 if (config->channel_num < 1 || config->channel_num > 10) {
257 pair_err("does not support %d channels\n", config->channel_num);
261 /* Validate output width */
262 if (config->output_word_width == ASRC_WIDTH_8_BIT) {
263 pair_err("does not support 8bit width output\n");
267 /* Validate input and output sample rates */
268 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
269 if (inrate == supported_input_rate[in])
272 if (in == ARRAY_SIZE(supported_input_rate)) {
273 pair_err("unsupported input sample rate: %dHz\n", inrate);
277 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
278 if (outrate == supported_asrc_rate[out])
281 if (out == ARRAY_SIZE(supported_asrc_rate)) {
282 pair_err("unsupported output sample rate: %dHz\n", outrate);
286 /* Validate input and output clock sources */
287 clk_index[IN] = clk_map[IN][config->inclk];
288 clk_index[OUT] = clk_map[OUT][config->outclk];
290 /* We only have output clock for ideal ratio mode */
291 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
293 div[IN] = clk_get_rate(clk) / inrate;
295 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
296 inrate, clk_index[ideal ? OUT : IN]);
300 clk = asrc_priv->asrck_clk[clk_index[OUT]];
302 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
304 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
306 div[OUT] = clk_get_rate(clk) / outrate;
309 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
310 outrate, clk_index[OUT]);
314 /* Set the channel number */
315 channels = config->channel_num;
317 if (asrc_priv->channel_bits < 4)
320 /* Update channels for current pair */
321 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
322 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
323 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
325 /* Default setting: Automatic selection for processing mode */
326 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
327 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
328 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
329 ASRCTR_USRi_MASK(index), 0);
331 /* Set the input and output clock sources */
332 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
333 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
334 ASRCSR_AICS(index, clk_index[IN]) |
335 ASRCSR_AOCS(index, clk_index[OUT]));
337 /* Calculate the input clock divisors */
338 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
339 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
341 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
342 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
343 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
344 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
345 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
347 /* Implement word_width configurations */
348 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
349 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
350 ASRMCR1i_OW16(config->output_word_width) |
351 ASRMCR1i_IWD(config->input_word_width));
353 /* Enable BUFFER STALL */
354 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
355 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
357 /* Set default thresholds for input and output FIFO */
358 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
359 ASRC_INPUTFIFO_THRESHOLD);
361 /* Configure the followings only for Ideal Ratio mode */
365 /* Clear ASTSx bit to use Ideal Ratio mode */
366 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
367 ASRCTR_ATSi_MASK(index), 0);
369 /* Enable Ideal Ratio mode */
370 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
371 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
372 ASRCTR_IDR(index) | ASRCTR_USR(index));
374 /* Apply configurations for pre- and post-processing */
375 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
376 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
377 ASRCFG_PREMOD(index, process_option[in][out][0]) |
378 ASRCFG_POSTMOD(index, process_option[in][out][1]));
380 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
384 * Start the assigned ASRC pair
386 * It enables the assigned pair and makes it stopped at the stall level.
388 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
390 struct fsl_asrc *asrc_priv = pair->asrc_priv;
391 enum asrc_pair_index index = pair->index;
392 int reg, retry = 10, i;
394 /* Enable the current pair */
395 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
396 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
398 /* Wait for status of initialization */
401 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
402 reg &= ASRCFG_INIRQi_MASK(index);
403 } while (!reg && --retry);
405 /* Make the input fifo to ASRC STALL level */
406 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
407 for (i = 0; i < pair->channels * 4; i++)
408 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
410 /* Enable overload interrupt */
411 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
415 * Stop the assigned ASRC pair
417 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
419 struct fsl_asrc *asrc_priv = pair->asrc_priv;
420 enum asrc_pair_index index = pair->index;
422 /* Stop the current pair */
423 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
424 ASRCTR_ASRCEi_MASK(index), 0);
428 * Get DMA channel according to the pair and direction.
430 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
432 struct fsl_asrc *asrc_priv = pair->asrc_priv;
433 enum asrc_pair_index index = pair->index;
436 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
438 return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
440 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
442 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
443 struct snd_pcm_hw_params *params,
444 struct snd_soc_dai *dai)
446 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
447 int width = snd_pcm_format_width(params_format(params));
448 struct snd_pcm_runtime *runtime = substream->runtime;
449 struct fsl_asrc_pair *pair = runtime->private_data;
450 unsigned int channels = params_channels(params);
451 unsigned int rate = params_rate(params);
452 struct asrc_config config;
455 ret = fsl_asrc_request_pair(channels, pair);
457 dev_err(dai->dev, "fail to request asrc pair\n");
461 pair->config = &config;
464 width = ASRC_WIDTH_16_BIT;
466 width = ASRC_WIDTH_24_BIT;
468 if (asrc_priv->asrc_width == 16)
469 word_width = ASRC_WIDTH_16_BIT;
471 word_width = ASRC_WIDTH_24_BIT;
473 config.pair = pair->index;
474 config.channel_num = channels;
475 config.inclk = INCLK_NONE;
476 config.outclk = OUTCLK_ASRCK1_CLK;
478 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
479 config.input_word_width = width;
480 config.output_word_width = word_width;
481 config.input_sample_rate = rate;
482 config.output_sample_rate = asrc_priv->asrc_rate;
484 config.input_word_width = word_width;
485 config.output_word_width = width;
486 config.input_sample_rate = asrc_priv->asrc_rate;
487 config.output_sample_rate = rate;
490 ret = fsl_asrc_config_pair(pair);
492 dev_err(dai->dev, "fail to config asrc pair\n");
499 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
500 struct snd_soc_dai *dai)
502 struct snd_pcm_runtime *runtime = substream->runtime;
503 struct fsl_asrc_pair *pair = runtime->private_data;
506 fsl_asrc_release_pair(pair);
511 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
512 struct snd_soc_dai *dai)
514 struct snd_pcm_runtime *runtime = substream->runtime;
515 struct fsl_asrc_pair *pair = runtime->private_data;
518 case SNDRV_PCM_TRIGGER_START:
519 case SNDRV_PCM_TRIGGER_RESUME:
520 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
521 fsl_asrc_start_pair(pair);
523 case SNDRV_PCM_TRIGGER_STOP:
524 case SNDRV_PCM_TRIGGER_SUSPEND:
525 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
526 fsl_asrc_stop_pair(pair);
535 static struct snd_soc_dai_ops fsl_asrc_dai_ops = {
536 .hw_params = fsl_asrc_dai_hw_params,
537 .hw_free = fsl_asrc_dai_hw_free,
538 .trigger = fsl_asrc_dai_trigger,
541 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
543 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
545 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
546 &asrc_priv->dma_params_rx);
551 #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
552 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
553 SNDRV_PCM_FMTBIT_S16_LE | \
554 SNDRV_PCM_FMTBIT_S20_3LE)
556 static struct snd_soc_dai_driver fsl_asrc_dai = {
557 .probe = fsl_asrc_dai_probe,
559 .stream_name = "ASRC-Playback",
562 .rates = FSL_ASRC_RATES,
563 .formats = FSL_ASRC_FORMATS,
566 .stream_name = "ASRC-Capture",
569 .rates = FSL_ASRC_RATES,
570 .formats = FSL_ASRC_FORMATS,
572 .ops = &fsl_asrc_dai_ops,
575 static const struct snd_soc_component_driver fsl_asrc_component = {
576 .name = "fsl-asrc-dai",
579 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
623 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
643 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
684 static struct regmap_config fsl_asrc_regmap_config = {
689 .max_register = REG_ASRMCR1C,
690 .readable_reg = fsl_asrc_readable_reg,
691 .volatile_reg = fsl_asrc_volatile_reg,
692 .writeable_reg = fsl_asrc_writeable_reg,
693 .cache_type = REGCACHE_RBTREE,
697 * Initialize ASRC registers with a default configurations
699 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
701 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
702 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
704 /* Disable interrupt by default */
705 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
707 /* Apply recommended settings for parameters from Reference Manual */
708 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
709 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
710 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
711 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
712 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
714 /* Base address for task queue FIFO. Set to 0x7C */
715 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
716 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
718 /* Set the processing clock for 76KHz to 133M */
719 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
721 /* Set the processing clock for 56KHz to 133M */
722 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
726 * Interrupt handler for ASRC
728 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
730 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
731 struct device *dev = &asrc_priv->pdev->dev;
732 enum asrc_pair_index index;
735 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
737 /* Clean overload error */
738 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
741 * We here use dev_dbg() for all exceptions because ASRC itself does
742 * not care if FIFO overflowed or underrun while a warning in the
743 * interrupt would result a ridged conversion.
745 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
746 if (!asrc_priv->pair[index])
749 if (status & ASRSTR_ATQOL) {
750 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
751 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
754 if (status & ASRSTR_AOOL(index)) {
755 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
756 pair_dbg("Output Task Overload\n");
759 if (status & ASRSTR_AIOL(index)) {
760 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
761 pair_dbg("Input Task Overload\n");
764 if (status & ASRSTR_AODO(index)) {
765 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
766 pair_dbg("Output Data Buffer has overflowed\n");
769 if (status & ASRSTR_AIDU(index)) {
770 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
771 pair_dbg("Input Data Buffer has underflowed\n");
778 static int fsl_asrc_probe(struct platform_device *pdev)
780 struct device_node *np = pdev->dev.of_node;
781 struct fsl_asrc *asrc_priv;
782 struct resource *res;
787 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
791 asrc_priv->pdev = pdev;
792 strcpy(asrc_priv->name, np->name);
794 /* Get the addresses and IRQ */
795 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
796 regs = devm_ioremap_resource(&pdev->dev, res);
798 return PTR_ERR(regs);
800 asrc_priv->paddr = res->start;
802 /* Register regmap and let it prepare core clock */
803 if (of_property_read_bool(np, "big-endian"))
804 fsl_asrc_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
806 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
807 &fsl_asrc_regmap_config);
808 if (IS_ERR(asrc_priv->regmap)) {
809 dev_err(&pdev->dev, "failed to init regmap\n");
810 return PTR_ERR(asrc_priv->regmap);
813 irq = platform_get_irq(pdev, 0);
815 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
819 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
820 asrc_priv->name, asrc_priv);
822 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
826 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
827 if (IS_ERR(asrc_priv->mem_clk)) {
828 dev_err(&pdev->dev, "failed to get mem clock\n");
829 return PTR_ERR(asrc_priv->mem_clk);
832 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
833 if (IS_ERR(asrc_priv->ipg_clk)) {
834 dev_err(&pdev->dev, "failed to get ipg clock\n");
835 return PTR_ERR(asrc_priv->ipg_clk);
838 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
839 sprintf(tmp, "asrck_%x", i);
840 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
841 if (IS_ERR(asrc_priv->asrck_clk[i])) {
842 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
843 return PTR_ERR(asrc_priv->asrck_clk[i]);
847 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-asrc")) {
848 asrc_priv->channel_bits = 3;
849 clk_map[IN] = input_clk_map_imx35;
850 clk_map[OUT] = output_clk_map_imx35;
852 asrc_priv->channel_bits = 4;
853 clk_map[IN] = input_clk_map_imx53;
854 clk_map[OUT] = output_clk_map_imx53;
857 ret = fsl_asrc_init(asrc_priv);
859 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
863 asrc_priv->channel_avail = 10;
865 ret = of_property_read_u32(np, "fsl,asrc-rate",
866 &asrc_priv->asrc_rate);
868 dev_err(&pdev->dev, "failed to get output rate\n");
872 ret = of_property_read_u32(np, "fsl,asrc-width",
873 &asrc_priv->asrc_width);
875 dev_err(&pdev->dev, "failed to get output width\n");
879 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
880 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
881 asrc_priv->asrc_width = 24;
884 platform_set_drvdata(pdev, asrc_priv);
885 pm_runtime_enable(&pdev->dev);
886 spin_lock_init(&asrc_priv->lock);
888 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
891 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
895 ret = devm_snd_soc_register_platform(&pdev->dev, &fsl_asrc_platform);
897 dev_err(&pdev->dev, "failed to register ASoC platform\n");
901 dev_info(&pdev->dev, "driver registered\n");
906 #ifdef CONFIG_PM_RUNTIME
907 static int fsl_asrc_runtime_resume(struct device *dev)
909 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
912 clk_prepare_enable(asrc_priv->mem_clk);
913 clk_prepare_enable(asrc_priv->ipg_clk);
914 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
915 clk_prepare_enable(asrc_priv->asrck_clk[i]);
920 static int fsl_asrc_runtime_suspend(struct device *dev)
922 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
925 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
926 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
927 clk_disable_unprepare(asrc_priv->ipg_clk);
928 clk_disable_unprepare(asrc_priv->mem_clk);
932 #endif /* CONFIG_PM_RUNTIME */
934 #ifdef CONFIG_PM_SLEEP
935 static int fsl_asrc_suspend(struct device *dev)
937 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
939 regcache_cache_only(asrc_priv->regmap, true);
940 regcache_mark_dirty(asrc_priv->regmap);
945 static int fsl_asrc_resume(struct device *dev)
947 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
950 /* Stop all pairs provisionally */
951 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
952 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
953 ASRCTR_ASRCEi_ALL_MASK, 0);
955 /* Restore all registers */
956 regcache_cache_only(asrc_priv->regmap, false);
957 regcache_sync(asrc_priv->regmap);
959 /* Restart enabled pairs */
960 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
961 ASRCTR_ASRCEi_ALL_MASK, asrctr);
965 #endif /* CONFIG_PM_SLEEP */
967 static const struct dev_pm_ops fsl_asrc_pm = {
968 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
969 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
972 static const struct of_device_id fsl_asrc_ids[] = {
973 { .compatible = "fsl,imx35-asrc", },
974 { .compatible = "fsl,imx53-asrc", },
977 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
979 static struct platform_driver fsl_asrc_driver = {
980 .probe = fsl_asrc_probe,
983 .of_match_table = fsl_asrc_ids,
987 module_platform_driver(fsl_asrc_driver);
989 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
990 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
991 MODULE_ALIAS("platform:fsl-asrc");
992 MODULE_LICENSE("GPL v2");