2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
70 u32 val = readl(addr);
71 val = (val & ~clear) | set;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
85 SNDRV_PCM_RATE_CONTINUOUS)
88 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
90 * This driver currently only supports the SSI running in I2S slave mode.
92 * The SSI has a limitation in that the samples must be in the same byte
93 * order as the host CPU. This is because when multiple bytes are written
94 * to the STX register, the bytes and bits must be written in the same
95 * order. The STX is a shift register, so all the bits need to be aligned
96 * (bit-endianness must match byte-endianness). Processors typically write
97 * the bits within a byte in the same order that the bytes of a word are
98 * written in. So if the host CPU is big-endian, then only big-endian
99 * samples will be written to STX properly.
102 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
103 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
104 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
106 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
107 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
108 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
111 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
112 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
113 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
114 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
115 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
116 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
117 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
127 struct fsl_ssi_reg_val {
134 struct fsl_ssi_rxtx_reg_val {
135 struct fsl_ssi_reg_val rx;
136 struct fsl_ssi_reg_val tx;
140 * fsl_ssi_private: per-SSI private data
142 * @ssi: pointer to the SSI's registers
143 * @ssi_phys: physical address of the SSI registers
144 * @irq: IRQ of this SSI
145 * @playback: the number of playback streams opened
146 * @capture: the number of capture streams opened
147 * @cpu_dai: the CPU DAI for this device
148 * @dev_attr: the sysfs device attribute structure
149 * @stats: SSI statistics
150 * @name: name for this device
152 struct fsl_ssi_private {
153 struct ccsr_ssi __iomem *ssi;
156 unsigned int fifo_depth;
157 struct snd_soc_dai_driver cpu_dai_drv;
158 struct platform_device *pdev;
160 enum fsl_ssi_type hw_type;
169 spinlock_t baudclk_lock;
172 struct snd_dmaengine_dai_dma_data dma_params_tx;
173 struct snd_dmaengine_dai_dma_data dma_params_rx;
174 struct imx_dma_data filter_data_tx;
175 struct imx_dma_data filter_data_rx;
176 struct imx_pcm_fiq_params fiq_params;
177 /* Register values for rx/tx configuration */
178 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
203 struct dentry *dbg_dir;
204 struct dentry *dbg_stats;
209 static const struct of_device_id fsl_ssi_ids[] = {
210 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
211 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
212 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
213 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
216 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
219 * fsl_ssi_isr: SSI interrupt handler
221 * Although it's possible to use the interrupt handler to send and receive
222 * data to/from the SSI, we use the DMA instead. Programming is more
223 * complicated, but the performance is much better.
225 * This interrupt handler is used only to gather statistics.
227 * @irq: IRQ of the SSI device
228 * @dev_id: pointer to the ssi_private structure for this SSI device
230 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
232 struct fsl_ssi_private *ssi_private = dev_id;
233 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
234 irqreturn_t ret = IRQ_NONE;
237 __be32 sisr_write_mask = 0;
239 switch (ssi_private->hw_type) {
244 case FSL_SSI_MCP8610:
246 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
247 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
248 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
252 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
253 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
257 /* We got an interrupt, so read the status register to see what we
258 were interrupted for. We mask it with the Interrupt Enable register
259 so that we only check for events that we're interested in.
261 sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
263 if (sisr & CCSR_SSI_SISR_RFRC) {
264 ssi_private->stats.rfrc++;
268 if (sisr & CCSR_SSI_SISR_TFRC) {
269 ssi_private->stats.tfrc++;
273 if (sisr & CCSR_SSI_SISR_CMDAU) {
274 ssi_private->stats.cmdau++;
278 if (sisr & CCSR_SSI_SISR_CMDDU) {
279 ssi_private->stats.cmddu++;
283 if (sisr & CCSR_SSI_SISR_RXT) {
284 ssi_private->stats.rxt++;
288 if (sisr & CCSR_SSI_SISR_RDR1) {
289 ssi_private->stats.rdr1++;
293 if (sisr & CCSR_SSI_SISR_RDR0) {
294 ssi_private->stats.rdr0++;
298 if (sisr & CCSR_SSI_SISR_TDE1) {
299 ssi_private->stats.tde1++;
303 if (sisr & CCSR_SSI_SISR_TDE0) {
304 ssi_private->stats.tde0++;
308 if (sisr & CCSR_SSI_SISR_ROE1) {
309 ssi_private->stats.roe1++;
313 if (sisr & CCSR_SSI_SISR_ROE0) {
314 ssi_private->stats.roe0++;
318 if (sisr & CCSR_SSI_SISR_TUE1) {
319 ssi_private->stats.tue1++;
323 if (sisr & CCSR_SSI_SISR_TUE0) {
324 ssi_private->stats.tue0++;
328 if (sisr & CCSR_SSI_SISR_TFS) {
329 ssi_private->stats.tfs++;
333 if (sisr & CCSR_SSI_SISR_RFS) {
334 ssi_private->stats.rfs++;
338 if (sisr & CCSR_SSI_SISR_TLS) {
339 ssi_private->stats.tls++;
343 if (sisr & CCSR_SSI_SISR_RLS) {
344 ssi_private->stats.rls++;
348 if (sisr & CCSR_SSI_SISR_RFF1) {
349 ssi_private->stats.rff1++;
353 if (sisr & CCSR_SSI_SISR_RFF0) {
354 ssi_private->stats.rff0++;
358 if (sisr & CCSR_SSI_SISR_TFE1) {
359 ssi_private->stats.tfe1++;
363 if (sisr & CCSR_SSI_SISR_TFE0) {
364 ssi_private->stats.tfe0++;
368 sisr2 = sisr & sisr_write_mask;
369 /* Clear the bits that we set */
371 write_ssi(sisr2, &ssi->sisr);
376 #if IS_ENABLED(CONFIG_DEBUG_FS)
377 /* Show the statistics of a flag only if its interrupt is enabled. The
378 * compiler will optimze this code to a no-op if the interrupt is not
381 #define SIER_SHOW(flag, name) \
383 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
384 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
389 * fsl_sysfs_ssi_show: display SSI statistics
391 * Display the statistics for the current SSI device. To avoid confusion,
392 * we only show those counts that are enabled.
394 static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
396 struct fsl_ssi_private *ssi_private = s->private;
398 SIER_SHOW(RFRC_EN, rfrc);
399 SIER_SHOW(TFRC_EN, tfrc);
400 SIER_SHOW(CMDAU_EN, cmdau);
401 SIER_SHOW(CMDDU_EN, cmddu);
402 SIER_SHOW(RXT_EN, rxt);
403 SIER_SHOW(RDR1_EN, rdr1);
404 SIER_SHOW(RDR0_EN, rdr0);
405 SIER_SHOW(TDE1_EN, tde1);
406 SIER_SHOW(TDE0_EN, tde0);
407 SIER_SHOW(ROE1_EN, roe1);
408 SIER_SHOW(ROE0_EN, roe0);
409 SIER_SHOW(TUE1_EN, tue1);
410 SIER_SHOW(TUE0_EN, tue0);
411 SIER_SHOW(TFS_EN, tfs);
412 SIER_SHOW(RFS_EN, rfs);
413 SIER_SHOW(TLS_EN, tls);
414 SIER_SHOW(RLS_EN, rls);
415 SIER_SHOW(RFF1_EN, rff1);
416 SIER_SHOW(RFF0_EN, rff0);
417 SIER_SHOW(TFE1_EN, tfe1);
418 SIER_SHOW(TFE0_EN, tfe0);
423 static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
425 return single_open(file, fsl_ssi_stats_show, inode->i_private);
428 static const struct file_operations fsl_ssi_stats_ops = {
429 .open = fsl_ssi_stats_open,
432 .release = single_release,
435 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
438 ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
439 if (!ssi_private->dbg_dir)
442 ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
443 ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
444 if (!ssi_private->dbg_stats) {
445 debugfs_remove(ssi_private->dbg_dir);
452 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
454 debugfs_remove(ssi_private->dbg_stats);
455 debugfs_remove(ssi_private->dbg_dir);
460 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
466 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
470 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
473 * Enable/Disable all rx/tx config flags at once.
475 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
478 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
479 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
482 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
483 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
484 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
486 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
487 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
488 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
493 * Enable/Disable a ssi configuration. You have to pass either
494 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
496 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
497 struct fsl_ssi_reg_val *vals)
499 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
500 struct fsl_ssi_reg_val *avals;
501 u32 scr_val = read_ssi(&ssi->scr);
502 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
503 !!(scr_val & CCSR_SSI_SCR_RE);
505 /* Find the other direction values rx or tx which we do not want to
507 if (&ssi_private->rxtx_reg_val.rx == vals)
508 avals = &ssi_private->rxtx_reg_val.tx;
510 avals = &ssi_private->rxtx_reg_val.rx;
512 /* If vals should be disabled, start with disabling the unit */
514 u32 scr = vals->scr & (vals->scr ^ avals->scr);
515 write_ssi_mask(&ssi->scr, scr, 0);
519 * We are running on a SoC which does not support online SSI
520 * reconfiguration, so we have to enable all necessary flags at once
521 * even if we do not use them later (capture and playback configuration)
523 if (ssi_private->offline_config) {
524 if ((enable && !nr_active_streams) ||
525 (!enable && nr_active_streams == 1))
526 fsl_ssi_rxtx_config(ssi_private, enable);
532 * Configure single direction units while the SSI unit is running
533 * (online configuration)
536 write_ssi_mask(&ssi->sier, 0, vals->sier);
537 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
538 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
545 * Disabling the necessary flags for one of rx/tx while the
546 * other stream is active is a little bit more difficult. We
547 * have to disable only those flags that differ between both
548 * streams (rx XOR tx) and that are set in the stream that is
549 * disabled now. Otherwise we could alter flags of the other
553 /* These assignments are simply vals without bits set in avals*/
554 sier = vals->sier & (vals->sier ^ avals->sier);
555 srcr = vals->srcr & (vals->srcr ^ avals->srcr);
556 stcr = vals->stcr & (vals->stcr ^ avals->stcr);
558 write_ssi_mask(&ssi->srcr, srcr, 0);
559 write_ssi_mask(&ssi->stcr, stcr, 0);
560 write_ssi_mask(&ssi->sier, sier, 0);
564 /* Enabling of subunits is done after configuration */
566 write_ssi_mask(&ssi->scr, 0, vals->scr);
570 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
572 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
575 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
577 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
581 * Setup rx/tx register values used to enable/disable the streams. These will
582 * be used later in fsl_ssi_config to setup the streams without the need to
583 * check for all different SSI modes.
585 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
587 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
589 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
592 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
596 if (!ssi_private->imx_ac97) {
597 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
603 if (ssi_private->use_dma) {
604 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
607 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608 reg->tx.sier |= CCSR_SSI_SIER_TIE;
611 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
615 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
617 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
620 * Setup the clock control register
622 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
624 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
628 * Enable AC97 mode and startup the SSI
630 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
632 write_ssi(0xff, &ssi->saccdis);
633 write_ssi(0x300, &ssi->saccen);
636 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
637 * codec before a stream is started.
639 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
640 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
642 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
645 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
647 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
649 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
651 fsl_ssi_setup_reg_vals(ssi_private);
653 if (ssi_private->imx_ac97)
654 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
656 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
659 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
660 * to be disabled before updating the registers we set here.
662 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
665 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
666 * enable the transmit and receive FIFO.
668 * FIXME: Little-endian samples require a different shift dir
670 write_ssi_mask(&ssi->scr,
671 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
672 CCSR_SSI_SCR_TFR_CLK_DIS |
673 ssi_private->i2s_mode |
674 (synchronous ? CCSR_SSI_SCR_SYN : 0));
676 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
677 CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
679 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
680 CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
683 * The DC and PM bits are only used if the SSI is the clock master.
687 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
688 * use FIFO 1. We program the transmit water to signal a DMA transfer
689 * if there are only two (or fewer) elements left in the FIFO. Two
690 * elements equals one frame (left channel, right channel). This value,
691 * however, depends on the depth of the transmit buffer.
693 * We set the watermark on the same level as the DMA burstsize. For
694 * fiq it is probably better to use the biggest possible watermark
697 if (ssi_private->use_dma)
698 wm = ssi_private->fifo_depth - 2;
700 wm = ssi_private->fifo_depth;
702 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
703 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
707 * For ac97 interrupts are enabled with the startup of the substream
708 * because it is also running without an active substream. Normally SSI
709 * is only enabled when there is a substream.
711 if (ssi_private->imx_ac97)
712 fsl_ssi_setup_ac97(ssi_private);
719 * fsl_ssi_startup: create a new substream
721 * This is the first function called when a stream is opened.
723 * If this is the first stream open, then grab the IRQ and program most of
726 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
727 struct snd_soc_dai *dai)
729 struct snd_soc_pcm_runtime *rtd = substream->private_data;
730 struct fsl_ssi_private *ssi_private =
731 snd_soc_dai_get_drvdata(rtd->cpu_dai);
734 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
735 * Second, fsl_ssi_setup was already called by ac97_init earlier if
736 * the driver is in ac97 mode.
738 if (!dai->active && !ssi_private->imx_ac97) {
739 fsl_ssi_setup(ssi_private);
740 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
741 ssi_private->baudclk_locked = false;
742 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
749 * fsl_ssi_hw_params - program the sample size
751 * Most of the SSI registers have been programmed in the startup function,
752 * but the word length must be programmed here. Unfortunately, programming
753 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
754 * cause a problem with supporting simultaneous playback and capture. If
755 * the SSI is already playing a stream, then that stream may be temporarily
756 * stopped when you start capture.
758 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
761 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
762 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
764 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
765 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
766 unsigned int channels = params_channels(hw_params);
767 unsigned int sample_size =
768 snd_pcm_format_width(params_format(hw_params));
769 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
770 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
773 * If we're in synchronous mode, and the SSI is already enabled,
774 * then STCCR is already set properly.
776 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
780 * FIXME: The documentation says that SxCCR[WL] should not be
781 * modified while the SSI is enabled. The only time this can
782 * happen is if we're trying to do simultaneous playback and
783 * capture in asynchronous mode. Unfortunately, I have been enable
784 * to get that to work at all on the P1022DS. Therefore, we don't
785 * bother to disable/enable the SSI when setting SxCCR[WL], because
786 * the SSI will stop anyway. Maybe one day, this will get fixed.
789 /* In synchronous mode, the SSI uses STCCR for capture */
790 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
791 ssi_private->cpu_dai_drv.symmetric_rates)
792 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
794 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
796 if (!ssi_private->imx_ac97)
797 write_ssi_mask(&ssi->scr,
798 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
799 channels == 1 ? 0 : ssi_private->i2s_mode);
805 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
807 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
809 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
810 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
811 u32 strcr = 0, stcr, srcr, scr, mask;
813 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
814 scr |= CCSR_SSI_SCR_NET;
816 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
817 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
819 stcr = read_ssi(&ssi->stcr) & ~mask;
820 srcr = read_ssi(&ssi->srcr) & ~mask;
822 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
823 case SND_SOC_DAIFMT_I2S:
824 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
825 case SND_SOC_DAIFMT_CBS_CFS:
826 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
828 case SND_SOC_DAIFMT_CBM_CFM:
829 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
834 scr |= ssi_private->i2s_mode;
836 /* Data on rising edge of bclk, frame low, 1clk before data */
837 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
838 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
840 case SND_SOC_DAIFMT_LEFT_J:
841 /* Data on rising edge of bclk, frame high */
842 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
844 case SND_SOC_DAIFMT_DSP_A:
845 /* Data on rising edge of bclk, frame high, 1clk before data */
846 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
847 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
849 case SND_SOC_DAIFMT_DSP_B:
850 /* Data on rising edge of bclk, frame high */
851 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
852 CCSR_SSI_STCR_TXBIT0;
858 /* DAI clock inversion */
859 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
860 case SND_SOC_DAIFMT_NB_NF:
861 /* Nothing to do for both normal cases */
863 case SND_SOC_DAIFMT_IB_NF:
864 /* Invert bit clock */
865 strcr ^= CCSR_SSI_STCR_TSCKP;
867 case SND_SOC_DAIFMT_NB_IF:
868 /* Invert frame clock */
869 strcr ^= CCSR_SSI_STCR_TFSI;
871 case SND_SOC_DAIFMT_IB_IF:
872 /* Invert both clocks */
873 strcr ^= CCSR_SSI_STCR_TSCKP;
874 strcr ^= CCSR_SSI_STCR_TFSI;
880 /* DAI clock master masks */
881 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
882 case SND_SOC_DAIFMT_CBS_CFS:
883 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
884 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
886 case SND_SOC_DAIFMT_CBM_CFM:
887 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
896 if (ssi_private->cpu_dai_drv.symmetric_rates) {
897 /* Need to clear RXDIR when using SYNC mode */
898 srcr &= ~CCSR_SSI_SRCR_RXDIR;
899 scr |= CCSR_SSI_SCR_SYN;
902 write_ssi(stcr, &ssi->stcr);
903 write_ssi(srcr, &ssi->srcr);
904 write_ssi(scr, &ssi->scr);
910 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
912 * Note: This function can be only called when using SSI as DAI master
914 * Quick instruction for parameters:
915 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
916 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
918 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
919 int clk_id, unsigned int freq, int dir)
921 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
922 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
923 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
924 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
925 unsigned long flags, clkrate, baudrate, tmprate;
926 u64 sub, savesub = 100000;
928 /* Don't apply it to any non-baudclk circumstance */
929 if (IS_ERR(ssi_private->baudclk))
932 /* It should be already enough to divide clock by setting pm alone */
936 factor = (div2 + 1) * (7 * psr + 1) * 2;
938 for (i = 0; i < 255; i++) {
939 /* The bclk rate must be smaller than 1/5 sysclk rate */
940 if (factor * (i + 1) < 5)
943 tmprate = freq * factor * (i + 2);
944 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
946 do_div(clkrate, factor);
947 afreq = (u32)clkrate / (i + 1);
951 else if (freq / afreq == 1)
953 else if (afreq / freq == 1)
958 /* Calculate the fraction */
973 /* No proper pm found if it is still remaining the initial value */
975 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
979 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
980 (psr ? CCSR_SSI_SxCCR_PSR : 0);
981 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
983 if (dir == SND_SOC_CLOCK_OUT || synchronous)
984 write_ssi_mask(&ssi->stccr, mask, stccr);
986 write_ssi_mask(&ssi->srccr, mask, stccr);
988 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
989 if (!ssi_private->baudclk_locked) {
990 ret = clk_set_rate(ssi_private->baudclk, baudrate);
992 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
993 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
996 ssi_private->baudclk_locked = true;
998 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1004 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1006 * Note: This function can be only called when using SSI as DAI master
1008 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1009 u32 rx_mask, int slots, int slot_width)
1011 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1012 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1015 /* The slot number should be >= 2 if using Network mode or I2S mode */
1016 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
1017 if (val && slots < 2) {
1018 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1022 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
1023 CCSR_SSI_SxCCR_DC(slots));
1024 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
1025 CCSR_SSI_SxCCR_DC(slots));
1027 /* The register SxMSKs needs SSI to provide essential clock due to
1028 * hardware design. So we here temporarily enable SSI to set them.
1030 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
1031 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
1033 write_ssi(tx_mask, &ssi->stmsk);
1034 write_ssi(rx_mask, &ssi->srmsk);
1036 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
1042 * fsl_ssi_trigger: start and stop the DMA transfer.
1044 * This function is called by ALSA to start, stop, pause, and resume the DMA
1047 * The DMA channel is in external master start and pause mode, which
1048 * means the SSI completely controls the flow of data.
1050 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1051 struct snd_soc_dai *dai)
1053 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1054 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1055 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1056 unsigned long flags;
1059 case SNDRV_PCM_TRIGGER_START:
1060 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1061 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1062 fsl_ssi_tx_config(ssi_private, true);
1064 fsl_ssi_rx_config(ssi_private, true);
1067 case SNDRV_PCM_TRIGGER_STOP:
1068 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1069 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1070 fsl_ssi_tx_config(ssi_private, false);
1072 fsl_ssi_rx_config(ssi_private, false);
1074 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
1075 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
1076 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1077 ssi_private->baudclk_locked = false;
1078 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1086 if (ssi_private->imx_ac97) {
1087 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1088 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1090 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1096 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1098 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1100 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
1101 dai->playback_dma_data = &ssi_private->dma_params_tx;
1102 dai->capture_dma_data = &ssi_private->dma_params_rx;
1108 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1109 .startup = fsl_ssi_startup,
1110 .hw_params = fsl_ssi_hw_params,
1111 .set_fmt = fsl_ssi_set_dai_fmt,
1112 .set_sysclk = fsl_ssi_set_dai_sysclk,
1113 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1114 .trigger = fsl_ssi_trigger,
1117 /* Template for the CPU dai driver structure */
1118 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1119 .probe = fsl_ssi_dai_probe,
1123 .rates = FSLSSI_I2S_RATES,
1124 .formats = FSLSSI_I2S_FORMATS,
1129 .rates = FSLSSI_I2S_RATES,
1130 .formats = FSLSSI_I2S_FORMATS,
1132 .ops = &fsl_ssi_dai_ops,
1135 static const struct snd_soc_component_driver fsl_ssi_component = {
1139 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1142 .stream_name = "AC97 Playback",
1145 .rates = SNDRV_PCM_RATE_8000_48000,
1146 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1149 .stream_name = "AC97 Capture",
1152 .rates = SNDRV_PCM_RATE_48000,
1153 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1155 .ops = &fsl_ssi_dai_ops,
1159 static struct fsl_ssi_private *fsl_ac97_data;
1161 static void fsl_ssi_ac97_init(void)
1163 fsl_ssi_setup(fsl_ac97_data);
1166 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1169 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1178 write_ssi(lreg, &ssi->sacadd);
1181 write_ssi(lval , &ssi->sacdat);
1183 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1188 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1191 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1193 unsigned short val = -1;
1196 lreg = (reg & 0x7f) << 12;
1197 write_ssi(lreg, &ssi->sacadd);
1198 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1203 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1208 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1209 .read = fsl_ssi_ac97_read,
1210 .write = fsl_ssi_ac97_write,
1214 * Make every character in a string lower-case
1216 static void make_lowercase(char *s)
1222 if ((c >= 'A') && (c <= 'Z'))
1223 *p = c + ('a' - 'A');
1228 static int fsl_ssi_probe(struct platform_device *pdev)
1230 struct fsl_ssi_private *ssi_private;
1232 struct device_attribute *dev_attr = NULL;
1233 struct device_node *np = pdev->dev.of_node;
1234 const struct of_device_id *of_id;
1235 enum fsl_ssi_type hw_type;
1236 const char *p, *sprop;
1237 const uint32_t *iprop;
1238 struct resource res;
1243 /* SSIs that are not connected on the board should have a
1244 * status = "disabled"
1245 * property in their device tree nodes.
1247 if (!of_device_is_available(np))
1250 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1253 hw_type = (enum fsl_ssi_type) of_id->data;
1255 /* We only support the SSI in "I2S Slave" mode */
1256 sprop = of_get_property(np, "fsl,mode", NULL);
1258 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1261 if (!strcmp(sprop, "ac97-slave")) {
1263 } else if (strcmp(sprop, "i2s-slave")) {
1264 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
1268 /* The DAI name is the last part of the full name of the node. */
1269 p = strrchr(np->full_name, '/') + 1;
1270 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1273 dev_err(&pdev->dev, "could not allocate DAI object\n");
1277 strcpy(ssi_private->name, p);
1279 ssi_private->use_dma = !of_property_read_bool(np,
1280 "fsl,fiq-stream-filter");
1281 ssi_private->hw_type = hw_type;
1284 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1285 sizeof(fsl_ssi_ac97_dai));
1287 fsl_ac97_data = ssi_private;
1288 ssi_private->imx_ac97 = true;
1290 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1292 /* Initialize this copy of the CPU DAI driver structure */
1293 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1294 sizeof(fsl_ssi_dai_template));
1296 ssi_private->cpu_dai_drv.name = ssi_private->name;
1298 /* Get the addresses and IRQ */
1299 ret = of_address_to_resource(np, 0, &res);
1301 dev_err(&pdev->dev, "could not determine device resources\n");
1304 ssi_private->ssi = of_iomap(np, 0);
1305 if (!ssi_private->ssi) {
1306 dev_err(&pdev->dev, "could not map device resources\n");
1309 ssi_private->ssi_phys = res.start;
1311 ssi_private->irq = irq_of_parse_and_map(np, 0);
1312 if (!ssi_private->irq) {
1313 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1317 /* Are the RX and the TX clocks locked? */
1318 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1319 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1320 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1321 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1324 /* Determine the FIFO depth. */
1325 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1327 ssi_private->fifo_depth = be32_to_cpup(iprop);
1329 /* Older 8610 DTs didn't have the fifo-depth property */
1330 ssi_private->fifo_depth = 8;
1332 ssi_private->baudclk_locked = false;
1333 spin_lock_init(&ssi_private->baudclk_lock);
1336 * imx51 and later SoCs have a slightly different IP that allows the
1337 * SSI configuration while the SSI unit is running.
1339 * More important, it is necessary on those SoCs to configure the
1340 * sperate TX/RX DMA bits just before starting the stream
1341 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1342 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1343 * how the SDMA unit handles the DMA request.
1345 * SDMA units are present on devices starting at imx35 but the imx35
1346 * reference manual states that the DMA bits should not be changed
1347 * while the SSI unit is running (SSIEN). So we support the necessary
1348 * online configuration of fsl-ssi starting at imx51.
1351 case FSL_SSI_MCP8610:
1354 ssi_private->offline_config = true;
1357 ssi_private->offline_config = false;
1361 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1362 hw_type == FSL_SSI_MX35) {
1364 ssi_private->ssi_on_imx = true;
1366 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1367 if (IS_ERR(ssi_private->clk)) {
1368 ret = PTR_ERR(ssi_private->clk);
1369 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1372 ret = clk_prepare_enable(ssi_private->clk);
1374 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1379 /* For those SLAVE implementations, we ingore non-baudclk cases
1380 * and, instead, abandon MASTER mode that needs baud clock.
1382 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1383 if (IS_ERR(ssi_private->baudclk))
1384 dev_warn(&pdev->dev, "could not get baud clock: %ld\n",
1385 PTR_ERR(ssi_private->baudclk));
1387 clk_prepare_enable(ssi_private->baudclk);
1390 * We have burstsize be "fifo_depth - 2" to match the SSI
1391 * watermark setting in fsl_ssi_startup().
1393 ssi_private->dma_params_tx.maxburst =
1394 ssi_private->fifo_depth - 2;
1395 ssi_private->dma_params_rx.maxburst =
1396 ssi_private->fifo_depth - 2;
1397 ssi_private->dma_params_tx.addr =
1398 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1399 ssi_private->dma_params_rx.addr =
1400 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1401 ssi_private->dma_params_tx.filter_data =
1402 &ssi_private->filter_data_tx;
1403 ssi_private->dma_params_rx.filter_data =
1404 &ssi_private->filter_data_rx;
1405 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1406 ssi_private->use_dma) {
1408 * FIXME: This is a temporary solution until all
1409 * necessary dma drivers support the generic dma
1412 ret = of_property_read_u32_array(pdev->dev.of_node,
1413 "fsl,ssi-dma-events", dma_events, 2);
1414 if (ret && ssi_private->use_dma) {
1415 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1420 shared = of_device_is_compatible(of_get_parent(np),
1423 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1424 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1425 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1426 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1430 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1431 * different writeable interrupt status registers.
1433 if (ssi_private->use_dma) {
1434 /* The 'name' should not have any slashes in it. */
1435 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1436 fsl_ssi_isr, 0, ssi_private->name,
1438 ssi_private->irq_stats = true;
1440 dev_err(&pdev->dev, "could not claim irq %u\n",
1446 /* Register with ASoC */
1447 dev_set_drvdata(&pdev->dev, ssi_private);
1449 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1450 &ssi_private->cpu_dai_drv, 1);
1452 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1456 ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1460 if (ssi_private->ssi_on_imx) {
1461 if (!ssi_private->use_dma) {
1464 * Some boards use an incompatible codec. To get it
1465 * working, we are using imx-fiq-pcm-audio, that
1466 * can handle those codecs. DMA is not possible in this
1470 ssi_private->fiq_params.irq = ssi_private->irq;
1471 ssi_private->fiq_params.base = ssi_private->ssi;
1472 ssi_private->fiq_params.dma_params_rx =
1473 &ssi_private->dma_params_rx;
1474 ssi_private->fiq_params.dma_params_tx =
1475 &ssi_private->dma_params_tx;
1477 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1481 ret = imx_pcm_dma_init(pdev);
1488 * If codec-handle property is missing from SSI node, we assume
1489 * that the machine driver uses new binding which does not require
1490 * SSI driver to trigger machine driver's probe.
1492 if (!of_get_property(np, "codec-handle", NULL)) {
1493 ssi_private->new_binding = true;
1497 /* Trigger the machine driver's probe function. The platform driver
1498 * name of the machine driver is taken from /compatible property of the
1499 * device tree. We also pass the address of the CPU DAI driver
1502 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1503 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1504 p = strrchr(sprop, ',');
1507 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1508 make_lowercase(name);
1511 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1512 if (IS_ERR(ssi_private->pdev)) {
1513 ret = PTR_ERR(ssi_private->pdev);
1514 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1519 if (ssi_private->imx_ac97)
1520 fsl_ssi_ac97_init();
1525 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1526 imx_pcm_fiq_exit(pdev);
1529 fsl_ssi_debugfs_remove(ssi_private);
1532 snd_soc_unregister_component(&pdev->dev);
1535 device_remove_file(&pdev->dev, dev_attr);
1538 if (ssi_private->ssi_on_imx) {
1539 if (!IS_ERR(ssi_private->baudclk))
1540 clk_disable_unprepare(ssi_private->baudclk);
1541 clk_disable_unprepare(ssi_private->clk);
1545 if (ssi_private->irq_stats)
1546 irq_dispose_mapping(ssi_private->irq);
1551 static int fsl_ssi_remove(struct platform_device *pdev)
1553 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1555 fsl_ssi_debugfs_remove(ssi_private);
1557 if (!ssi_private->new_binding)
1558 platform_device_unregister(ssi_private->pdev);
1559 snd_soc_unregister_component(&pdev->dev);
1560 if (ssi_private->ssi_on_imx) {
1561 if (!IS_ERR(ssi_private->baudclk))
1562 clk_disable_unprepare(ssi_private->baudclk);
1563 clk_disable_unprepare(ssi_private->clk);
1565 if (ssi_private->irq_stats)
1566 irq_dispose_mapping(ssi_private->irq);
1571 static struct platform_driver fsl_ssi_driver = {
1573 .name = "fsl-ssi-dai",
1574 .owner = THIS_MODULE,
1575 .of_match_table = fsl_ssi_ids,
1577 .probe = fsl_ssi_probe,
1578 .remove = fsl_ssi_remove,
1581 module_platform_driver(fsl_ssi_driver);
1583 MODULE_ALIAS("platform:fsl-ssi-dai");
1584 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1585 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1586 MODULE_LICENSE("GPL v2");