2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
69 u32 val = readl(addr);
70 val = (val & ~clear) | set;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
110 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
111 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
112 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
113 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
114 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
123 struct fsl_ssi_reg_val {
130 struct fsl_ssi_rxtx_reg_val {
131 struct fsl_ssi_reg_val rx;
132 struct fsl_ssi_reg_val tx;
136 * fsl_ssi_private: per-SSI private data
138 * @ssi: pointer to the SSI's registers
139 * @ssi_phys: physical address of the SSI registers
140 * @irq: IRQ of this SSI
141 * @playback: the number of playback streams opened
142 * @capture: the number of capture streams opened
143 * @cpu_dai: the CPU DAI for this device
144 * @dev_attr: the sysfs device attribute structure
145 * @stats: SSI statistics
147 struct fsl_ssi_private {
148 struct ccsr_ssi __iomem *ssi;
151 unsigned int fifo_depth;
152 struct snd_soc_dai_driver cpu_dai_drv;
153 struct platform_device *pdev;
154 unsigned int dai_fmt;
156 enum fsl_ssi_type hw_type;
161 spinlock_t baudclk_lock;
164 struct snd_dmaengine_dai_dma_data dma_params_tx;
165 struct snd_dmaengine_dai_dma_data dma_params_rx;
166 struct imx_pcm_fiq_params fiq_params;
167 /* Register values for rx/tx configuration */
168 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
170 struct fsl_ssi_dbg dbg_stats;
173 static const struct of_device_id fsl_ssi_ids[] = {
174 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
175 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
176 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
177 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
180 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
182 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
184 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
187 static bool fsl_ssi_on_imx(struct fsl_ssi_private *ssi_private)
189 switch (ssi_private->hw_type) {
194 case FSL_SSI_MCP8610:
202 * imx51 and later SoCs have a slightly different IP that allows the
203 * SSI configuration while the SSI unit is running.
205 * More important, it is necessary on those SoCs to configure the
206 * sperate TX/RX DMA bits just before starting the stream
207 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
208 * sends any DMA requests to the SDMA unit, otherwise it is not defined
209 * how the SDMA unit handles the DMA request.
211 * SDMA units are present on devices starting at imx35 but the imx35
212 * reference manual states that the DMA bits should not be changed
213 * while the SSI unit is running (SSIEN). So we support the necessary
214 * online configuration of fsl-ssi starting at imx51.
216 static bool fsl_ssi_offline_config(struct fsl_ssi_private *ssi_private)
218 switch (ssi_private->hw_type) {
219 case FSL_SSI_MCP8610:
231 * fsl_ssi_isr: SSI interrupt handler
233 * Although it's possible to use the interrupt handler to send and receive
234 * data to/from the SSI, we use the DMA instead. Programming is more
235 * complicated, but the performance is much better.
237 * This interrupt handler is used only to gather statistics.
239 * @irq: IRQ of the SSI device
240 * @dev_id: pointer to the ssi_private structure for this SSI device
242 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
244 struct fsl_ssi_private *ssi_private = dev_id;
245 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
248 __be32 sisr_write_mask = 0;
250 switch (ssi_private->hw_type) {
255 case FSL_SSI_MCP8610:
257 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
258 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
259 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
263 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
264 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
268 /* We got an interrupt, so read the status register to see what we
269 were interrupted for. We mask it with the Interrupt Enable register
270 so that we only check for events that we're interested in.
272 sisr = read_ssi(&ssi->sisr);
274 sisr2 = sisr & sisr_write_mask;
275 /* Clear the bits that we set */
277 write_ssi(sisr2, &ssi->sisr);
279 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
285 * Enable/Disable all rx/tx config flags at once.
287 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
290 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
291 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
294 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
295 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
296 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
298 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
299 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
300 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
305 * Calculate the bits that have to be disabled for the current stream that is
306 * getting disabled. This keeps the bits enabled that are necessary for the
307 * second stream to work if 'stream_active' is true.
309 * Detailed calculation:
310 * These are the values that need to be active after disabling. For non-active
311 * second stream, this is 0:
312 * vals_stream * !!stream_active
314 * The following computes the overall differences between the setup for the
315 * to-disable stream and the active stream, a simple XOR:
316 * vals_disable ^ (vals_stream * !!(stream_active))
318 * The full expression adds a mask on all values we care about
320 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
322 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
325 * Enable/Disable a ssi configuration. You have to pass either
326 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
328 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
329 struct fsl_ssi_reg_val *vals)
331 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
332 struct fsl_ssi_reg_val *avals;
333 u32 scr_val = read_ssi(&ssi->scr);
334 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
335 !!(scr_val & CCSR_SSI_SCR_RE);
338 if (nr_active_streams - 1 > 0)
343 /* Find the other direction values rx or tx which we do not want to
345 if (&ssi_private->rxtx_reg_val.rx == vals)
346 avals = &ssi_private->rxtx_reg_val.tx;
348 avals = &ssi_private->rxtx_reg_val.rx;
350 /* If vals should be disabled, start with disabling the unit */
352 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
354 write_ssi_mask(&ssi->scr, scr, 0);
358 * We are running on a SoC which does not support online SSI
359 * reconfiguration, so we have to enable all necessary flags at once
360 * even if we do not use them later (capture and playback configuration)
362 if (fsl_ssi_offline_config(ssi_private)) {
363 if ((enable && !nr_active_streams) ||
364 (!enable && !keep_active))
365 fsl_ssi_rxtx_config(ssi_private, enable);
371 * Configure single direction units while the SSI unit is running
372 * (online configuration)
375 write_ssi_mask(&ssi->sier, 0, vals->sier);
376 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
377 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
384 * Disabling the necessary flags for one of rx/tx while the
385 * other stream is active is a little bit more difficult. We
386 * have to disable only those flags that differ between both
387 * streams (rx XOR tx) and that are set in the stream that is
388 * disabled now. Otherwise we could alter flags of the other
392 /* These assignments are simply vals without bits set in avals*/
393 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
395 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
397 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
400 write_ssi_mask(&ssi->srcr, srcr, 0);
401 write_ssi_mask(&ssi->stcr, stcr, 0);
402 write_ssi_mask(&ssi->sier, sier, 0);
406 /* Enabling of subunits is done after configuration */
408 write_ssi_mask(&ssi->scr, 0, vals->scr);
412 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
414 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
417 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
419 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
423 * Setup rx/tx register values used to enable/disable the streams. These will
424 * be used later in fsl_ssi_config to setup the streams without the need to
425 * check for all different SSI modes.
427 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
429 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
431 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
432 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
434 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
435 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
438 if (!fsl_ssi_is_ac97(ssi_private)) {
439 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
440 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
441 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
442 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
445 if (ssi_private->use_dma) {
446 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
447 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
449 reg->rx.sier |= CCSR_SSI_SIER_RIE;
450 reg->tx.sier |= CCSR_SSI_SIER_TIE;
453 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
454 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
457 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
459 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
462 * Setup the clock control register
464 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
466 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
470 * Enable AC97 mode and startup the SSI
472 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
474 write_ssi(0xff, &ssi->saccdis);
475 write_ssi(0x300, &ssi->saccen);
478 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
479 * codec before a stream is started.
481 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
482 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
484 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
488 * fsl_ssi_startup: create a new substream
490 * This is the first function called when a stream is opened.
492 * If this is the first stream open, then grab the IRQ and program most of
495 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
496 struct snd_soc_dai *dai)
498 struct snd_soc_pcm_runtime *rtd = substream->private_data;
499 struct fsl_ssi_private *ssi_private =
500 snd_soc_dai_get_drvdata(rtd->cpu_dai);
503 if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) {
504 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
505 ssi_private->baudclk_locked = false;
506 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
509 /* When using dual fifo mode, it is safer to ensure an even period
510 * size. If appearing to an odd number while DMA always starts its
511 * task from fifo0, fifo1 would be neglected at the end of each
512 * period. But SSI would still access fifo1 with an invalid data.
514 if (ssi_private->use_dual_fifo)
515 snd_pcm_hw_constraint_step(substream->runtime, 0,
516 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
522 * fsl_ssi_hw_params - program the sample size
524 * Most of the SSI registers have been programmed in the startup function,
525 * but the word length must be programmed here. Unfortunately, programming
526 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
527 * cause a problem with supporting simultaneous playback and capture. If
528 * the SSI is already playing a stream, then that stream may be temporarily
529 * stopped when you start capture.
531 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
534 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
535 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
537 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
538 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
539 unsigned int channels = params_channels(hw_params);
540 unsigned int sample_size =
541 snd_pcm_format_width(params_format(hw_params));
542 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
543 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
546 * If we're in synchronous mode, and the SSI is already enabled,
547 * then STCCR is already set properly.
549 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
553 * FIXME: The documentation says that SxCCR[WL] should not be
554 * modified while the SSI is enabled. The only time this can
555 * happen is if we're trying to do simultaneous playback and
556 * capture in asynchronous mode. Unfortunately, I have been enable
557 * to get that to work at all on the P1022DS. Therefore, we don't
558 * bother to disable/enable the SSI when setting SxCCR[WL], because
559 * the SSI will stop anyway. Maybe one day, this will get fixed.
562 /* In synchronous mode, the SSI uses STCCR for capture */
563 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
564 ssi_private->cpu_dai_drv.symmetric_rates)
565 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
567 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
569 if (!fsl_ssi_is_ac97(ssi_private))
570 write_ssi_mask(&ssi->scr,
571 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
572 channels == 1 ? 0 : ssi_private->i2s_mode);
578 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
580 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
582 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
583 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
584 u32 strcr = 0, stcr, srcr, scr, mask;
587 ssi_private->dai_fmt = fmt;
589 fsl_ssi_setup_reg_vals(ssi_private);
591 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
593 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
594 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
596 stcr = read_ssi(&ssi->stcr) & ~mask;
597 srcr = read_ssi(&ssi->srcr) & ~mask;
599 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
600 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
601 case SND_SOC_DAIFMT_I2S:
602 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
603 case SND_SOC_DAIFMT_CBS_CFS:
604 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
606 case SND_SOC_DAIFMT_CBM_CFM:
607 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
613 /* Data on rising edge of bclk, frame low, 1clk before data */
614 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
615 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
617 case SND_SOC_DAIFMT_LEFT_J:
618 /* Data on rising edge of bclk, frame high */
619 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
621 case SND_SOC_DAIFMT_DSP_A:
622 /* Data on rising edge of bclk, frame high, 1clk before data */
623 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
624 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
626 case SND_SOC_DAIFMT_DSP_B:
627 /* Data on rising edge of bclk, frame high */
628 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
629 CCSR_SSI_STCR_TXBIT0;
631 case SND_SOC_DAIFMT_AC97:
632 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
637 scr |= ssi_private->i2s_mode;
639 /* DAI clock inversion */
640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
641 case SND_SOC_DAIFMT_NB_NF:
642 /* Nothing to do for both normal cases */
644 case SND_SOC_DAIFMT_IB_NF:
645 /* Invert bit clock */
646 strcr ^= CCSR_SSI_STCR_TSCKP;
648 case SND_SOC_DAIFMT_NB_IF:
649 /* Invert frame clock */
650 strcr ^= CCSR_SSI_STCR_TFSI;
652 case SND_SOC_DAIFMT_IB_IF:
653 /* Invert both clocks */
654 strcr ^= CCSR_SSI_STCR_TSCKP;
655 strcr ^= CCSR_SSI_STCR_TFSI;
661 /* DAI clock master masks */
662 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
663 case SND_SOC_DAIFMT_CBS_CFS:
664 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
665 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
667 case SND_SOC_DAIFMT_CBM_CFM:
668 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
677 if (ssi_private->cpu_dai_drv.symmetric_rates) {
678 /* Need to clear RXDIR when using SYNC mode */
679 srcr &= ~CCSR_SSI_SRCR_RXDIR;
680 scr |= CCSR_SSI_SCR_SYN;
683 write_ssi(stcr, &ssi->stcr);
684 write_ssi(srcr, &ssi->srcr);
685 write_ssi(scr, &ssi->scr);
688 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
689 * use FIFO 1. We program the transmit water to signal a DMA transfer
690 * if there are only two (or fewer) elements left in the FIFO. Two
691 * elements equals one frame (left channel, right channel). This value,
692 * however, depends on the depth of the transmit buffer.
694 * We set the watermark on the same level as the DMA burstsize. For
695 * fiq it is probably better to use the biggest possible watermark
698 if (ssi_private->use_dma)
699 wm = ssi_private->fifo_depth - 2;
701 wm = ssi_private->fifo_depth;
703 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
704 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
707 if (ssi_private->use_dual_fifo) {
708 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
709 CCSR_SSI_SRCR_RFEN1);
710 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
711 CCSR_SSI_STCR_TFEN1);
712 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
713 CCSR_SSI_SCR_TCH_EN);
716 if (fmt & SND_SOC_DAIFMT_AC97)
717 fsl_ssi_setup_ac97(ssi_private);
723 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
725 * Note: This function can be only called when using SSI as DAI master
727 * Quick instruction for parameters:
728 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
729 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
731 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
732 int clk_id, unsigned int freq, int dir)
734 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
735 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
736 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
737 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
738 unsigned long flags, clkrate, baudrate, tmprate;
739 u64 sub, savesub = 100000;
741 /* Don't apply it to any non-baudclk circumstance */
742 if (IS_ERR(ssi_private->baudclk))
745 /* It should be already enough to divide clock by setting pm alone */
749 factor = (div2 + 1) * (7 * psr + 1) * 2;
751 for (i = 0; i < 255; i++) {
752 /* The bclk rate must be smaller than 1/5 sysclk rate */
753 if (factor * (i + 1) < 5)
756 tmprate = freq * factor * (i + 2);
757 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
759 do_div(clkrate, factor);
760 afreq = (u32)clkrate / (i + 1);
764 else if (freq / afreq == 1)
766 else if (afreq / freq == 1)
771 /* Calculate the fraction */
786 /* No proper pm found if it is still remaining the initial value */
788 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
792 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
793 (psr ? CCSR_SSI_SxCCR_PSR : 0);
794 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
796 if (dir == SND_SOC_CLOCK_OUT || synchronous)
797 write_ssi_mask(&ssi->stccr, mask, stccr);
799 write_ssi_mask(&ssi->srccr, mask, stccr);
801 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
802 if (!ssi_private->baudclk_locked) {
803 ret = clk_set_rate(ssi_private->baudclk, baudrate);
805 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
806 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
809 ssi_private->baudclk_locked = true;
811 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
817 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
819 * Note: This function can be only called when using SSI as DAI master
821 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
822 u32 rx_mask, int slots, int slot_width)
824 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
825 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
828 /* The slot number should be >= 2 if using Network mode or I2S mode */
829 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
830 if (val && slots < 2) {
831 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
835 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
836 CCSR_SSI_SxCCR_DC(slots));
837 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
838 CCSR_SSI_SxCCR_DC(slots));
840 /* The register SxMSKs needs SSI to provide essential clock due to
841 * hardware design. So we here temporarily enable SSI to set them.
843 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
844 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
846 write_ssi(tx_mask, &ssi->stmsk);
847 write_ssi(rx_mask, &ssi->srmsk);
849 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
855 * fsl_ssi_trigger: start and stop the DMA transfer.
857 * This function is called by ALSA to start, stop, pause, and resume the DMA
860 * The DMA channel is in external master start and pause mode, which
861 * means the SSI completely controls the flow of data.
863 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
864 struct snd_soc_dai *dai)
866 struct snd_soc_pcm_runtime *rtd = substream->private_data;
867 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
868 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
872 case SNDRV_PCM_TRIGGER_START:
873 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
874 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
875 fsl_ssi_tx_config(ssi_private, true);
877 fsl_ssi_rx_config(ssi_private, true);
880 case SNDRV_PCM_TRIGGER_STOP:
881 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
882 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
883 fsl_ssi_tx_config(ssi_private, false);
885 fsl_ssi_rx_config(ssi_private, false);
887 if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) &
888 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
889 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
890 ssi_private->baudclk_locked = false;
891 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
899 if (fsl_ssi_is_ac97(ssi_private)) {
900 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
901 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
903 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
909 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
911 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
913 if (fsl_ssi_on_imx(ssi_private) && ssi_private->use_dma) {
914 dai->playback_dma_data = &ssi_private->dma_params_tx;
915 dai->capture_dma_data = &ssi_private->dma_params_rx;
921 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
922 .startup = fsl_ssi_startup,
923 .hw_params = fsl_ssi_hw_params,
924 .set_fmt = fsl_ssi_set_dai_fmt,
925 .set_sysclk = fsl_ssi_set_dai_sysclk,
926 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
927 .trigger = fsl_ssi_trigger,
930 /* Template for the CPU dai driver structure */
931 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
932 .probe = fsl_ssi_dai_probe,
936 .rates = FSLSSI_I2S_RATES,
937 .formats = FSLSSI_I2S_FORMATS,
942 .rates = FSLSSI_I2S_RATES,
943 .formats = FSLSSI_I2S_FORMATS,
945 .ops = &fsl_ssi_dai_ops,
948 static const struct snd_soc_component_driver fsl_ssi_component = {
952 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
955 .stream_name = "AC97 Playback",
958 .rates = SNDRV_PCM_RATE_8000_48000,
959 .formats = SNDRV_PCM_FMTBIT_S16_LE,
962 .stream_name = "AC97 Capture",
965 .rates = SNDRV_PCM_RATE_48000,
966 .formats = SNDRV_PCM_FMTBIT_S16_LE,
968 .ops = &fsl_ssi_dai_ops,
972 static struct fsl_ssi_private *fsl_ac97_data;
974 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
977 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
986 write_ssi(lreg, &ssi->sacadd);
989 write_ssi(lval , &ssi->sacdat);
991 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
996 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
999 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1001 unsigned short val = -1;
1004 lreg = (reg & 0x7f) << 12;
1005 write_ssi(lreg, &ssi->sacadd);
1006 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1011 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1016 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1017 .read = fsl_ssi_ac97_read,
1018 .write = fsl_ssi_ac97_write,
1022 * Make every character in a string lower-case
1024 static void make_lowercase(char *s)
1030 if ((c >= 'A') && (c <= 'Z'))
1031 *p = c + ('a' - 'A');
1036 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1037 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1039 struct device_node *np = pdev->dev.of_node;
1043 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1044 if (IS_ERR(ssi_private->clk)) {
1045 ret = PTR_ERR(ssi_private->clk);
1046 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1050 ret = clk_prepare_enable(ssi_private->clk);
1052 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1056 /* For those SLAVE implementations, we ingore non-baudclk cases
1057 * and, instead, abandon MASTER mode that needs baud clock.
1059 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1060 if (IS_ERR(ssi_private->baudclk))
1061 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1062 PTR_ERR(ssi_private->baudclk));
1064 clk_prepare_enable(ssi_private->baudclk);
1067 * We have burstsize be "fifo_depth - 2" to match the SSI
1068 * watermark setting in fsl_ssi_startup().
1070 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1071 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1072 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys +
1073 offsetof(struct ccsr_ssi, stx0);
1074 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys +
1075 offsetof(struct ccsr_ssi, srx0);
1077 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1078 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1079 ssi_private->use_dual_fifo = true;
1080 /* When using dual fifo mode, we need to keep watermark
1081 * as even numbers due to dma script limitation.
1083 ssi_private->dma_params_tx.maxburst &= ~0x1;
1084 ssi_private->dma_params_rx.maxburst &= ~0x1;
1087 if (!ssi_private->use_dma) {
1090 * Some boards use an incompatible codec. To get it
1091 * working, we are using imx-fiq-pcm-audio, that
1092 * can handle those codecs. DMA is not possible in this
1096 ssi_private->fiq_params.irq = ssi_private->irq;
1097 ssi_private->fiq_params.base = iomem;
1098 ssi_private->fiq_params.dma_params_rx =
1099 &ssi_private->dma_params_rx;
1100 ssi_private->fiq_params.dma_params_tx =
1101 &ssi_private->dma_params_tx;
1103 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1107 ret = imx_pcm_dma_init(pdev);
1115 if (!IS_ERR(ssi_private->baudclk))
1116 clk_disable_unprepare(ssi_private->baudclk);
1118 clk_disable_unprepare(ssi_private->clk);
1123 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1124 struct fsl_ssi_private *ssi_private)
1126 if (!ssi_private->use_dma)
1127 imx_pcm_fiq_exit(pdev);
1128 if (!IS_ERR(ssi_private->baudclk))
1129 clk_disable_unprepare(ssi_private->baudclk);
1130 clk_disable_unprepare(ssi_private->clk);
1133 static int fsl_ssi_probe(struct platform_device *pdev)
1135 struct fsl_ssi_private *ssi_private;
1137 struct device_node *np = pdev->dev.of_node;
1138 const struct of_device_id *of_id;
1139 enum fsl_ssi_type hw_type;
1140 const char *p, *sprop;
1141 const uint32_t *iprop;
1142 struct resource res;
1146 /* SSIs that are not connected on the board should have a
1147 * status = "disabled"
1148 * property in their device tree nodes.
1150 if (!of_device_is_available(np))
1153 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1156 hw_type = (enum fsl_ssi_type) of_id->data;
1158 sprop = of_get_property(np, "fsl,mode", NULL);
1160 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1163 if (!strcmp(sprop, "ac97-slave"))
1166 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1169 dev_err(&pdev->dev, "could not allocate DAI object\n");
1173 ssi_private->use_dma = !of_property_read_bool(np,
1174 "fsl,fiq-stream-filter");
1175 ssi_private->hw_type = hw_type;
1178 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1179 sizeof(fsl_ssi_ac97_dai));
1181 fsl_ac97_data = ssi_private;
1183 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1185 /* Initialize this copy of the CPU DAI driver structure */
1186 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1187 sizeof(fsl_ssi_dai_template));
1189 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1191 /* Get the addresses and IRQ */
1192 ret = of_address_to_resource(np, 0, &res);
1194 dev_err(&pdev->dev, "could not determine device resources\n");
1197 ssi_private->ssi = of_iomap(np, 0);
1198 if (!ssi_private->ssi) {
1199 dev_err(&pdev->dev, "could not map device resources\n");
1202 ssi_private->ssi_phys = res.start;
1204 ssi_private->irq = irq_of_parse_and_map(np, 0);
1205 if (!ssi_private->irq) {
1206 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1210 /* Are the RX and the TX clocks locked? */
1211 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1212 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1213 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1214 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1217 /* Determine the FIFO depth. */
1218 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1220 ssi_private->fifo_depth = be32_to_cpup(iprop);
1222 /* Older 8610 DTs didn't have the fifo-depth property */
1223 ssi_private->fifo_depth = 8;
1225 ssi_private->baudclk_locked = false;
1226 spin_lock_init(&ssi_private->baudclk_lock);
1228 dev_set_drvdata(&pdev->dev, ssi_private);
1230 if (fsl_ssi_on_imx(ssi_private)) {
1231 ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi);
1236 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1237 &ssi_private->cpu_dai_drv, 1);
1239 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1240 goto error_asoc_register;
1243 if (ssi_private->use_dma) {
1244 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1245 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1248 dev_err(&pdev->dev, "could not claim irq %u\n",
1254 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1256 goto error_asoc_register;
1259 * If codec-handle property is missing from SSI node, we assume
1260 * that the machine driver uses new binding which does not require
1261 * SSI driver to trigger machine driver's probe.
1263 if (!of_get_property(np, "codec-handle", NULL))
1266 /* Trigger the machine driver's probe function. The platform driver
1267 * name of the machine driver is taken from /compatible property of the
1268 * device tree. We also pass the address of the CPU DAI driver
1271 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1272 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1273 p = strrchr(sprop, ',');
1276 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1277 make_lowercase(name);
1280 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1281 if (IS_ERR(ssi_private->pdev)) {
1282 ret = PTR_ERR(ssi_private->pdev);
1283 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1284 goto error_sound_card;
1291 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1294 snd_soc_unregister_component(&pdev->dev);
1296 error_asoc_register:
1297 if (fsl_ssi_on_imx(ssi_private))
1298 fsl_ssi_imx_clean(pdev, ssi_private);
1301 if (ssi_private->use_dma)
1302 irq_dispose_mapping(ssi_private->irq);
1307 static int fsl_ssi_remove(struct platform_device *pdev)
1309 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1311 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1313 if (ssi_private->pdev)
1314 platform_device_unregister(ssi_private->pdev);
1315 snd_soc_unregister_component(&pdev->dev);
1317 if (fsl_ssi_on_imx(ssi_private))
1318 fsl_ssi_imx_clean(pdev, ssi_private);
1320 if (ssi_private->use_dma)
1321 irq_dispose_mapping(ssi_private->irq);
1326 static struct platform_driver fsl_ssi_driver = {
1328 .name = "fsl-ssi-dai",
1329 .owner = THIS_MODULE,
1330 .of_match_table = fsl_ssi_ids,
1332 .probe = fsl_ssi_probe,
1333 .remove = fsl_ssi_remove,
1336 module_platform_driver(fsl_ssi_driver);
1338 MODULE_ALIAS("platform:fsl-ssi-dai");
1339 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1340 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1341 MODULE_LICENSE("GPL v2");