2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/of_address.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_platform.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/initval.h>
49 #include <sound/soc.h>
50 #include <sound/dmaengine_pcm.h>
56 #define read_ssi(addr) in_be32(addr)
57 #define write_ssi(val, addr) out_be32(addr, val)
58 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
60 #define read_ssi(addr) readl(addr)
61 #define write_ssi(val, addr) writel(val, addr)
63 * FIXME: Proper locking should be added at write_ssi_mask caller level
64 * to ensure this register read/modify/write sequence is race free.
66 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
75 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * This driver currently only supports the SSI running in I2S slave mode,
78 * which means the codec determines the sample rate. Therefore, we tell
79 * ALSA that we support all rates and let the codec driver decide what rates
80 * are really supported.
82 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 /* SIER bitflag of interrupts to enable */
110 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
117 * fsl_ssi_private: per-SSI private data
119 * @ssi: pointer to the SSI's registers
120 * @ssi_phys: physical address of the SSI registers
121 * @irq: IRQ of this SSI
122 * @first_stream: pointer to the stream that was opened first
123 * @second_stream: pointer to second stream
124 * @playback: the number of playback streams opened
125 * @capture: the number of capture streams opened
126 * @cpu_dai: the CPU DAI for this device
127 * @dev_attr: the sysfs device attribute structure
128 * @stats: SSI statistics
129 * @name: name for this device
131 struct fsl_ssi_private {
132 struct ccsr_ssi __iomem *ssi;
135 struct snd_pcm_substream *first_stream;
136 struct snd_pcm_substream *second_stream;
137 unsigned int fifo_depth;
138 struct snd_soc_dai_driver cpu_dai_drv;
139 struct device_attribute dev_attr;
140 struct platform_device *pdev;
148 struct snd_dmaengine_dai_dma_data dma_params_tx;
149 struct snd_dmaengine_dai_dma_data dma_params_rx;
150 struct imx_dma_data filter_data_tx;
151 struct imx_dma_data filter_data_rx;
152 struct imx_pcm_fiq_params fiq_params;
182 * fsl_ssi_isr: SSI interrupt handler
184 * Although it's possible to use the interrupt handler to send and receive
185 * data to/from the SSI, we use the DMA instead. Programming is more
186 * complicated, but the performance is much better.
188 * This interrupt handler is used only to gather statistics.
190 * @irq: IRQ of the SSI device
191 * @dev_id: pointer to the ssi_private structure for this SSI device
193 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
195 struct fsl_ssi_private *ssi_private = dev_id;
196 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
197 irqreturn_t ret = IRQ_NONE;
201 /* We got an interrupt, so read the status register to see what we
202 were interrupted for. We mask it with the Interrupt Enable register
203 so that we only check for events that we're interested in.
205 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
207 if (sisr & CCSR_SSI_SISR_RFRC) {
208 ssi_private->stats.rfrc++;
209 sisr2 |= CCSR_SSI_SISR_RFRC;
213 if (sisr & CCSR_SSI_SISR_TFRC) {
214 ssi_private->stats.tfrc++;
215 sisr2 |= CCSR_SSI_SISR_TFRC;
219 if (sisr & CCSR_SSI_SISR_CMDAU) {
220 ssi_private->stats.cmdau++;
224 if (sisr & CCSR_SSI_SISR_CMDDU) {
225 ssi_private->stats.cmddu++;
229 if (sisr & CCSR_SSI_SISR_RXT) {
230 ssi_private->stats.rxt++;
234 if (sisr & CCSR_SSI_SISR_RDR1) {
235 ssi_private->stats.rdr1++;
239 if (sisr & CCSR_SSI_SISR_RDR0) {
240 ssi_private->stats.rdr0++;
244 if (sisr & CCSR_SSI_SISR_TDE1) {
245 ssi_private->stats.tde1++;
249 if (sisr & CCSR_SSI_SISR_TDE0) {
250 ssi_private->stats.tde0++;
254 if (sisr & CCSR_SSI_SISR_ROE1) {
255 ssi_private->stats.roe1++;
256 sisr2 |= CCSR_SSI_SISR_ROE1;
260 if (sisr & CCSR_SSI_SISR_ROE0) {
261 ssi_private->stats.roe0++;
262 sisr2 |= CCSR_SSI_SISR_ROE0;
266 if (sisr & CCSR_SSI_SISR_TUE1) {
267 ssi_private->stats.tue1++;
268 sisr2 |= CCSR_SSI_SISR_TUE1;
272 if (sisr & CCSR_SSI_SISR_TUE0) {
273 ssi_private->stats.tue0++;
274 sisr2 |= CCSR_SSI_SISR_TUE0;
278 if (sisr & CCSR_SSI_SISR_TFS) {
279 ssi_private->stats.tfs++;
283 if (sisr & CCSR_SSI_SISR_RFS) {
284 ssi_private->stats.rfs++;
288 if (sisr & CCSR_SSI_SISR_TLS) {
289 ssi_private->stats.tls++;
293 if (sisr & CCSR_SSI_SISR_RLS) {
294 ssi_private->stats.rls++;
298 if (sisr & CCSR_SSI_SISR_RFF1) {
299 ssi_private->stats.rff1++;
303 if (sisr & CCSR_SSI_SISR_RFF0) {
304 ssi_private->stats.rff0++;
308 if (sisr & CCSR_SSI_SISR_TFE1) {
309 ssi_private->stats.tfe1++;
313 if (sisr & CCSR_SSI_SISR_TFE0) {
314 ssi_private->stats.tfe0++;
318 /* Clear the bits that we set */
320 write_ssi(sisr2, &ssi->sisr);
325 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
327 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
330 * Setup the clock control register
332 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
334 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
338 * Enable AC97 mode and startup the SSI
340 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
342 write_ssi(0xff, &ssi->saccdis);
343 write_ssi(0x300, &ssi->saccen);
346 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
347 * codec before a stream is started.
349 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
350 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
352 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
355 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
357 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
359 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
361 if (ssi_private->imx_ac97)
362 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
364 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
367 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
368 * to be disabled before updating the registers we set here.
370 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
373 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
374 * enable the transmit and receive FIFO.
376 * FIXME: Little-endian samples require a different shift dir
378 write_ssi_mask(&ssi->scr,
379 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
380 CCSR_SSI_SCR_TFR_CLK_DIS |
381 ssi_private->i2s_mode |
382 (synchronous ? CCSR_SSI_SCR_SYN : 0));
384 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
385 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
386 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
388 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
389 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
390 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
392 * The DC and PM bits are only used if the SSI is the clock master.
396 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
397 * use FIFO 1. We program the transmit water to signal a DMA transfer
398 * if there are only two (or fewer) elements left in the FIFO. Two
399 * elements equals one frame (left channel, right channel). This value,
400 * however, depends on the depth of the transmit buffer.
402 * We set the watermark on the same level as the DMA burstsize. For
403 * fiq it is probably better to use the biggest possible watermark
406 if (ssi_private->use_dma)
407 wm = ssi_private->fifo_depth - 2;
409 wm = ssi_private->fifo_depth;
411 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
412 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
416 * For ac97 interrupts are enabled with the startup of the substream
417 * because it is also running without an active substream. Normally SSI
418 * is only enabled when there is a substream.
420 if (ssi_private->imx_ac97)
421 fsl_ssi_setup_ac97(ssi_private);
428 * fsl_ssi_startup: create a new substream
430 * This is the first function called when a stream is opened.
432 * If this is the first stream open, then grab the IRQ and program most of
435 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
436 struct snd_soc_dai *dai)
438 struct snd_soc_pcm_runtime *rtd = substream->private_data;
439 struct fsl_ssi_private *ssi_private =
440 snd_soc_dai_get_drvdata(rtd->cpu_dai);
441 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
444 * If this is the first stream opened, then request the IRQ
445 * and initialize the SSI registers.
447 if (!ssi_private->first_stream) {
448 ssi_private->first_stream = substream;
451 * fsl_ssi_setup was already called by ac97_init earlier if
452 * the driver is in ac97 mode.
454 if (!ssi_private->imx_ac97)
455 fsl_ssi_setup(ssi_private);
458 struct snd_pcm_runtime *first_runtime =
459 ssi_private->first_stream->runtime;
461 * This is the second stream open, and we're in
462 * synchronous mode, so we need to impose sample
463 * sample size constraints. This is because STCCR is
464 * used for playback and capture in synchronous mode,
465 * so there's no way to specify different word
468 * Note that this can cause a race condition if the
469 * second stream is opened before the first stream is
470 * fully initialized. We provide some protection by
471 * checking to make sure the first stream is
472 * initialized, but it's not perfect. ALSA sometimes
473 * re-initializes the driver with a different sample
474 * rate or size. If the second stream is opened
475 * before the first stream has received its final
476 * parameters, then the second stream may be
477 * constrained to the wrong sample rate or size.
479 if (first_runtime->sample_bits) {
480 snd_pcm_hw_constraint_minmax(substream->runtime,
481 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
482 first_runtime->sample_bits,
483 first_runtime->sample_bits);
487 ssi_private->second_stream = substream;
494 * fsl_ssi_hw_params - program the sample size
496 * Most of the SSI registers have been programmed in the startup function,
497 * but the word length must be programmed here. Unfortunately, programming
498 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
499 * cause a problem with supporting simultaneous playback and capture. If
500 * the SSI is already playing a stream, then that stream may be temporarily
501 * stopped when you start capture.
503 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
506 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
507 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
509 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
510 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
511 unsigned int channels = params_channels(hw_params);
512 unsigned int sample_size =
513 snd_pcm_format_width(params_format(hw_params));
514 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
515 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
518 * If we're in synchronous mode, and the SSI is already enabled,
519 * then STCCR is already set properly.
521 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
525 * FIXME: The documentation says that SxCCR[WL] should not be
526 * modified while the SSI is enabled. The only time this can
527 * happen is if we're trying to do simultaneous playback and
528 * capture in asynchronous mode. Unfortunately, I have been enable
529 * to get that to work at all on the P1022DS. Therefore, we don't
530 * bother to disable/enable the SSI when setting SxCCR[WL], because
531 * the SSI will stop anyway. Maybe one day, this will get fixed.
534 /* In synchronous mode, the SSI uses STCCR for capture */
535 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
536 ssi_private->cpu_dai_drv.symmetric_rates)
537 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
539 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
541 if (!ssi_private->imx_ac97)
542 write_ssi_mask(&ssi->scr,
543 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
544 channels == 1 ? 0 : ssi_private->i2s_mode);
550 * fsl_ssi_trigger: start and stop the DMA transfer.
552 * This function is called by ALSA to start, stop, pause, and resume the DMA
555 * The DMA channel is in external master start and pause mode, which
556 * means the SSI completely controls the flow of data.
558 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
559 struct snd_soc_dai *dai)
561 struct snd_soc_pcm_runtime *rtd = substream->private_data;
562 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
563 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
564 unsigned int sier_bits;
567 * Enable only the interrupts and DMA requests
568 * that are needed for the channel. As the fiq
569 * is polling for this bits, we have to ensure
570 * that this are aligned with the preallocated
574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
575 if (ssi_private->use_dma)
576 sier_bits = SIER_FLAGS;
578 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
580 if (ssi_private->use_dma)
581 sier_bits = SIER_FLAGS;
583 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
587 case SNDRV_PCM_TRIGGER_START:
588 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
589 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
590 write_ssi_mask(&ssi->scr, 0,
591 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
593 write_ssi_mask(&ssi->scr, 0,
594 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
597 case SNDRV_PCM_TRIGGER_STOP:
598 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
599 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
600 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
602 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
604 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
605 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
606 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
613 write_ssi(sier_bits, &ssi->sier);
619 * fsl_ssi_shutdown: shutdown the SSI
621 * Shutdown the SSI if there are no other substreams open.
623 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
624 struct snd_soc_dai *dai)
626 struct snd_soc_pcm_runtime *rtd = substream->private_data;
627 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
629 if (ssi_private->first_stream == substream)
630 ssi_private->first_stream = ssi_private->second_stream;
632 ssi_private->second_stream = NULL;
635 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
637 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
639 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
640 dai->playback_dma_data = &ssi_private->dma_params_tx;
641 dai->capture_dma_data = &ssi_private->dma_params_rx;
647 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
648 .startup = fsl_ssi_startup,
649 .hw_params = fsl_ssi_hw_params,
650 .shutdown = fsl_ssi_shutdown,
651 .trigger = fsl_ssi_trigger,
654 /* Template for the CPU dai driver structure */
655 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
656 .probe = fsl_ssi_dai_probe,
660 .rates = FSLSSI_I2S_RATES,
661 .formats = FSLSSI_I2S_FORMATS,
666 .rates = FSLSSI_I2S_RATES,
667 .formats = FSLSSI_I2S_FORMATS,
669 .ops = &fsl_ssi_dai_ops,
672 static const struct snd_soc_component_driver fsl_ssi_component = {
677 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
679 * This function is called by ALSA to start, stop, pause, and resume the
682 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
683 struct snd_soc_dai *dai)
685 struct snd_soc_pcm_runtime *rtd = substream->private_data;
686 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
688 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
691 case SNDRV_PCM_TRIGGER_START:
692 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
693 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
694 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
695 CCSR_SSI_SIER_TFE0_EN);
697 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
698 CCSR_SSI_SIER_RFF0_EN);
701 case SNDRV_PCM_TRIGGER_STOP:
702 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
703 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
704 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
705 CCSR_SSI_SIER_TFE0_EN, 0);
707 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
708 CCSR_SSI_SIER_RFF0_EN, 0);
715 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
716 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
718 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
723 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
724 .startup = fsl_ssi_startup,
725 .shutdown = fsl_ssi_shutdown,
726 .trigger = fsl_ssi_ac97_trigger,
729 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
732 .stream_name = "AC97 Playback",
735 .rates = SNDRV_PCM_RATE_8000_48000,
736 .formats = SNDRV_PCM_FMTBIT_S16_LE,
739 .stream_name = "AC97 Capture",
742 .rates = SNDRV_PCM_RATE_48000,
743 .formats = SNDRV_PCM_FMTBIT_S16_LE,
745 .ops = &fsl_ssi_ac97_dai_ops,
749 static struct fsl_ssi_private *fsl_ac97_data;
751 static void fsl_ssi_ac97_init(void)
753 fsl_ssi_setup(fsl_ac97_data);
756 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
759 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
768 write_ssi(lreg, &ssi->sacadd);
771 write_ssi(lval , &ssi->sacdat);
773 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
778 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
781 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
783 unsigned short val = -1;
786 lreg = (reg & 0x7f) << 12;
787 write_ssi(lreg, &ssi->sacadd);
788 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
793 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
798 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
799 .read = fsl_ssi_ac97_read,
800 .write = fsl_ssi_ac97_write,
803 /* Show the statistics of a flag only if its interrupt is enabled. The
804 * compiler will optimze this code to a no-op if the interrupt is not
807 #define SIER_SHOW(flag, name) \
809 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
810 length += sprintf(buf + length, #name "=%u\n", \
811 ssi_private->stats.name); \
816 * fsl_sysfs_ssi_show: display SSI statistics
818 * Display the statistics for the current SSI device. To avoid confusion,
819 * we only show those counts that are enabled.
821 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
822 struct device_attribute *attr, char *buf)
824 struct fsl_ssi_private *ssi_private =
825 container_of(attr, struct fsl_ssi_private, dev_attr);
828 SIER_SHOW(RFRC_EN, rfrc);
829 SIER_SHOW(TFRC_EN, tfrc);
830 SIER_SHOW(CMDAU_EN, cmdau);
831 SIER_SHOW(CMDDU_EN, cmddu);
832 SIER_SHOW(RXT_EN, rxt);
833 SIER_SHOW(RDR1_EN, rdr1);
834 SIER_SHOW(RDR0_EN, rdr0);
835 SIER_SHOW(TDE1_EN, tde1);
836 SIER_SHOW(TDE0_EN, tde0);
837 SIER_SHOW(ROE1_EN, roe1);
838 SIER_SHOW(ROE0_EN, roe0);
839 SIER_SHOW(TUE1_EN, tue1);
840 SIER_SHOW(TUE0_EN, tue0);
841 SIER_SHOW(TFS_EN, tfs);
842 SIER_SHOW(RFS_EN, rfs);
843 SIER_SHOW(TLS_EN, tls);
844 SIER_SHOW(RLS_EN, rls);
845 SIER_SHOW(RFF1_EN, rff1);
846 SIER_SHOW(RFF0_EN, rff0);
847 SIER_SHOW(TFE1_EN, tfe1);
848 SIER_SHOW(TFE0_EN, tfe0);
854 * Make every character in a string lower-case
856 static void make_lowercase(char *s)
862 if ((c >= 'A') && (c <= 'Z'))
863 *p = c + ('a' - 'A');
868 static int fsl_ssi_probe(struct platform_device *pdev)
870 struct fsl_ssi_private *ssi_private;
872 struct device_attribute *dev_attr = NULL;
873 struct device_node *np = pdev->dev.of_node;
874 const char *p, *sprop;
875 const uint32_t *iprop;
881 /* SSIs that are not connected on the board should have a
882 * status = "disabled"
883 * property in their device tree nodes.
885 if (!of_device_is_available(np))
888 /* We only support the SSI in "I2S Slave" mode */
889 sprop = of_get_property(np, "fsl,mode", NULL);
891 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
894 if (!strcmp(sprop, "ac97-slave")) {
896 } else if (strcmp(sprop, "i2s-slave")) {
897 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
901 /* The DAI name is the last part of the full name of the node. */
902 p = strrchr(np->full_name, '/') + 1;
903 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
906 dev_err(&pdev->dev, "could not allocate DAI object\n");
910 strcpy(ssi_private->name, p);
912 ssi_private->use_dma = !of_property_read_bool(np,
913 "fsl,fiq-stream-filter");
916 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
917 sizeof(fsl_ssi_ac97_dai));
919 fsl_ac97_data = ssi_private;
920 ssi_private->imx_ac97 = true;
922 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
924 /* Initialize this copy of the CPU DAI driver structure */
925 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
926 sizeof(fsl_ssi_dai_template));
928 ssi_private->cpu_dai_drv.name = ssi_private->name;
930 /* Get the addresses and IRQ */
931 ret = of_address_to_resource(np, 0, &res);
933 dev_err(&pdev->dev, "could not determine device resources\n");
936 ssi_private->ssi = of_iomap(np, 0);
937 if (!ssi_private->ssi) {
938 dev_err(&pdev->dev, "could not map device resources\n");
941 ssi_private->ssi_phys = res.start;
943 ssi_private->irq = irq_of_parse_and_map(np, 0);
944 if (!ssi_private->irq) {
945 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
949 /* Are the RX and the TX clocks locked? */
950 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
951 ssi_private->cpu_dai_drv.symmetric_rates = 1;
953 /* Determine the FIFO depth. */
954 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
956 ssi_private->fifo_depth = be32_to_cpup(iprop);
958 /* Older 8610 DTs didn't have the fifo-depth property */
959 ssi_private->fifo_depth = 8;
961 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
963 ssi_private->ssi_on_imx = true;
965 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
966 if (IS_ERR(ssi_private->clk)) {
967 ret = PTR_ERR(ssi_private->clk);
968 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
971 ret = clk_prepare_enable(ssi_private->clk);
973 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
979 * We have burstsize be "fifo_depth - 2" to match the SSI
980 * watermark setting in fsl_ssi_startup().
982 ssi_private->dma_params_tx.maxburst =
983 ssi_private->fifo_depth - 2;
984 ssi_private->dma_params_rx.maxburst =
985 ssi_private->fifo_depth - 2;
986 ssi_private->dma_params_tx.addr =
987 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
988 ssi_private->dma_params_rx.addr =
989 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
990 ssi_private->dma_params_tx.filter_data =
991 &ssi_private->filter_data_tx;
992 ssi_private->dma_params_rx.filter_data =
993 &ssi_private->filter_data_rx;
994 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
995 ssi_private->use_dma) {
997 * FIXME: This is a temporary solution until all
998 * necessary dma drivers support the generic dma
1001 ret = of_property_read_u32_array(pdev->dev.of_node,
1002 "fsl,ssi-dma-events", dma_events, 2);
1003 if (ret && ssi_private->use_dma) {
1004 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1009 shared = of_device_is_compatible(of_get_parent(np),
1012 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1013 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1014 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1015 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1016 } else if (ssi_private->use_dma) {
1017 /* The 'name' should not have any slashes in it. */
1018 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1019 fsl_ssi_isr, 0, ssi_private->name,
1022 dev_err(&pdev->dev, "could not claim irq %u\n",
1028 /* Initialize the the device_attribute structure */
1029 dev_attr = &ssi_private->dev_attr;
1030 sysfs_attr_init(&dev_attr->attr);
1031 dev_attr->attr.name = "statistics";
1032 dev_attr->attr.mode = S_IRUGO;
1033 dev_attr->show = fsl_sysfs_ssi_show;
1035 ret = device_create_file(&pdev->dev, dev_attr);
1037 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1038 ssi_private->dev_attr.attr.name);
1042 /* Register with ASoC */
1043 dev_set_drvdata(&pdev->dev, ssi_private);
1045 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1046 &ssi_private->cpu_dai_drv, 1);
1048 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1052 if (ssi_private->ssi_on_imx) {
1053 if (!ssi_private->use_dma) {
1056 * Some boards use an incompatible codec. To get it
1057 * working, we are using imx-fiq-pcm-audio, that
1058 * can handle those codecs. DMA is not possible in this
1062 ssi_private->fiq_params.irq = ssi_private->irq;
1063 ssi_private->fiq_params.base = ssi_private->ssi;
1064 ssi_private->fiq_params.dma_params_rx =
1065 &ssi_private->dma_params_rx;
1066 ssi_private->fiq_params.dma_params_tx =
1067 &ssi_private->dma_params_tx;
1069 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1073 ret = imx_pcm_dma_init(pdev);
1080 * If codec-handle property is missing from SSI node, we assume
1081 * that the machine driver uses new binding which does not require
1082 * SSI driver to trigger machine driver's probe.
1084 if (!of_get_property(np, "codec-handle", NULL)) {
1085 ssi_private->new_binding = true;
1089 /* Trigger the machine driver's probe function. The platform driver
1090 * name of the machine driver is taken from /compatible property of the
1091 * device tree. We also pass the address of the CPU DAI driver
1094 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1095 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1096 p = strrchr(sprop, ',');
1099 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1100 make_lowercase(name);
1103 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1104 if (IS_ERR(ssi_private->pdev)) {
1105 ret = PTR_ERR(ssi_private->pdev);
1106 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1111 if (ssi_private->imx_ac97)
1112 fsl_ssi_ac97_init();
1117 snd_soc_unregister_component(&pdev->dev);
1120 device_remove_file(&pdev->dev, dev_attr);
1123 if (ssi_private->ssi_on_imx)
1124 clk_disable_unprepare(ssi_private->clk);
1127 irq_dispose_mapping(ssi_private->irq);
1132 static int fsl_ssi_remove(struct platform_device *pdev)
1134 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1136 if (!ssi_private->new_binding)
1137 platform_device_unregister(ssi_private->pdev);
1138 snd_soc_unregister_component(&pdev->dev);
1139 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1140 if (ssi_private->ssi_on_imx)
1141 clk_disable_unprepare(ssi_private->clk);
1142 irq_dispose_mapping(ssi_private->irq);
1147 static const struct of_device_id fsl_ssi_ids[] = {
1148 { .compatible = "fsl,mpc8610-ssi", },
1149 { .compatible = "fsl,imx21-ssi", },
1152 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1154 static struct platform_driver fsl_ssi_driver = {
1156 .name = "fsl-ssi-dai",
1157 .owner = THIS_MODULE,
1158 .of_match_table = fsl_ssi_ids,
1160 .probe = fsl_ssi_probe,
1161 .remove = fsl_ssi_remove,
1164 module_platform_driver(fsl_ssi_driver);
1166 MODULE_ALIAS("platform:fsl-ssi-dai");
1167 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1168 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1169 MODULE_LICENSE("GPL v2");