2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
70 u32 val = readl(addr);
71 val = (val & ~clear) | set;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
89 * This driver currently only supports the SSI running in I2S slave mode.
91 * The SSI has a limitation in that the samples must be in the same byte
92 * order as the host CPU. This is because when multiple bytes are written
93 * to the STX register, the bytes and bits must be written in the same
94 * order. The STX is a shift register, so all the bits need to be aligned
95 * (bit-endianness must match byte-endianness). Processors typically write
96 * the bits within a byte in the same order that the bytes of a word are
97 * written in. So if the host CPU is big-endian, then only big-endian
98 * samples will be written to STX properly.
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
110 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
111 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
113 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
114 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
115 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
116 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
126 struct fsl_ssi_reg_val {
133 struct fsl_ssi_rxtx_reg_val {
134 struct fsl_ssi_reg_val rx;
135 struct fsl_ssi_reg_val tx;
139 * fsl_ssi_private: per-SSI private data
141 * @ssi: pointer to the SSI's registers
142 * @ssi_phys: physical address of the SSI registers
143 * @irq: IRQ of this SSI
144 * @playback: the number of playback streams opened
145 * @capture: the number of capture streams opened
146 * @cpu_dai: the CPU DAI for this device
147 * @dev_attr: the sysfs device attribute structure
148 * @stats: SSI statistics
149 * @name: name for this device
151 struct fsl_ssi_private {
152 struct ccsr_ssi __iomem *ssi;
155 unsigned int fifo_depth;
156 struct snd_soc_dai_driver cpu_dai_drv;
157 struct platform_device *pdev;
159 enum fsl_ssi_type hw_type;
169 spinlock_t baudclk_lock;
172 struct snd_dmaengine_dai_dma_data dma_params_tx;
173 struct snd_dmaengine_dai_dma_data dma_params_rx;
174 struct imx_dma_data filter_data_tx;
175 struct imx_dma_data filter_data_rx;
176 struct imx_pcm_fiq_params fiq_params;
177 /* Register values for rx/tx configuration */
178 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
203 struct dentry *dbg_dir;
204 struct dentry *dbg_stats;
209 static const struct of_device_id fsl_ssi_ids[] = {
210 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
211 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
212 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
213 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
216 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
219 * fsl_ssi_isr: SSI interrupt handler
221 * Although it's possible to use the interrupt handler to send and receive
222 * data to/from the SSI, we use the DMA instead. Programming is more
223 * complicated, but the performance is much better.
225 * This interrupt handler is used only to gather statistics.
227 * @irq: IRQ of the SSI device
228 * @dev_id: pointer to the ssi_private structure for this SSI device
230 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
232 struct fsl_ssi_private *ssi_private = dev_id;
233 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
234 irqreturn_t ret = IRQ_NONE;
237 __be32 sisr_write_mask = 0;
239 switch (ssi_private->hw_type) {
244 case FSL_SSI_MCP8610:
246 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
247 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
248 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
252 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
253 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
257 /* We got an interrupt, so read the status register to see what we
258 were interrupted for. We mask it with the Interrupt Enable register
259 so that we only check for events that we're interested in.
261 sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
263 if (sisr & CCSR_SSI_SISR_RFRC) {
264 ssi_private->stats.rfrc++;
268 if (sisr & CCSR_SSI_SISR_TFRC) {
269 ssi_private->stats.tfrc++;
273 if (sisr & CCSR_SSI_SISR_CMDAU) {
274 ssi_private->stats.cmdau++;
278 if (sisr & CCSR_SSI_SISR_CMDDU) {
279 ssi_private->stats.cmddu++;
283 if (sisr & CCSR_SSI_SISR_RXT) {
284 ssi_private->stats.rxt++;
288 if (sisr & CCSR_SSI_SISR_RDR1) {
289 ssi_private->stats.rdr1++;
293 if (sisr & CCSR_SSI_SISR_RDR0) {
294 ssi_private->stats.rdr0++;
298 if (sisr & CCSR_SSI_SISR_TDE1) {
299 ssi_private->stats.tde1++;
303 if (sisr & CCSR_SSI_SISR_TDE0) {
304 ssi_private->stats.tde0++;
308 if (sisr & CCSR_SSI_SISR_ROE1) {
309 ssi_private->stats.roe1++;
313 if (sisr & CCSR_SSI_SISR_ROE0) {
314 ssi_private->stats.roe0++;
318 if (sisr & CCSR_SSI_SISR_TUE1) {
319 ssi_private->stats.tue1++;
323 if (sisr & CCSR_SSI_SISR_TUE0) {
324 ssi_private->stats.tue0++;
328 if (sisr & CCSR_SSI_SISR_TFS) {
329 ssi_private->stats.tfs++;
333 if (sisr & CCSR_SSI_SISR_RFS) {
334 ssi_private->stats.rfs++;
338 if (sisr & CCSR_SSI_SISR_TLS) {
339 ssi_private->stats.tls++;
343 if (sisr & CCSR_SSI_SISR_RLS) {
344 ssi_private->stats.rls++;
348 if (sisr & CCSR_SSI_SISR_RFF1) {
349 ssi_private->stats.rff1++;
353 if (sisr & CCSR_SSI_SISR_RFF0) {
354 ssi_private->stats.rff0++;
358 if (sisr & CCSR_SSI_SISR_TFE1) {
359 ssi_private->stats.tfe1++;
363 if (sisr & CCSR_SSI_SISR_TFE0) {
364 ssi_private->stats.tfe0++;
368 sisr2 = sisr & sisr_write_mask;
369 /* Clear the bits that we set */
371 write_ssi(sisr2, &ssi->sisr);
376 #if IS_ENABLED(CONFIG_DEBUG_FS)
377 /* Show the statistics of a flag only if its interrupt is enabled. The
378 * compiler will optimze this code to a no-op if the interrupt is not
381 #define SIER_SHOW(flag, name) \
383 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
384 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
389 * fsl_sysfs_ssi_show: display SSI statistics
391 * Display the statistics for the current SSI device. To avoid confusion,
392 * we only show those counts that are enabled.
394 static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
396 struct fsl_ssi_private *ssi_private = s->private;
398 SIER_SHOW(RFRC_EN, rfrc);
399 SIER_SHOW(TFRC_EN, tfrc);
400 SIER_SHOW(CMDAU_EN, cmdau);
401 SIER_SHOW(CMDDU_EN, cmddu);
402 SIER_SHOW(RXT_EN, rxt);
403 SIER_SHOW(RDR1_EN, rdr1);
404 SIER_SHOW(RDR0_EN, rdr0);
405 SIER_SHOW(TDE1_EN, tde1);
406 SIER_SHOW(TDE0_EN, tde0);
407 SIER_SHOW(ROE1_EN, roe1);
408 SIER_SHOW(ROE0_EN, roe0);
409 SIER_SHOW(TUE1_EN, tue1);
410 SIER_SHOW(TUE0_EN, tue0);
411 SIER_SHOW(TFS_EN, tfs);
412 SIER_SHOW(RFS_EN, rfs);
413 SIER_SHOW(TLS_EN, tls);
414 SIER_SHOW(RLS_EN, rls);
415 SIER_SHOW(RFF1_EN, rff1);
416 SIER_SHOW(RFF0_EN, rff0);
417 SIER_SHOW(TFE1_EN, tfe1);
418 SIER_SHOW(TFE0_EN, tfe0);
423 static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
425 return single_open(file, fsl_ssi_stats_show, inode->i_private);
428 static const struct file_operations fsl_ssi_stats_ops = {
429 .open = fsl_ssi_stats_open,
432 .release = single_release,
435 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
438 ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
439 if (!ssi_private->dbg_dir)
442 ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
443 ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
444 if (!ssi_private->dbg_stats) {
445 debugfs_remove(ssi_private->dbg_dir);
452 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
454 debugfs_remove(ssi_private->dbg_stats);
455 debugfs_remove(ssi_private->dbg_dir);
460 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
466 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
470 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
473 * Enable/Disable all rx/tx config flags at once.
475 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
478 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
479 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
482 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
483 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
484 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
486 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
487 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
488 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
493 * Enable/Disable a ssi configuration. You have to pass either
494 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
496 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
497 struct fsl_ssi_reg_val *vals)
499 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
500 struct fsl_ssi_reg_val *avals;
501 u32 scr_val = read_ssi(&ssi->scr);
502 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
503 !!(scr_val & CCSR_SSI_SCR_RE);
505 /* Find the other direction values rx or tx which we do not want to
507 if (&ssi_private->rxtx_reg_val.rx == vals)
508 avals = &ssi_private->rxtx_reg_val.tx;
510 avals = &ssi_private->rxtx_reg_val.rx;
512 /* If vals should be disabled, start with disabling the unit */
514 u32 scr = vals->scr & (vals->scr ^ avals->scr);
515 write_ssi_mask(&ssi->scr, scr, 0);
519 * We are running on a SoC which does not support online SSI
520 * reconfiguration, so we have to enable all necessary flags at once
521 * even if we do not use them later (capture and playback configuration)
523 if (ssi_private->offline_config) {
524 if ((enable && !nr_active_streams) ||
525 (!enable && nr_active_streams == 1))
526 fsl_ssi_rxtx_config(ssi_private, enable);
532 * Configure single direction units while the SSI unit is running
533 * (online configuration)
536 write_ssi_mask(&ssi->sier, 0, vals->sier);
537 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
538 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
545 * Disabling the necessary flags for one of rx/tx while the
546 * other stream is active is a little bit more difficult. We
547 * have to disable only those flags that differ between both
548 * streams (rx XOR tx) and that are set in the stream that is
549 * disabled now. Otherwise we could alter flags of the other
553 /* These assignments are simply vals without bits set in avals*/
554 sier = vals->sier & (vals->sier ^ avals->sier);
555 srcr = vals->srcr & (vals->srcr ^ avals->srcr);
556 stcr = vals->stcr & (vals->stcr ^ avals->stcr);
558 write_ssi_mask(&ssi->srcr, srcr, 0);
559 write_ssi_mask(&ssi->stcr, stcr, 0);
560 write_ssi_mask(&ssi->sier, sier, 0);
564 /* Enabling of subunits is done after configuration */
566 write_ssi_mask(&ssi->scr, 0, vals->scr);
570 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
572 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
575 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
577 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
581 * Setup rx/tx register values used to enable/disable the streams. These will
582 * be used later in fsl_ssi_config to setup the streams without the need to
583 * check for all different SSI modes.
585 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
587 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
589 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
590 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
592 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
593 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
596 if (!ssi_private->imx_ac97) {
597 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
598 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
599 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
600 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
603 if (ssi_private->use_dma) {
604 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
605 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
607 reg->rx.sier |= CCSR_SSI_SIER_RIE;
608 reg->tx.sier |= CCSR_SSI_SIER_TIE;
611 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
612 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
615 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
617 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
620 * Setup the clock control register
622 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
624 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
628 * Enable AC97 mode and startup the SSI
630 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
632 write_ssi(0xff, &ssi->saccdis);
633 write_ssi(0x300, &ssi->saccen);
636 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
637 * codec before a stream is started.
639 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
640 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
642 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
646 * fsl_ssi_startup: create a new substream
648 * This is the first function called when a stream is opened.
650 * If this is the first stream open, then grab the IRQ and program most of
653 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
654 struct snd_soc_dai *dai)
656 struct snd_soc_pcm_runtime *rtd = substream->private_data;
657 struct fsl_ssi_private *ssi_private =
658 snd_soc_dai_get_drvdata(rtd->cpu_dai);
661 if (!dai->active && !ssi_private->imx_ac97) {
662 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
663 ssi_private->baudclk_locked = false;
664 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
667 /* When using dual fifo mode, it is safer to ensure an even period
668 * size. If appearing to an odd number while DMA always starts its
669 * task from fifo0, fifo1 would be neglected at the end of each
670 * period. But SSI would still access fifo1 with an invalid data.
672 if (ssi_private->use_dual_fifo)
673 snd_pcm_hw_constraint_step(substream->runtime, 0,
674 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
680 * fsl_ssi_hw_params - program the sample size
682 * Most of the SSI registers have been programmed in the startup function,
683 * but the word length must be programmed here. Unfortunately, programming
684 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
685 * cause a problem with supporting simultaneous playback and capture. If
686 * the SSI is already playing a stream, then that stream may be temporarily
687 * stopped when you start capture.
689 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
692 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
693 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
695 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
696 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
697 unsigned int channels = params_channels(hw_params);
698 unsigned int sample_size =
699 snd_pcm_format_width(params_format(hw_params));
700 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
701 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
704 * If we're in synchronous mode, and the SSI is already enabled,
705 * then STCCR is already set properly.
707 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
711 * FIXME: The documentation says that SxCCR[WL] should not be
712 * modified while the SSI is enabled. The only time this can
713 * happen is if we're trying to do simultaneous playback and
714 * capture in asynchronous mode. Unfortunately, I have been enable
715 * to get that to work at all on the P1022DS. Therefore, we don't
716 * bother to disable/enable the SSI when setting SxCCR[WL], because
717 * the SSI will stop anyway. Maybe one day, this will get fixed.
720 /* In synchronous mode, the SSI uses STCCR for capture */
721 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
722 ssi_private->cpu_dai_drv.symmetric_rates)
723 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
725 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
727 if (!ssi_private->imx_ac97)
728 write_ssi_mask(&ssi->scr,
729 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
730 channels == 1 ? 0 : ssi_private->i2s_mode);
736 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
738 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
740 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
741 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
742 u32 strcr = 0, stcr, srcr, scr, mask;
745 fsl_ssi_setup_reg_vals(ssi_private);
747 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
749 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
750 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
752 stcr = read_ssi(&ssi->stcr) & ~mask;
753 srcr = read_ssi(&ssi->srcr) & ~mask;
755 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
756 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
757 case SND_SOC_DAIFMT_I2S:
758 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
759 case SND_SOC_DAIFMT_CBS_CFS:
760 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
762 case SND_SOC_DAIFMT_CBM_CFM:
763 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
769 /* Data on rising edge of bclk, frame low, 1clk before data */
770 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
771 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
773 case SND_SOC_DAIFMT_LEFT_J:
774 /* Data on rising edge of bclk, frame high */
775 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
777 case SND_SOC_DAIFMT_DSP_A:
778 /* Data on rising edge of bclk, frame high, 1clk before data */
779 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
780 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
782 case SND_SOC_DAIFMT_DSP_B:
783 /* Data on rising edge of bclk, frame high */
784 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
785 CCSR_SSI_STCR_TXBIT0;
787 case SND_SOC_DAIFMT_AC97:
788 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
793 scr |= ssi_private->i2s_mode;
795 /* DAI clock inversion */
796 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
797 case SND_SOC_DAIFMT_NB_NF:
798 /* Nothing to do for both normal cases */
800 case SND_SOC_DAIFMT_IB_NF:
801 /* Invert bit clock */
802 strcr ^= CCSR_SSI_STCR_TSCKP;
804 case SND_SOC_DAIFMT_NB_IF:
805 /* Invert frame clock */
806 strcr ^= CCSR_SSI_STCR_TFSI;
808 case SND_SOC_DAIFMT_IB_IF:
809 /* Invert both clocks */
810 strcr ^= CCSR_SSI_STCR_TSCKP;
811 strcr ^= CCSR_SSI_STCR_TFSI;
817 /* DAI clock master masks */
818 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
819 case SND_SOC_DAIFMT_CBS_CFS:
820 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
821 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
823 case SND_SOC_DAIFMT_CBM_CFM:
824 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
833 if (ssi_private->cpu_dai_drv.symmetric_rates) {
834 /* Need to clear RXDIR when using SYNC mode */
835 srcr &= ~CCSR_SSI_SRCR_RXDIR;
836 scr |= CCSR_SSI_SCR_SYN;
839 write_ssi(stcr, &ssi->stcr);
840 write_ssi(srcr, &ssi->srcr);
841 write_ssi(scr, &ssi->scr);
844 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
845 * use FIFO 1. We program the transmit water to signal a DMA transfer
846 * if there are only two (or fewer) elements left in the FIFO. Two
847 * elements equals one frame (left channel, right channel). This value,
848 * however, depends on the depth of the transmit buffer.
850 * We set the watermark on the same level as the DMA burstsize. For
851 * fiq it is probably better to use the biggest possible watermark
854 if (ssi_private->use_dma)
855 wm = ssi_private->fifo_depth - 2;
857 wm = ssi_private->fifo_depth;
859 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
860 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
863 if (ssi_private->use_dual_fifo) {
864 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
865 CCSR_SSI_SRCR_RFEN1);
866 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
867 CCSR_SSI_STCR_TFEN1);
868 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
869 CCSR_SSI_SCR_TCH_EN);
872 if (fmt & SND_SOC_DAIFMT_AC97)
873 fsl_ssi_setup_ac97(ssi_private);
879 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
881 * Note: This function can be only called when using SSI as DAI master
883 * Quick instruction for parameters:
884 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
885 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
887 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
888 int clk_id, unsigned int freq, int dir)
890 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
891 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
892 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
893 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
894 unsigned long flags, clkrate, baudrate, tmprate;
895 u64 sub, savesub = 100000;
897 /* Don't apply it to any non-baudclk circumstance */
898 if (IS_ERR(ssi_private->baudclk))
901 /* It should be already enough to divide clock by setting pm alone */
905 factor = (div2 + 1) * (7 * psr + 1) * 2;
907 for (i = 0; i < 255; i++) {
908 /* The bclk rate must be smaller than 1/5 sysclk rate */
909 if (factor * (i + 1) < 5)
912 tmprate = freq * factor * (i + 2);
913 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
915 do_div(clkrate, factor);
916 afreq = (u32)clkrate / (i + 1);
920 else if (freq / afreq == 1)
922 else if (afreq / freq == 1)
927 /* Calculate the fraction */
942 /* No proper pm found if it is still remaining the initial value */
944 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
948 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
949 (psr ? CCSR_SSI_SxCCR_PSR : 0);
950 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
952 if (dir == SND_SOC_CLOCK_OUT || synchronous)
953 write_ssi_mask(&ssi->stccr, mask, stccr);
955 write_ssi_mask(&ssi->srccr, mask, stccr);
957 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
958 if (!ssi_private->baudclk_locked) {
959 ret = clk_set_rate(ssi_private->baudclk, baudrate);
961 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
962 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
965 ssi_private->baudclk_locked = true;
967 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
973 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
975 * Note: This function can be only called when using SSI as DAI master
977 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
978 u32 rx_mask, int slots, int slot_width)
980 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
981 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
984 /* The slot number should be >= 2 if using Network mode or I2S mode */
985 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
986 if (val && slots < 2) {
987 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
991 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
992 CCSR_SSI_SxCCR_DC(slots));
993 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
994 CCSR_SSI_SxCCR_DC(slots));
996 /* The register SxMSKs needs SSI to provide essential clock due to
997 * hardware design. So we here temporarily enable SSI to set them.
999 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
1000 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
1002 write_ssi(tx_mask, &ssi->stmsk);
1003 write_ssi(rx_mask, &ssi->srmsk);
1005 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
1011 * fsl_ssi_trigger: start and stop the DMA transfer.
1013 * This function is called by ALSA to start, stop, pause, and resume the DMA
1016 * The DMA channel is in external master start and pause mode, which
1017 * means the SSI completely controls the flow of data.
1019 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1020 struct snd_soc_dai *dai)
1022 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1023 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1024 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1025 unsigned long flags;
1028 case SNDRV_PCM_TRIGGER_START:
1029 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1030 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1031 fsl_ssi_tx_config(ssi_private, true);
1033 fsl_ssi_rx_config(ssi_private, true);
1036 case SNDRV_PCM_TRIGGER_STOP:
1037 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1038 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1039 fsl_ssi_tx_config(ssi_private, false);
1041 fsl_ssi_rx_config(ssi_private, false);
1043 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
1044 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
1045 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1046 ssi_private->baudclk_locked = false;
1047 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1055 if (ssi_private->imx_ac97) {
1056 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1057 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1059 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1065 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1067 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1069 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
1070 dai->playback_dma_data = &ssi_private->dma_params_tx;
1071 dai->capture_dma_data = &ssi_private->dma_params_rx;
1077 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1078 .startup = fsl_ssi_startup,
1079 .hw_params = fsl_ssi_hw_params,
1080 .set_fmt = fsl_ssi_set_dai_fmt,
1081 .set_sysclk = fsl_ssi_set_dai_sysclk,
1082 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1083 .trigger = fsl_ssi_trigger,
1086 /* Template for the CPU dai driver structure */
1087 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1088 .probe = fsl_ssi_dai_probe,
1092 .rates = FSLSSI_I2S_RATES,
1093 .formats = FSLSSI_I2S_FORMATS,
1098 .rates = FSLSSI_I2S_RATES,
1099 .formats = FSLSSI_I2S_FORMATS,
1101 .ops = &fsl_ssi_dai_ops,
1104 static const struct snd_soc_component_driver fsl_ssi_component = {
1108 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1111 .stream_name = "AC97 Playback",
1114 .rates = SNDRV_PCM_RATE_8000_48000,
1115 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1118 .stream_name = "AC97 Capture",
1121 .rates = SNDRV_PCM_RATE_48000,
1122 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1124 .ops = &fsl_ssi_dai_ops,
1128 static struct fsl_ssi_private *fsl_ac97_data;
1130 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1133 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1142 write_ssi(lreg, &ssi->sacadd);
1145 write_ssi(lval , &ssi->sacdat);
1147 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1152 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1155 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1157 unsigned short val = -1;
1160 lreg = (reg & 0x7f) << 12;
1161 write_ssi(lreg, &ssi->sacadd);
1162 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1167 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1172 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1173 .read = fsl_ssi_ac97_read,
1174 .write = fsl_ssi_ac97_write,
1178 * Make every character in a string lower-case
1180 static void make_lowercase(char *s)
1186 if ((c >= 'A') && (c <= 'Z'))
1187 *p = c + ('a' - 'A');
1192 static int fsl_ssi_probe(struct platform_device *pdev)
1194 struct fsl_ssi_private *ssi_private;
1196 struct device_attribute *dev_attr = NULL;
1197 struct device_node *np = pdev->dev.of_node;
1198 const struct of_device_id *of_id;
1199 enum fsl_ssi_type hw_type;
1200 const char *p, *sprop;
1201 const uint32_t *iprop;
1202 struct resource res;
1207 /* SSIs that are not connected on the board should have a
1208 * status = "disabled"
1209 * property in their device tree nodes.
1211 if (!of_device_is_available(np))
1214 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1217 hw_type = (enum fsl_ssi_type) of_id->data;
1219 sprop = of_get_property(np, "fsl,mode", NULL);
1221 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1224 if (!strcmp(sprop, "ac97-slave"))
1227 /* The DAI name is the last part of the full name of the node. */
1228 p = strrchr(np->full_name, '/') + 1;
1229 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1232 dev_err(&pdev->dev, "could not allocate DAI object\n");
1236 strcpy(ssi_private->name, p);
1238 ssi_private->use_dma = !of_property_read_bool(np,
1239 "fsl,fiq-stream-filter");
1240 ssi_private->hw_type = hw_type;
1243 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1244 sizeof(fsl_ssi_ac97_dai));
1246 fsl_ac97_data = ssi_private;
1247 ssi_private->imx_ac97 = true;
1249 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1251 /* Initialize this copy of the CPU DAI driver structure */
1252 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1253 sizeof(fsl_ssi_dai_template));
1255 ssi_private->cpu_dai_drv.name = ssi_private->name;
1257 /* Get the addresses and IRQ */
1258 ret = of_address_to_resource(np, 0, &res);
1260 dev_err(&pdev->dev, "could not determine device resources\n");
1263 ssi_private->ssi = of_iomap(np, 0);
1264 if (!ssi_private->ssi) {
1265 dev_err(&pdev->dev, "could not map device resources\n");
1268 ssi_private->ssi_phys = res.start;
1270 ssi_private->irq = irq_of_parse_and_map(np, 0);
1271 if (!ssi_private->irq) {
1272 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1276 /* Are the RX and the TX clocks locked? */
1277 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1278 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1279 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1280 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1283 /* Determine the FIFO depth. */
1284 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1286 ssi_private->fifo_depth = be32_to_cpup(iprop);
1288 /* Older 8610 DTs didn't have the fifo-depth property */
1289 ssi_private->fifo_depth = 8;
1291 ssi_private->baudclk_locked = false;
1292 spin_lock_init(&ssi_private->baudclk_lock);
1295 * imx51 and later SoCs have a slightly different IP that allows the
1296 * SSI configuration while the SSI unit is running.
1298 * More important, it is necessary on those SoCs to configure the
1299 * sperate TX/RX DMA bits just before starting the stream
1300 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1301 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1302 * how the SDMA unit handles the DMA request.
1304 * SDMA units are present on devices starting at imx35 but the imx35
1305 * reference manual states that the DMA bits should not be changed
1306 * while the SSI unit is running (SSIEN). So we support the necessary
1307 * online configuration of fsl-ssi starting at imx51.
1310 case FSL_SSI_MCP8610:
1313 ssi_private->offline_config = true;
1316 ssi_private->offline_config = false;
1320 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1321 hw_type == FSL_SSI_MX35) {
1322 u32 dma_events[2], dmas[4];
1323 ssi_private->ssi_on_imx = true;
1325 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1326 if (IS_ERR(ssi_private->clk)) {
1327 ret = PTR_ERR(ssi_private->clk);
1328 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1331 ret = clk_prepare_enable(ssi_private->clk);
1333 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1338 /* For those SLAVE implementations, we ingore non-baudclk cases
1339 * and, instead, abandon MASTER mode that needs baud clock.
1341 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1342 if (IS_ERR(ssi_private->baudclk))
1343 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1344 PTR_ERR(ssi_private->baudclk));
1346 clk_prepare_enable(ssi_private->baudclk);
1349 * We have burstsize be "fifo_depth - 2" to match the SSI
1350 * watermark setting in fsl_ssi_startup().
1352 ssi_private->dma_params_tx.maxburst =
1353 ssi_private->fifo_depth - 2;
1354 ssi_private->dma_params_rx.maxburst =
1355 ssi_private->fifo_depth - 2;
1356 ssi_private->dma_params_tx.addr =
1357 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1358 ssi_private->dma_params_rx.addr =
1359 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1360 ssi_private->dma_params_tx.filter_data =
1361 &ssi_private->filter_data_tx;
1362 ssi_private->dma_params_rx.filter_data =
1363 &ssi_private->filter_data_rx;
1364 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1365 ssi_private->use_dma) {
1367 * FIXME: This is a temporary solution until all
1368 * necessary dma drivers support the generic dma
1371 ret = of_property_read_u32_array(pdev->dev.of_node,
1372 "fsl,ssi-dma-events", dma_events, 2);
1373 if (ret && ssi_private->use_dma) {
1374 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1378 /* Should this be merge with the above? */
1379 if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
1380 && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1381 ssi_private->use_dual_fifo = true;
1382 /* When using dual fifo mode, we need to keep watermark
1383 * as even numbers due to dma script limitation.
1385 ssi_private->dma_params_tx.maxburst &= ~0x1;
1386 ssi_private->dma_params_rx.maxburst &= ~0x1;
1389 shared = of_device_is_compatible(of_get_parent(np),
1392 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1393 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1394 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1395 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1399 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1400 * different writeable interrupt status registers.
1402 if (ssi_private->use_dma) {
1403 /* The 'name' should not have any slashes in it. */
1404 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1405 fsl_ssi_isr, 0, ssi_private->name,
1407 ssi_private->irq_stats = true;
1409 dev_err(&pdev->dev, "could not claim irq %u\n",
1415 /* Register with ASoC */
1416 dev_set_drvdata(&pdev->dev, ssi_private);
1418 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1419 &ssi_private->cpu_dai_drv, 1);
1421 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1425 ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1429 if (ssi_private->ssi_on_imx) {
1430 if (!ssi_private->use_dma) {
1433 * Some boards use an incompatible codec. To get it
1434 * working, we are using imx-fiq-pcm-audio, that
1435 * can handle those codecs. DMA is not possible in this
1439 ssi_private->fiq_params.irq = ssi_private->irq;
1440 ssi_private->fiq_params.base = ssi_private->ssi;
1441 ssi_private->fiq_params.dma_params_rx =
1442 &ssi_private->dma_params_rx;
1443 ssi_private->fiq_params.dma_params_tx =
1444 &ssi_private->dma_params_tx;
1446 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1450 ret = imx_pcm_dma_init(pdev);
1457 * If codec-handle property is missing from SSI node, we assume
1458 * that the machine driver uses new binding which does not require
1459 * SSI driver to trigger machine driver's probe.
1461 if (!of_get_property(np, "codec-handle", NULL)) {
1462 ssi_private->new_binding = true;
1466 /* Trigger the machine driver's probe function. The platform driver
1467 * name of the machine driver is taken from /compatible property of the
1468 * device tree. We also pass the address of the CPU DAI driver
1471 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1472 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1473 p = strrchr(sprop, ',');
1476 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1477 make_lowercase(name);
1480 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1481 if (IS_ERR(ssi_private->pdev)) {
1482 ret = PTR_ERR(ssi_private->pdev);
1483 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1491 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1492 imx_pcm_fiq_exit(pdev);
1495 fsl_ssi_debugfs_remove(ssi_private);
1498 snd_soc_unregister_component(&pdev->dev);
1501 device_remove_file(&pdev->dev, dev_attr);
1504 if (ssi_private->ssi_on_imx) {
1505 if (!IS_ERR(ssi_private->baudclk))
1506 clk_disable_unprepare(ssi_private->baudclk);
1507 clk_disable_unprepare(ssi_private->clk);
1511 if (ssi_private->irq_stats)
1512 irq_dispose_mapping(ssi_private->irq);
1517 static int fsl_ssi_remove(struct platform_device *pdev)
1519 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1521 fsl_ssi_debugfs_remove(ssi_private);
1523 if (!ssi_private->new_binding)
1524 platform_device_unregister(ssi_private->pdev);
1525 snd_soc_unregister_component(&pdev->dev);
1526 if (ssi_private->ssi_on_imx) {
1527 if (!IS_ERR(ssi_private->baudclk))
1528 clk_disable_unprepare(ssi_private->baudclk);
1529 clk_disable_unprepare(ssi_private->clk);
1531 if (ssi_private->irq_stats)
1532 irq_dispose_mapping(ssi_private->irq);
1537 static struct platform_driver fsl_ssi_driver = {
1539 .name = "fsl-ssi-dai",
1540 .owner = THIS_MODULE,
1541 .of_match_table = fsl_ssi_ids,
1543 .probe = fsl_ssi_probe,
1544 .remove = fsl_ssi_remove,
1547 module_platform_driver(fsl_ssi_driver);
1549 MODULE_ALIAS("platform:fsl-ssi-dai");
1550 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1551 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1552 MODULE_LICENSE("GPL v2");