2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
70 u32 val = readl(addr);
71 val = (val & ~clear) | set;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
89 * This driver currently only supports the SSI running in I2S slave mode.
91 * The SSI has a limitation in that the samples must be in the same byte
92 * order as the host CPU. This is because when multiple bytes are written
93 * to the STX register, the bytes and bits must be written in the same
94 * order. The STX is a shift register, so all the bits need to be aligned
95 * (bit-endianness must match byte-endianness). Processors typically write
96 * the bits within a byte in the same order that the bytes of a word are
97 * written in. So if the host CPU is big-endian, then only big-endian
98 * samples will be written to STX properly.
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
110 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
111 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
113 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
114 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
115 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
116 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
126 struct fsl_ssi_reg_val {
133 struct fsl_ssi_rxtx_reg_val {
134 struct fsl_ssi_reg_val rx;
135 struct fsl_ssi_reg_val tx;
139 * fsl_ssi_private: per-SSI private data
141 * @ssi: pointer to the SSI's registers
142 * @ssi_phys: physical address of the SSI registers
143 * @irq: IRQ of this SSI
144 * @playback: the number of playback streams opened
145 * @capture: the number of capture streams opened
146 * @cpu_dai: the CPU DAI for this device
147 * @dev_attr: the sysfs device attribute structure
148 * @stats: SSI statistics
149 * @name: name for this device
151 struct fsl_ssi_private {
152 struct ccsr_ssi __iomem *ssi;
155 unsigned int fifo_depth;
156 struct snd_soc_dai_driver cpu_dai_drv;
157 struct platform_device *pdev;
159 enum fsl_ssi_type hw_type;
169 spinlock_t baudclk_lock;
172 struct snd_dmaengine_dai_dma_data dma_params_tx;
173 struct snd_dmaengine_dai_dma_data dma_params_rx;
174 struct imx_dma_data filter_data_tx;
175 struct imx_dma_data filter_data_rx;
176 struct imx_pcm_fiq_params fiq_params;
177 /* Register values for rx/tx configuration */
178 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
203 struct dentry *dbg_dir;
204 struct dentry *dbg_stats;
209 static const struct of_device_id fsl_ssi_ids[] = {
210 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
211 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
212 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
213 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
216 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
219 * fsl_ssi_isr: SSI interrupt handler
221 * Although it's possible to use the interrupt handler to send and receive
222 * data to/from the SSI, we use the DMA instead. Programming is more
223 * complicated, but the performance is much better.
225 * This interrupt handler is used only to gather statistics.
227 * @irq: IRQ of the SSI device
228 * @dev_id: pointer to the ssi_private structure for this SSI device
230 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
232 struct fsl_ssi_private *ssi_private = dev_id;
233 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
234 irqreturn_t ret = IRQ_NONE;
237 __be32 sisr_write_mask = 0;
239 switch (ssi_private->hw_type) {
244 case FSL_SSI_MCP8610:
246 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
247 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
248 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
252 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
253 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
257 /* We got an interrupt, so read the status register to see what we
258 were interrupted for. We mask it with the Interrupt Enable register
259 so that we only check for events that we're interested in.
261 sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
263 if (sisr & CCSR_SSI_SISR_RFRC) {
264 ssi_private->stats.rfrc++;
268 if (sisr & CCSR_SSI_SISR_TFRC) {
269 ssi_private->stats.tfrc++;
273 if (sisr & CCSR_SSI_SISR_CMDAU) {
274 ssi_private->stats.cmdau++;
278 if (sisr & CCSR_SSI_SISR_CMDDU) {
279 ssi_private->stats.cmddu++;
283 if (sisr & CCSR_SSI_SISR_RXT) {
284 ssi_private->stats.rxt++;
288 if (sisr & CCSR_SSI_SISR_RDR1) {
289 ssi_private->stats.rdr1++;
293 if (sisr & CCSR_SSI_SISR_RDR0) {
294 ssi_private->stats.rdr0++;
298 if (sisr & CCSR_SSI_SISR_TDE1) {
299 ssi_private->stats.tde1++;
303 if (sisr & CCSR_SSI_SISR_TDE0) {
304 ssi_private->stats.tde0++;
308 if (sisr & CCSR_SSI_SISR_ROE1) {
309 ssi_private->stats.roe1++;
313 if (sisr & CCSR_SSI_SISR_ROE0) {
314 ssi_private->stats.roe0++;
318 if (sisr & CCSR_SSI_SISR_TUE1) {
319 ssi_private->stats.tue1++;
323 if (sisr & CCSR_SSI_SISR_TUE0) {
324 ssi_private->stats.tue0++;
328 if (sisr & CCSR_SSI_SISR_TFS) {
329 ssi_private->stats.tfs++;
333 if (sisr & CCSR_SSI_SISR_RFS) {
334 ssi_private->stats.rfs++;
338 if (sisr & CCSR_SSI_SISR_TLS) {
339 ssi_private->stats.tls++;
343 if (sisr & CCSR_SSI_SISR_RLS) {
344 ssi_private->stats.rls++;
348 if (sisr & CCSR_SSI_SISR_RFF1) {
349 ssi_private->stats.rff1++;
353 if (sisr & CCSR_SSI_SISR_RFF0) {
354 ssi_private->stats.rff0++;
358 if (sisr & CCSR_SSI_SISR_TFE1) {
359 ssi_private->stats.tfe1++;
363 if (sisr & CCSR_SSI_SISR_TFE0) {
364 ssi_private->stats.tfe0++;
368 sisr2 = sisr & sisr_write_mask;
369 /* Clear the bits that we set */
371 write_ssi(sisr2, &ssi->sisr);
376 #if IS_ENABLED(CONFIG_DEBUG_FS)
377 /* Show the statistics of a flag only if its interrupt is enabled. The
378 * compiler will optimze this code to a no-op if the interrupt is not
381 #define SIER_SHOW(flag, name) \
383 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
384 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
389 * fsl_sysfs_ssi_show: display SSI statistics
391 * Display the statistics for the current SSI device. To avoid confusion,
392 * we only show those counts that are enabled.
394 static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
396 struct fsl_ssi_private *ssi_private = s->private;
398 SIER_SHOW(RFRC_EN, rfrc);
399 SIER_SHOW(TFRC_EN, tfrc);
400 SIER_SHOW(CMDAU_EN, cmdau);
401 SIER_SHOW(CMDDU_EN, cmddu);
402 SIER_SHOW(RXT_EN, rxt);
403 SIER_SHOW(RDR1_EN, rdr1);
404 SIER_SHOW(RDR0_EN, rdr0);
405 SIER_SHOW(TDE1_EN, tde1);
406 SIER_SHOW(TDE0_EN, tde0);
407 SIER_SHOW(ROE1_EN, roe1);
408 SIER_SHOW(ROE0_EN, roe0);
409 SIER_SHOW(TUE1_EN, tue1);
410 SIER_SHOW(TUE0_EN, tue0);
411 SIER_SHOW(TFS_EN, tfs);
412 SIER_SHOW(RFS_EN, rfs);
413 SIER_SHOW(TLS_EN, tls);
414 SIER_SHOW(RLS_EN, rls);
415 SIER_SHOW(RFF1_EN, rff1);
416 SIER_SHOW(RFF0_EN, rff0);
417 SIER_SHOW(TFE1_EN, tfe1);
418 SIER_SHOW(TFE0_EN, tfe0);
423 static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
425 return single_open(file, fsl_ssi_stats_show, inode->i_private);
428 static const struct file_operations fsl_ssi_stats_ops = {
429 .open = fsl_ssi_stats_open,
432 .release = single_release,
435 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
438 ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
439 if (!ssi_private->dbg_dir)
442 ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
443 ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
444 if (!ssi_private->dbg_stats) {
445 debugfs_remove(ssi_private->dbg_dir);
452 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
454 debugfs_remove(ssi_private->dbg_stats);
455 debugfs_remove(ssi_private->dbg_dir);
460 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
466 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
470 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
473 * Enable/Disable all rx/tx config flags at once.
475 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
478 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
479 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
482 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
483 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
484 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
486 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
487 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
488 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
493 * Calculate the bits that have to be disabled for the current stream that is
494 * getting disabled. This keeps the bits enabled that are necessary for the
495 * second stream to work if 'stream_active' is true.
497 * Detailed calculation:
498 * These are the values that need to be active after disabling. For non-active
499 * second stream, this is 0:
500 * vals_stream * !!stream_active
502 * The following computes the overall differences between the setup for the
503 * to-disable stream and the active stream, a simple XOR:
504 * vals_disable ^ (vals_stream * !!(stream_active))
506 * The full expression adds a mask on all values we care about
508 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
510 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
513 * Enable/Disable a ssi configuration. You have to pass either
514 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
516 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
517 struct fsl_ssi_reg_val *vals)
519 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
520 struct fsl_ssi_reg_val *avals;
521 u32 scr_val = read_ssi(&ssi->scr);
522 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
523 !!(scr_val & CCSR_SSI_SCR_RE);
526 if (nr_active_streams - 1 > 0)
531 /* Find the other direction values rx or tx which we do not want to
533 if (&ssi_private->rxtx_reg_val.rx == vals)
534 avals = &ssi_private->rxtx_reg_val.tx;
536 avals = &ssi_private->rxtx_reg_val.rx;
538 /* If vals should be disabled, start with disabling the unit */
540 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
542 write_ssi_mask(&ssi->scr, scr, 0);
546 * We are running on a SoC which does not support online SSI
547 * reconfiguration, so we have to enable all necessary flags at once
548 * even if we do not use them later (capture and playback configuration)
550 if (ssi_private->offline_config) {
551 if ((enable && !nr_active_streams) ||
552 (!enable && !keep_active))
553 fsl_ssi_rxtx_config(ssi_private, enable);
559 * Configure single direction units while the SSI unit is running
560 * (online configuration)
563 write_ssi_mask(&ssi->sier, 0, vals->sier);
564 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
565 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
572 * Disabling the necessary flags for one of rx/tx while the
573 * other stream is active is a little bit more difficult. We
574 * have to disable only those flags that differ between both
575 * streams (rx XOR tx) and that are set in the stream that is
576 * disabled now. Otherwise we could alter flags of the other
580 /* These assignments are simply vals without bits set in avals*/
581 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
583 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
585 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
588 write_ssi_mask(&ssi->srcr, srcr, 0);
589 write_ssi_mask(&ssi->stcr, stcr, 0);
590 write_ssi_mask(&ssi->sier, sier, 0);
594 /* Enabling of subunits is done after configuration */
596 write_ssi_mask(&ssi->scr, 0, vals->scr);
600 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
602 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
605 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
607 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
611 * Setup rx/tx register values used to enable/disable the streams. These will
612 * be used later in fsl_ssi_config to setup the streams without the need to
613 * check for all different SSI modes.
615 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
617 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
619 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
620 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
622 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
623 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
626 if (!ssi_private->imx_ac97) {
627 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
628 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
629 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
630 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
633 if (ssi_private->use_dma) {
634 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
635 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
637 reg->rx.sier |= CCSR_SSI_SIER_RIE;
638 reg->tx.sier |= CCSR_SSI_SIER_TIE;
641 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
642 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
645 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
647 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
650 * Setup the clock control register
652 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
654 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
658 * Enable AC97 mode and startup the SSI
660 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
662 write_ssi(0xff, &ssi->saccdis);
663 write_ssi(0x300, &ssi->saccen);
666 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
667 * codec before a stream is started.
669 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
670 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
672 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
676 * fsl_ssi_startup: create a new substream
678 * This is the first function called when a stream is opened.
680 * If this is the first stream open, then grab the IRQ and program most of
683 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
684 struct snd_soc_dai *dai)
686 struct snd_soc_pcm_runtime *rtd = substream->private_data;
687 struct fsl_ssi_private *ssi_private =
688 snd_soc_dai_get_drvdata(rtd->cpu_dai);
691 if (!dai->active && !ssi_private->imx_ac97) {
692 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
693 ssi_private->baudclk_locked = false;
694 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
697 /* When using dual fifo mode, it is safer to ensure an even period
698 * size. If appearing to an odd number while DMA always starts its
699 * task from fifo0, fifo1 would be neglected at the end of each
700 * period. But SSI would still access fifo1 with an invalid data.
702 if (ssi_private->use_dual_fifo)
703 snd_pcm_hw_constraint_step(substream->runtime, 0,
704 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
710 * fsl_ssi_hw_params - program the sample size
712 * Most of the SSI registers have been programmed in the startup function,
713 * but the word length must be programmed here. Unfortunately, programming
714 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
715 * cause a problem with supporting simultaneous playback and capture. If
716 * the SSI is already playing a stream, then that stream may be temporarily
717 * stopped when you start capture.
719 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
722 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
723 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
725 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
726 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
727 unsigned int channels = params_channels(hw_params);
728 unsigned int sample_size =
729 snd_pcm_format_width(params_format(hw_params));
730 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
731 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
734 * If we're in synchronous mode, and the SSI is already enabled,
735 * then STCCR is already set properly.
737 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
741 * FIXME: The documentation says that SxCCR[WL] should not be
742 * modified while the SSI is enabled. The only time this can
743 * happen is if we're trying to do simultaneous playback and
744 * capture in asynchronous mode. Unfortunately, I have been enable
745 * to get that to work at all on the P1022DS. Therefore, we don't
746 * bother to disable/enable the SSI when setting SxCCR[WL], because
747 * the SSI will stop anyway. Maybe one day, this will get fixed.
750 /* In synchronous mode, the SSI uses STCCR for capture */
751 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
752 ssi_private->cpu_dai_drv.symmetric_rates)
753 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
755 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
757 if (!ssi_private->imx_ac97)
758 write_ssi_mask(&ssi->scr,
759 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
760 channels == 1 ? 0 : ssi_private->i2s_mode);
766 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
768 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
770 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
771 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
772 u32 strcr = 0, stcr, srcr, scr, mask;
775 fsl_ssi_setup_reg_vals(ssi_private);
777 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
779 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
780 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
782 stcr = read_ssi(&ssi->stcr) & ~mask;
783 srcr = read_ssi(&ssi->srcr) & ~mask;
785 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
786 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
787 case SND_SOC_DAIFMT_I2S:
788 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
789 case SND_SOC_DAIFMT_CBS_CFS:
790 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
792 case SND_SOC_DAIFMT_CBM_CFM:
793 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
799 /* Data on rising edge of bclk, frame low, 1clk before data */
800 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
801 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
803 case SND_SOC_DAIFMT_LEFT_J:
804 /* Data on rising edge of bclk, frame high */
805 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
807 case SND_SOC_DAIFMT_DSP_A:
808 /* Data on rising edge of bclk, frame high, 1clk before data */
809 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
810 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
812 case SND_SOC_DAIFMT_DSP_B:
813 /* Data on rising edge of bclk, frame high */
814 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
815 CCSR_SSI_STCR_TXBIT0;
817 case SND_SOC_DAIFMT_AC97:
818 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
823 scr |= ssi_private->i2s_mode;
825 /* DAI clock inversion */
826 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
827 case SND_SOC_DAIFMT_NB_NF:
828 /* Nothing to do for both normal cases */
830 case SND_SOC_DAIFMT_IB_NF:
831 /* Invert bit clock */
832 strcr ^= CCSR_SSI_STCR_TSCKP;
834 case SND_SOC_DAIFMT_NB_IF:
835 /* Invert frame clock */
836 strcr ^= CCSR_SSI_STCR_TFSI;
838 case SND_SOC_DAIFMT_IB_IF:
839 /* Invert both clocks */
840 strcr ^= CCSR_SSI_STCR_TSCKP;
841 strcr ^= CCSR_SSI_STCR_TFSI;
847 /* DAI clock master masks */
848 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
849 case SND_SOC_DAIFMT_CBS_CFS:
850 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
851 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
853 case SND_SOC_DAIFMT_CBM_CFM:
854 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
863 if (ssi_private->cpu_dai_drv.symmetric_rates) {
864 /* Need to clear RXDIR when using SYNC mode */
865 srcr &= ~CCSR_SSI_SRCR_RXDIR;
866 scr |= CCSR_SSI_SCR_SYN;
869 write_ssi(stcr, &ssi->stcr);
870 write_ssi(srcr, &ssi->srcr);
871 write_ssi(scr, &ssi->scr);
874 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
875 * use FIFO 1. We program the transmit water to signal a DMA transfer
876 * if there are only two (or fewer) elements left in the FIFO. Two
877 * elements equals one frame (left channel, right channel). This value,
878 * however, depends on the depth of the transmit buffer.
880 * We set the watermark on the same level as the DMA burstsize. For
881 * fiq it is probably better to use the biggest possible watermark
884 if (ssi_private->use_dma)
885 wm = ssi_private->fifo_depth - 2;
887 wm = ssi_private->fifo_depth;
889 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
890 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
893 if (ssi_private->use_dual_fifo) {
894 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
895 CCSR_SSI_SRCR_RFEN1);
896 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
897 CCSR_SSI_STCR_TFEN1);
898 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
899 CCSR_SSI_SCR_TCH_EN);
902 if (fmt & SND_SOC_DAIFMT_AC97)
903 fsl_ssi_setup_ac97(ssi_private);
909 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
911 * Note: This function can be only called when using SSI as DAI master
913 * Quick instruction for parameters:
914 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
915 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
917 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
918 int clk_id, unsigned int freq, int dir)
920 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
921 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
922 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
923 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
924 unsigned long flags, clkrate, baudrate, tmprate;
925 u64 sub, savesub = 100000;
927 /* Don't apply it to any non-baudclk circumstance */
928 if (IS_ERR(ssi_private->baudclk))
931 /* It should be already enough to divide clock by setting pm alone */
935 factor = (div2 + 1) * (7 * psr + 1) * 2;
937 for (i = 0; i < 255; i++) {
938 /* The bclk rate must be smaller than 1/5 sysclk rate */
939 if (factor * (i + 1) < 5)
942 tmprate = freq * factor * (i + 2);
943 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
945 do_div(clkrate, factor);
946 afreq = (u32)clkrate / (i + 1);
950 else if (freq / afreq == 1)
952 else if (afreq / freq == 1)
957 /* Calculate the fraction */
972 /* No proper pm found if it is still remaining the initial value */
974 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
978 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
979 (psr ? CCSR_SSI_SxCCR_PSR : 0);
980 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
982 if (dir == SND_SOC_CLOCK_OUT || synchronous)
983 write_ssi_mask(&ssi->stccr, mask, stccr);
985 write_ssi_mask(&ssi->srccr, mask, stccr);
987 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
988 if (!ssi_private->baudclk_locked) {
989 ret = clk_set_rate(ssi_private->baudclk, baudrate);
991 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
992 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
995 ssi_private->baudclk_locked = true;
997 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1003 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1005 * Note: This function can be only called when using SSI as DAI master
1007 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1008 u32 rx_mask, int slots, int slot_width)
1010 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1011 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1014 /* The slot number should be >= 2 if using Network mode or I2S mode */
1015 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
1016 if (val && slots < 2) {
1017 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1021 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
1022 CCSR_SSI_SxCCR_DC(slots));
1023 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
1024 CCSR_SSI_SxCCR_DC(slots));
1026 /* The register SxMSKs needs SSI to provide essential clock due to
1027 * hardware design. So we here temporarily enable SSI to set them.
1029 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
1030 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
1032 write_ssi(tx_mask, &ssi->stmsk);
1033 write_ssi(rx_mask, &ssi->srmsk);
1035 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
1041 * fsl_ssi_trigger: start and stop the DMA transfer.
1043 * This function is called by ALSA to start, stop, pause, and resume the DMA
1046 * The DMA channel is in external master start and pause mode, which
1047 * means the SSI completely controls the flow of data.
1049 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1050 struct snd_soc_dai *dai)
1052 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1053 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1054 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1055 unsigned long flags;
1058 case SNDRV_PCM_TRIGGER_START:
1059 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1060 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1061 fsl_ssi_tx_config(ssi_private, true);
1063 fsl_ssi_rx_config(ssi_private, true);
1066 case SNDRV_PCM_TRIGGER_STOP:
1067 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1068 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1069 fsl_ssi_tx_config(ssi_private, false);
1071 fsl_ssi_rx_config(ssi_private, false);
1073 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
1074 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
1075 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1076 ssi_private->baudclk_locked = false;
1077 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1085 if (ssi_private->imx_ac97) {
1086 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1087 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1089 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1095 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1097 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1099 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
1100 dai->playback_dma_data = &ssi_private->dma_params_tx;
1101 dai->capture_dma_data = &ssi_private->dma_params_rx;
1107 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1108 .startup = fsl_ssi_startup,
1109 .hw_params = fsl_ssi_hw_params,
1110 .set_fmt = fsl_ssi_set_dai_fmt,
1111 .set_sysclk = fsl_ssi_set_dai_sysclk,
1112 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1113 .trigger = fsl_ssi_trigger,
1116 /* Template for the CPU dai driver structure */
1117 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1118 .probe = fsl_ssi_dai_probe,
1122 .rates = FSLSSI_I2S_RATES,
1123 .formats = FSLSSI_I2S_FORMATS,
1128 .rates = FSLSSI_I2S_RATES,
1129 .formats = FSLSSI_I2S_FORMATS,
1131 .ops = &fsl_ssi_dai_ops,
1134 static const struct snd_soc_component_driver fsl_ssi_component = {
1138 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1141 .stream_name = "AC97 Playback",
1144 .rates = SNDRV_PCM_RATE_8000_48000,
1145 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1148 .stream_name = "AC97 Capture",
1151 .rates = SNDRV_PCM_RATE_48000,
1152 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1154 .ops = &fsl_ssi_dai_ops,
1158 static struct fsl_ssi_private *fsl_ac97_data;
1160 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1163 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1172 write_ssi(lreg, &ssi->sacadd);
1175 write_ssi(lval , &ssi->sacdat);
1177 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1182 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1185 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1187 unsigned short val = -1;
1190 lreg = (reg & 0x7f) << 12;
1191 write_ssi(lreg, &ssi->sacadd);
1192 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1197 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1202 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1203 .read = fsl_ssi_ac97_read,
1204 .write = fsl_ssi_ac97_write,
1208 * Make every character in a string lower-case
1210 static void make_lowercase(char *s)
1216 if ((c >= 'A') && (c <= 'Z'))
1217 *p = c + ('a' - 'A');
1222 static int fsl_ssi_probe(struct platform_device *pdev)
1224 struct fsl_ssi_private *ssi_private;
1226 struct device_attribute *dev_attr = NULL;
1227 struct device_node *np = pdev->dev.of_node;
1228 const struct of_device_id *of_id;
1229 enum fsl_ssi_type hw_type;
1230 const char *p, *sprop;
1231 const uint32_t *iprop;
1232 struct resource res;
1237 /* SSIs that are not connected on the board should have a
1238 * status = "disabled"
1239 * property in their device tree nodes.
1241 if (!of_device_is_available(np))
1244 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1247 hw_type = (enum fsl_ssi_type) of_id->data;
1249 sprop = of_get_property(np, "fsl,mode", NULL);
1251 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1254 if (!strcmp(sprop, "ac97-slave"))
1257 /* The DAI name is the last part of the full name of the node. */
1258 p = strrchr(np->full_name, '/') + 1;
1259 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1262 dev_err(&pdev->dev, "could not allocate DAI object\n");
1266 strcpy(ssi_private->name, p);
1268 ssi_private->use_dma = !of_property_read_bool(np,
1269 "fsl,fiq-stream-filter");
1270 ssi_private->hw_type = hw_type;
1273 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1274 sizeof(fsl_ssi_ac97_dai));
1276 fsl_ac97_data = ssi_private;
1277 ssi_private->imx_ac97 = true;
1279 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1281 /* Initialize this copy of the CPU DAI driver structure */
1282 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1283 sizeof(fsl_ssi_dai_template));
1285 ssi_private->cpu_dai_drv.name = ssi_private->name;
1287 /* Get the addresses and IRQ */
1288 ret = of_address_to_resource(np, 0, &res);
1290 dev_err(&pdev->dev, "could not determine device resources\n");
1293 ssi_private->ssi = of_iomap(np, 0);
1294 if (!ssi_private->ssi) {
1295 dev_err(&pdev->dev, "could not map device resources\n");
1298 ssi_private->ssi_phys = res.start;
1300 ssi_private->irq = irq_of_parse_and_map(np, 0);
1301 if (!ssi_private->irq) {
1302 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1306 /* Are the RX and the TX clocks locked? */
1307 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1308 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1309 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1310 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1313 /* Determine the FIFO depth. */
1314 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1316 ssi_private->fifo_depth = be32_to_cpup(iprop);
1318 /* Older 8610 DTs didn't have the fifo-depth property */
1319 ssi_private->fifo_depth = 8;
1321 ssi_private->baudclk_locked = false;
1322 spin_lock_init(&ssi_private->baudclk_lock);
1325 * imx51 and later SoCs have a slightly different IP that allows the
1326 * SSI configuration while the SSI unit is running.
1328 * More important, it is necessary on those SoCs to configure the
1329 * sperate TX/RX DMA bits just before starting the stream
1330 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1331 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1332 * how the SDMA unit handles the DMA request.
1334 * SDMA units are present on devices starting at imx35 but the imx35
1335 * reference manual states that the DMA bits should not be changed
1336 * while the SSI unit is running (SSIEN). So we support the necessary
1337 * online configuration of fsl-ssi starting at imx51.
1340 case FSL_SSI_MCP8610:
1343 ssi_private->offline_config = true;
1346 ssi_private->offline_config = false;
1350 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1351 hw_type == FSL_SSI_MX35) {
1352 u32 dma_events[2], dmas[4];
1353 ssi_private->ssi_on_imx = true;
1355 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1356 if (IS_ERR(ssi_private->clk)) {
1357 ret = PTR_ERR(ssi_private->clk);
1358 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1361 ret = clk_prepare_enable(ssi_private->clk);
1363 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1368 /* For those SLAVE implementations, we ingore non-baudclk cases
1369 * and, instead, abandon MASTER mode that needs baud clock.
1371 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1372 if (IS_ERR(ssi_private->baudclk))
1373 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1374 PTR_ERR(ssi_private->baudclk));
1376 clk_prepare_enable(ssi_private->baudclk);
1379 * We have burstsize be "fifo_depth - 2" to match the SSI
1380 * watermark setting in fsl_ssi_startup().
1382 ssi_private->dma_params_tx.maxburst =
1383 ssi_private->fifo_depth - 2;
1384 ssi_private->dma_params_rx.maxburst =
1385 ssi_private->fifo_depth - 2;
1386 ssi_private->dma_params_tx.addr =
1387 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1388 ssi_private->dma_params_rx.addr =
1389 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1390 ssi_private->dma_params_tx.filter_data =
1391 &ssi_private->filter_data_tx;
1392 ssi_private->dma_params_rx.filter_data =
1393 &ssi_private->filter_data_rx;
1394 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1395 ssi_private->use_dma) {
1397 * FIXME: This is a temporary solution until all
1398 * necessary dma drivers support the generic dma
1401 ret = of_property_read_u32_array(pdev->dev.of_node,
1402 "fsl,ssi-dma-events", dma_events, 2);
1403 if (ret && ssi_private->use_dma) {
1404 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1408 /* Should this be merge with the above? */
1409 if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
1410 && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1411 ssi_private->use_dual_fifo = true;
1412 /* When using dual fifo mode, we need to keep watermark
1413 * as even numbers due to dma script limitation.
1415 ssi_private->dma_params_tx.maxburst &= ~0x1;
1416 ssi_private->dma_params_rx.maxburst &= ~0x1;
1419 shared = of_device_is_compatible(of_get_parent(np),
1422 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1423 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1424 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1425 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1429 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1430 * different writeable interrupt status registers.
1432 if (ssi_private->use_dma) {
1433 /* The 'name' should not have any slashes in it. */
1434 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1435 fsl_ssi_isr, 0, ssi_private->name,
1437 ssi_private->irq_stats = true;
1439 dev_err(&pdev->dev, "could not claim irq %u\n",
1445 /* Register with ASoC */
1446 dev_set_drvdata(&pdev->dev, ssi_private);
1448 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1449 &ssi_private->cpu_dai_drv, 1);
1451 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1455 ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1459 if (ssi_private->ssi_on_imx) {
1460 if (!ssi_private->use_dma) {
1463 * Some boards use an incompatible codec. To get it
1464 * working, we are using imx-fiq-pcm-audio, that
1465 * can handle those codecs. DMA is not possible in this
1469 ssi_private->fiq_params.irq = ssi_private->irq;
1470 ssi_private->fiq_params.base = ssi_private->ssi;
1471 ssi_private->fiq_params.dma_params_rx =
1472 &ssi_private->dma_params_rx;
1473 ssi_private->fiq_params.dma_params_tx =
1474 &ssi_private->dma_params_tx;
1476 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1480 ret = imx_pcm_dma_init(pdev);
1487 * If codec-handle property is missing from SSI node, we assume
1488 * that the machine driver uses new binding which does not require
1489 * SSI driver to trigger machine driver's probe.
1491 if (!of_get_property(np, "codec-handle", NULL)) {
1492 ssi_private->new_binding = true;
1496 /* Trigger the machine driver's probe function. The platform driver
1497 * name of the machine driver is taken from /compatible property of the
1498 * device tree. We also pass the address of the CPU DAI driver
1501 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1502 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1503 p = strrchr(sprop, ',');
1506 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1507 make_lowercase(name);
1510 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1511 if (IS_ERR(ssi_private->pdev)) {
1512 ret = PTR_ERR(ssi_private->pdev);
1513 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1521 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1522 imx_pcm_fiq_exit(pdev);
1525 fsl_ssi_debugfs_remove(ssi_private);
1528 snd_soc_unregister_component(&pdev->dev);
1531 device_remove_file(&pdev->dev, dev_attr);
1534 if (ssi_private->ssi_on_imx) {
1535 if (!IS_ERR(ssi_private->baudclk))
1536 clk_disable_unprepare(ssi_private->baudclk);
1537 clk_disable_unprepare(ssi_private->clk);
1541 if (ssi_private->irq_stats)
1542 irq_dispose_mapping(ssi_private->irq);
1547 static int fsl_ssi_remove(struct platform_device *pdev)
1549 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1551 fsl_ssi_debugfs_remove(ssi_private);
1553 if (!ssi_private->new_binding)
1554 platform_device_unregister(ssi_private->pdev);
1555 snd_soc_unregister_component(&pdev->dev);
1556 if (ssi_private->ssi_on_imx) {
1557 if (!IS_ERR(ssi_private->baudclk))
1558 clk_disable_unprepare(ssi_private->baudclk);
1559 clk_disable_unprepare(ssi_private->clk);
1561 if (ssi_private->irq_stats)
1562 irq_dispose_mapping(ssi_private->irq);
1567 static struct platform_driver fsl_ssi_driver = {
1569 .name = "fsl-ssi-dai",
1570 .owner = THIS_MODULE,
1571 .of_match_table = fsl_ssi_ids,
1573 .probe = fsl_ssi_probe,
1574 .remove = fsl_ssi_remove,
1577 module_platform_driver(fsl_ssi_driver);
1579 MODULE_ALIAS("platform:fsl-ssi-dai");
1580 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1581 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1582 MODULE_LICENSE("GPL v2");