2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
69 u32 val = readl(addr);
70 val = (val & ~clear) | set;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
110 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
111 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
112 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
113 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
114 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
123 struct fsl_ssi_reg_val {
130 struct fsl_ssi_rxtx_reg_val {
131 struct fsl_ssi_reg_val rx;
132 struct fsl_ssi_reg_val tx;
136 * fsl_ssi_private: per-SSI private data
138 * @ssi: pointer to the SSI's registers
139 * @ssi_phys: physical address of the SSI registers
140 * @irq: IRQ of this SSI
141 * @playback: the number of playback streams opened
142 * @capture: the number of capture streams opened
143 * @cpu_dai: the CPU DAI for this device
144 * @dev_attr: the sysfs device attribute structure
145 * @stats: SSI statistics
146 * @name: name for this device
148 struct fsl_ssi_private {
149 struct ccsr_ssi __iomem *ssi;
152 unsigned int fifo_depth;
153 struct snd_soc_dai_driver cpu_dai_drv;
154 struct platform_device *pdev;
156 enum fsl_ssi_type hw_type;
166 spinlock_t baudclk_lock;
169 struct snd_dmaengine_dai_dma_data dma_params_tx;
170 struct snd_dmaengine_dai_dma_data dma_params_rx;
171 struct imx_dma_data filter_data_tx;
172 struct imx_dma_data filter_data_rx;
173 struct imx_pcm_fiq_params fiq_params;
174 /* Register values for rx/tx configuration */
175 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
177 struct fsl_ssi_dbg dbg_stats;
182 static const struct of_device_id fsl_ssi_ids[] = {
183 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
184 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
185 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
186 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
189 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
192 * fsl_ssi_isr: SSI interrupt handler
194 * Although it's possible to use the interrupt handler to send and receive
195 * data to/from the SSI, we use the DMA instead. Programming is more
196 * complicated, but the performance is much better.
198 * This interrupt handler is used only to gather statistics.
200 * @irq: IRQ of the SSI device
201 * @dev_id: pointer to the ssi_private structure for this SSI device
203 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
205 struct fsl_ssi_private *ssi_private = dev_id;
206 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
209 __be32 sisr_write_mask = 0;
211 switch (ssi_private->hw_type) {
216 case FSL_SSI_MCP8610:
218 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
219 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
220 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
224 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
225 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
229 /* We got an interrupt, so read the status register to see what we
230 were interrupted for. We mask it with the Interrupt Enable register
231 so that we only check for events that we're interested in.
233 sisr = read_ssi(&ssi->sisr);
235 sisr2 = sisr & sisr_write_mask;
236 /* Clear the bits that we set */
238 write_ssi(sisr2, &ssi->sisr);
240 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
246 * Enable/Disable all rx/tx config flags at once.
248 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
251 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
252 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
255 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
256 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
257 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
259 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
260 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
261 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
266 * Calculate the bits that have to be disabled for the current stream that is
267 * getting disabled. This keeps the bits enabled that are necessary for the
268 * second stream to work if 'stream_active' is true.
270 * Detailed calculation:
271 * These are the values that need to be active after disabling. For non-active
272 * second stream, this is 0:
273 * vals_stream * !!stream_active
275 * The following computes the overall differences between the setup for the
276 * to-disable stream and the active stream, a simple XOR:
277 * vals_disable ^ (vals_stream * !!(stream_active))
279 * The full expression adds a mask on all values we care about
281 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
283 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
286 * Enable/Disable a ssi configuration. You have to pass either
287 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
289 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
290 struct fsl_ssi_reg_val *vals)
292 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
293 struct fsl_ssi_reg_val *avals;
294 u32 scr_val = read_ssi(&ssi->scr);
295 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
296 !!(scr_val & CCSR_SSI_SCR_RE);
299 if (nr_active_streams - 1 > 0)
304 /* Find the other direction values rx or tx which we do not want to
306 if (&ssi_private->rxtx_reg_val.rx == vals)
307 avals = &ssi_private->rxtx_reg_val.tx;
309 avals = &ssi_private->rxtx_reg_val.rx;
311 /* If vals should be disabled, start with disabling the unit */
313 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
315 write_ssi_mask(&ssi->scr, scr, 0);
319 * We are running on a SoC which does not support online SSI
320 * reconfiguration, so we have to enable all necessary flags at once
321 * even if we do not use them later (capture and playback configuration)
323 if (ssi_private->offline_config) {
324 if ((enable && !nr_active_streams) ||
325 (!enable && !keep_active))
326 fsl_ssi_rxtx_config(ssi_private, enable);
332 * Configure single direction units while the SSI unit is running
333 * (online configuration)
336 write_ssi_mask(&ssi->sier, 0, vals->sier);
337 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
338 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
345 * Disabling the necessary flags for one of rx/tx while the
346 * other stream is active is a little bit more difficult. We
347 * have to disable only those flags that differ between both
348 * streams (rx XOR tx) and that are set in the stream that is
349 * disabled now. Otherwise we could alter flags of the other
353 /* These assignments are simply vals without bits set in avals*/
354 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
356 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
358 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
361 write_ssi_mask(&ssi->srcr, srcr, 0);
362 write_ssi_mask(&ssi->stcr, stcr, 0);
363 write_ssi_mask(&ssi->sier, sier, 0);
367 /* Enabling of subunits is done after configuration */
369 write_ssi_mask(&ssi->scr, 0, vals->scr);
373 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
375 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
378 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
380 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
384 * Setup rx/tx register values used to enable/disable the streams. These will
385 * be used later in fsl_ssi_config to setup the streams without the need to
386 * check for all different SSI modes.
388 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
390 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
392 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
393 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
395 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
396 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
399 if (!ssi_private->imx_ac97) {
400 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
401 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
402 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
403 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
406 if (ssi_private->use_dma) {
407 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
408 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
410 reg->rx.sier |= CCSR_SSI_SIER_RIE;
411 reg->tx.sier |= CCSR_SSI_SIER_TIE;
414 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
415 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
418 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
420 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
423 * Setup the clock control register
425 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
427 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
431 * Enable AC97 mode and startup the SSI
433 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
435 write_ssi(0xff, &ssi->saccdis);
436 write_ssi(0x300, &ssi->saccen);
439 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
440 * codec before a stream is started.
442 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
443 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
445 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
449 * fsl_ssi_startup: create a new substream
451 * This is the first function called when a stream is opened.
453 * If this is the first stream open, then grab the IRQ and program most of
456 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
457 struct snd_soc_dai *dai)
459 struct snd_soc_pcm_runtime *rtd = substream->private_data;
460 struct fsl_ssi_private *ssi_private =
461 snd_soc_dai_get_drvdata(rtd->cpu_dai);
464 if (!dai->active && !ssi_private->imx_ac97) {
465 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
466 ssi_private->baudclk_locked = false;
467 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
470 /* When using dual fifo mode, it is safer to ensure an even period
471 * size. If appearing to an odd number while DMA always starts its
472 * task from fifo0, fifo1 would be neglected at the end of each
473 * period. But SSI would still access fifo1 with an invalid data.
475 if (ssi_private->use_dual_fifo)
476 snd_pcm_hw_constraint_step(substream->runtime, 0,
477 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
483 * fsl_ssi_hw_params - program the sample size
485 * Most of the SSI registers have been programmed in the startup function,
486 * but the word length must be programmed here. Unfortunately, programming
487 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
488 * cause a problem with supporting simultaneous playback and capture. If
489 * the SSI is already playing a stream, then that stream may be temporarily
490 * stopped when you start capture.
492 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
495 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
496 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
498 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
499 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
500 unsigned int channels = params_channels(hw_params);
501 unsigned int sample_size =
502 snd_pcm_format_width(params_format(hw_params));
503 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
504 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
507 * If we're in synchronous mode, and the SSI is already enabled,
508 * then STCCR is already set properly.
510 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
514 * FIXME: The documentation says that SxCCR[WL] should not be
515 * modified while the SSI is enabled. The only time this can
516 * happen is if we're trying to do simultaneous playback and
517 * capture in asynchronous mode. Unfortunately, I have been enable
518 * to get that to work at all on the P1022DS. Therefore, we don't
519 * bother to disable/enable the SSI when setting SxCCR[WL], because
520 * the SSI will stop anyway. Maybe one day, this will get fixed.
523 /* In synchronous mode, the SSI uses STCCR for capture */
524 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
525 ssi_private->cpu_dai_drv.symmetric_rates)
526 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
528 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
530 if (!ssi_private->imx_ac97)
531 write_ssi_mask(&ssi->scr,
532 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
533 channels == 1 ? 0 : ssi_private->i2s_mode);
539 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
541 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
543 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
544 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
545 u32 strcr = 0, stcr, srcr, scr, mask;
548 fsl_ssi_setup_reg_vals(ssi_private);
550 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
552 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
553 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
555 stcr = read_ssi(&ssi->stcr) & ~mask;
556 srcr = read_ssi(&ssi->srcr) & ~mask;
558 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
559 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
560 case SND_SOC_DAIFMT_I2S:
561 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
562 case SND_SOC_DAIFMT_CBS_CFS:
563 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
565 case SND_SOC_DAIFMT_CBM_CFM:
566 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
572 /* Data on rising edge of bclk, frame low, 1clk before data */
573 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
574 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
576 case SND_SOC_DAIFMT_LEFT_J:
577 /* Data on rising edge of bclk, frame high */
578 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
580 case SND_SOC_DAIFMT_DSP_A:
581 /* Data on rising edge of bclk, frame high, 1clk before data */
582 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
583 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
585 case SND_SOC_DAIFMT_DSP_B:
586 /* Data on rising edge of bclk, frame high */
587 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
588 CCSR_SSI_STCR_TXBIT0;
590 case SND_SOC_DAIFMT_AC97:
591 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
596 scr |= ssi_private->i2s_mode;
598 /* DAI clock inversion */
599 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
600 case SND_SOC_DAIFMT_NB_NF:
601 /* Nothing to do for both normal cases */
603 case SND_SOC_DAIFMT_IB_NF:
604 /* Invert bit clock */
605 strcr ^= CCSR_SSI_STCR_TSCKP;
607 case SND_SOC_DAIFMT_NB_IF:
608 /* Invert frame clock */
609 strcr ^= CCSR_SSI_STCR_TFSI;
611 case SND_SOC_DAIFMT_IB_IF:
612 /* Invert both clocks */
613 strcr ^= CCSR_SSI_STCR_TSCKP;
614 strcr ^= CCSR_SSI_STCR_TFSI;
620 /* DAI clock master masks */
621 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
622 case SND_SOC_DAIFMT_CBS_CFS:
623 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
624 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
626 case SND_SOC_DAIFMT_CBM_CFM:
627 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
636 if (ssi_private->cpu_dai_drv.symmetric_rates) {
637 /* Need to clear RXDIR when using SYNC mode */
638 srcr &= ~CCSR_SSI_SRCR_RXDIR;
639 scr |= CCSR_SSI_SCR_SYN;
642 write_ssi(stcr, &ssi->stcr);
643 write_ssi(srcr, &ssi->srcr);
644 write_ssi(scr, &ssi->scr);
647 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
648 * use FIFO 1. We program the transmit water to signal a DMA transfer
649 * if there are only two (or fewer) elements left in the FIFO. Two
650 * elements equals one frame (left channel, right channel). This value,
651 * however, depends on the depth of the transmit buffer.
653 * We set the watermark on the same level as the DMA burstsize. For
654 * fiq it is probably better to use the biggest possible watermark
657 if (ssi_private->use_dma)
658 wm = ssi_private->fifo_depth - 2;
660 wm = ssi_private->fifo_depth;
662 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
663 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
666 if (ssi_private->use_dual_fifo) {
667 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
668 CCSR_SSI_SRCR_RFEN1);
669 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
670 CCSR_SSI_STCR_TFEN1);
671 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
672 CCSR_SSI_SCR_TCH_EN);
675 if (fmt & SND_SOC_DAIFMT_AC97)
676 fsl_ssi_setup_ac97(ssi_private);
682 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
684 * Note: This function can be only called when using SSI as DAI master
686 * Quick instruction for parameters:
687 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
688 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
690 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
691 int clk_id, unsigned int freq, int dir)
693 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
694 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
695 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
696 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
697 unsigned long flags, clkrate, baudrate, tmprate;
698 u64 sub, savesub = 100000;
700 /* Don't apply it to any non-baudclk circumstance */
701 if (IS_ERR(ssi_private->baudclk))
704 /* It should be already enough to divide clock by setting pm alone */
708 factor = (div2 + 1) * (7 * psr + 1) * 2;
710 for (i = 0; i < 255; i++) {
711 /* The bclk rate must be smaller than 1/5 sysclk rate */
712 if (factor * (i + 1) < 5)
715 tmprate = freq * factor * (i + 2);
716 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
718 do_div(clkrate, factor);
719 afreq = (u32)clkrate / (i + 1);
723 else if (freq / afreq == 1)
725 else if (afreq / freq == 1)
730 /* Calculate the fraction */
745 /* No proper pm found if it is still remaining the initial value */
747 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
751 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
752 (psr ? CCSR_SSI_SxCCR_PSR : 0);
753 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
755 if (dir == SND_SOC_CLOCK_OUT || synchronous)
756 write_ssi_mask(&ssi->stccr, mask, stccr);
758 write_ssi_mask(&ssi->srccr, mask, stccr);
760 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
761 if (!ssi_private->baudclk_locked) {
762 ret = clk_set_rate(ssi_private->baudclk, baudrate);
764 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
765 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
768 ssi_private->baudclk_locked = true;
770 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
776 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
778 * Note: This function can be only called when using SSI as DAI master
780 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
781 u32 rx_mask, int slots, int slot_width)
783 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
784 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
787 /* The slot number should be >= 2 if using Network mode or I2S mode */
788 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
789 if (val && slots < 2) {
790 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
794 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
795 CCSR_SSI_SxCCR_DC(slots));
796 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
797 CCSR_SSI_SxCCR_DC(slots));
799 /* The register SxMSKs needs SSI to provide essential clock due to
800 * hardware design. So we here temporarily enable SSI to set them.
802 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
803 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
805 write_ssi(tx_mask, &ssi->stmsk);
806 write_ssi(rx_mask, &ssi->srmsk);
808 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
814 * fsl_ssi_trigger: start and stop the DMA transfer.
816 * This function is called by ALSA to start, stop, pause, and resume the DMA
819 * The DMA channel is in external master start and pause mode, which
820 * means the SSI completely controls the flow of data.
822 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
823 struct snd_soc_dai *dai)
825 struct snd_soc_pcm_runtime *rtd = substream->private_data;
826 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
827 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
831 case SNDRV_PCM_TRIGGER_START:
832 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
833 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
834 fsl_ssi_tx_config(ssi_private, true);
836 fsl_ssi_rx_config(ssi_private, true);
839 case SNDRV_PCM_TRIGGER_STOP:
840 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
841 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
842 fsl_ssi_tx_config(ssi_private, false);
844 fsl_ssi_rx_config(ssi_private, false);
846 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
847 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
848 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
849 ssi_private->baudclk_locked = false;
850 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
858 if (ssi_private->imx_ac97) {
859 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
860 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
862 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
868 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
870 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
872 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
873 dai->playback_dma_data = &ssi_private->dma_params_tx;
874 dai->capture_dma_data = &ssi_private->dma_params_rx;
880 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
881 .startup = fsl_ssi_startup,
882 .hw_params = fsl_ssi_hw_params,
883 .set_fmt = fsl_ssi_set_dai_fmt,
884 .set_sysclk = fsl_ssi_set_dai_sysclk,
885 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
886 .trigger = fsl_ssi_trigger,
889 /* Template for the CPU dai driver structure */
890 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
891 .probe = fsl_ssi_dai_probe,
895 .rates = FSLSSI_I2S_RATES,
896 .formats = FSLSSI_I2S_FORMATS,
901 .rates = FSLSSI_I2S_RATES,
902 .formats = FSLSSI_I2S_FORMATS,
904 .ops = &fsl_ssi_dai_ops,
907 static const struct snd_soc_component_driver fsl_ssi_component = {
911 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
914 .stream_name = "AC97 Playback",
917 .rates = SNDRV_PCM_RATE_8000_48000,
918 .formats = SNDRV_PCM_FMTBIT_S16_LE,
921 .stream_name = "AC97 Capture",
924 .rates = SNDRV_PCM_RATE_48000,
925 .formats = SNDRV_PCM_FMTBIT_S16_LE,
927 .ops = &fsl_ssi_dai_ops,
931 static struct fsl_ssi_private *fsl_ac97_data;
933 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
936 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
945 write_ssi(lreg, &ssi->sacadd);
948 write_ssi(lval , &ssi->sacdat);
950 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
955 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
958 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
960 unsigned short val = -1;
963 lreg = (reg & 0x7f) << 12;
964 write_ssi(lreg, &ssi->sacadd);
965 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
970 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
975 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
976 .read = fsl_ssi_ac97_read,
977 .write = fsl_ssi_ac97_write,
981 * Make every character in a string lower-case
983 static void make_lowercase(char *s)
989 if ((c >= 'A') && (c <= 'Z'))
990 *p = c + ('a' - 'A');
995 static int fsl_ssi_probe(struct platform_device *pdev)
997 struct fsl_ssi_private *ssi_private;
999 struct device_attribute *dev_attr = NULL;
1000 struct device_node *np = pdev->dev.of_node;
1001 const struct of_device_id *of_id;
1002 enum fsl_ssi_type hw_type;
1003 const char *p, *sprop;
1004 const uint32_t *iprop;
1005 struct resource res;
1010 /* SSIs that are not connected on the board should have a
1011 * status = "disabled"
1012 * property in their device tree nodes.
1014 if (!of_device_is_available(np))
1017 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1020 hw_type = (enum fsl_ssi_type) of_id->data;
1022 sprop = of_get_property(np, "fsl,mode", NULL);
1024 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1027 if (!strcmp(sprop, "ac97-slave"))
1030 /* The DAI name is the last part of the full name of the node. */
1031 p = strrchr(np->full_name, '/') + 1;
1032 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1035 dev_err(&pdev->dev, "could not allocate DAI object\n");
1039 strcpy(ssi_private->name, p);
1041 ssi_private->use_dma = !of_property_read_bool(np,
1042 "fsl,fiq-stream-filter");
1043 ssi_private->hw_type = hw_type;
1046 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1047 sizeof(fsl_ssi_ac97_dai));
1049 fsl_ac97_data = ssi_private;
1050 ssi_private->imx_ac97 = true;
1052 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1054 /* Initialize this copy of the CPU DAI driver structure */
1055 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1056 sizeof(fsl_ssi_dai_template));
1058 ssi_private->cpu_dai_drv.name = ssi_private->name;
1060 /* Get the addresses and IRQ */
1061 ret = of_address_to_resource(np, 0, &res);
1063 dev_err(&pdev->dev, "could not determine device resources\n");
1066 ssi_private->ssi = of_iomap(np, 0);
1067 if (!ssi_private->ssi) {
1068 dev_err(&pdev->dev, "could not map device resources\n");
1071 ssi_private->ssi_phys = res.start;
1073 ssi_private->irq = irq_of_parse_and_map(np, 0);
1074 if (!ssi_private->irq) {
1075 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1079 /* Are the RX and the TX clocks locked? */
1080 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1081 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1082 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1083 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1086 /* Determine the FIFO depth. */
1087 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1089 ssi_private->fifo_depth = be32_to_cpup(iprop);
1091 /* Older 8610 DTs didn't have the fifo-depth property */
1092 ssi_private->fifo_depth = 8;
1094 ssi_private->baudclk_locked = false;
1095 spin_lock_init(&ssi_private->baudclk_lock);
1098 * imx51 and later SoCs have a slightly different IP that allows the
1099 * SSI configuration while the SSI unit is running.
1101 * More important, it is necessary on those SoCs to configure the
1102 * sperate TX/RX DMA bits just before starting the stream
1103 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1104 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1105 * how the SDMA unit handles the DMA request.
1107 * SDMA units are present on devices starting at imx35 but the imx35
1108 * reference manual states that the DMA bits should not be changed
1109 * while the SSI unit is running (SSIEN). So we support the necessary
1110 * online configuration of fsl-ssi starting at imx51.
1113 case FSL_SSI_MCP8610:
1116 ssi_private->offline_config = true;
1119 ssi_private->offline_config = false;
1123 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1124 hw_type == FSL_SSI_MX35) {
1125 u32 dma_events[2], dmas[4];
1126 ssi_private->ssi_on_imx = true;
1128 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1129 if (IS_ERR(ssi_private->clk)) {
1130 ret = PTR_ERR(ssi_private->clk);
1131 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1134 ret = clk_prepare_enable(ssi_private->clk);
1136 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1141 /* For those SLAVE implementations, we ingore non-baudclk cases
1142 * and, instead, abandon MASTER mode that needs baud clock.
1144 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1145 if (IS_ERR(ssi_private->baudclk))
1146 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1147 PTR_ERR(ssi_private->baudclk));
1149 clk_prepare_enable(ssi_private->baudclk);
1152 * We have burstsize be "fifo_depth - 2" to match the SSI
1153 * watermark setting in fsl_ssi_startup().
1155 ssi_private->dma_params_tx.maxburst =
1156 ssi_private->fifo_depth - 2;
1157 ssi_private->dma_params_rx.maxburst =
1158 ssi_private->fifo_depth - 2;
1159 ssi_private->dma_params_tx.addr =
1160 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1161 ssi_private->dma_params_rx.addr =
1162 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1163 ssi_private->dma_params_tx.filter_data =
1164 &ssi_private->filter_data_tx;
1165 ssi_private->dma_params_rx.filter_data =
1166 &ssi_private->filter_data_rx;
1167 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1168 ssi_private->use_dma) {
1170 * FIXME: This is a temporary solution until all
1171 * necessary dma drivers support the generic dma
1174 ret = of_property_read_u32_array(pdev->dev.of_node,
1175 "fsl,ssi-dma-events", dma_events, 2);
1176 if (ret && ssi_private->use_dma) {
1177 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1181 /* Should this be merge with the above? */
1182 if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
1183 && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1184 ssi_private->use_dual_fifo = true;
1185 /* When using dual fifo mode, we need to keep watermark
1186 * as even numbers due to dma script limitation.
1188 ssi_private->dma_params_tx.maxburst &= ~0x1;
1189 ssi_private->dma_params_rx.maxburst &= ~0x1;
1192 shared = of_device_is_compatible(of_get_parent(np),
1195 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1196 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1197 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1198 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1202 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1203 * different writeable interrupt status registers.
1205 if (ssi_private->use_dma) {
1206 /* The 'name' should not have any slashes in it. */
1207 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1208 fsl_ssi_isr, 0, ssi_private->name,
1210 ssi_private->irq_stats = true;
1212 dev_err(&pdev->dev, "could not claim irq %u\n",
1218 /* Register with ASoC */
1219 dev_set_drvdata(&pdev->dev, ssi_private);
1221 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1222 &ssi_private->cpu_dai_drv, 1);
1224 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1228 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1232 if (ssi_private->ssi_on_imx) {
1233 if (!ssi_private->use_dma) {
1236 * Some boards use an incompatible codec. To get it
1237 * working, we are using imx-fiq-pcm-audio, that
1238 * can handle those codecs. DMA is not possible in this
1242 ssi_private->fiq_params.irq = ssi_private->irq;
1243 ssi_private->fiq_params.base = ssi_private->ssi;
1244 ssi_private->fiq_params.dma_params_rx =
1245 &ssi_private->dma_params_rx;
1246 ssi_private->fiq_params.dma_params_tx =
1247 &ssi_private->dma_params_tx;
1249 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1253 ret = imx_pcm_dma_init(pdev);
1260 * If codec-handle property is missing from SSI node, we assume
1261 * that the machine driver uses new binding which does not require
1262 * SSI driver to trigger machine driver's probe.
1264 if (!of_get_property(np, "codec-handle", NULL)) {
1265 ssi_private->new_binding = true;
1269 /* Trigger the machine driver's probe function. The platform driver
1270 * name of the machine driver is taken from /compatible property of the
1271 * device tree. We also pass the address of the CPU DAI driver
1274 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1275 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1276 p = strrchr(sprop, ',');
1279 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1280 make_lowercase(name);
1283 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1284 if (IS_ERR(ssi_private->pdev)) {
1285 ret = PTR_ERR(ssi_private->pdev);
1286 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1294 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1295 imx_pcm_fiq_exit(pdev);
1298 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1301 snd_soc_unregister_component(&pdev->dev);
1304 device_remove_file(&pdev->dev, dev_attr);
1307 if (ssi_private->ssi_on_imx) {
1308 if (!IS_ERR(ssi_private->baudclk))
1309 clk_disable_unprepare(ssi_private->baudclk);
1310 clk_disable_unprepare(ssi_private->clk);
1314 if (ssi_private->irq_stats)
1315 irq_dispose_mapping(ssi_private->irq);
1320 static int fsl_ssi_remove(struct platform_device *pdev)
1322 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1324 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1326 if (!ssi_private->new_binding)
1327 platform_device_unregister(ssi_private->pdev);
1328 snd_soc_unregister_component(&pdev->dev);
1329 if (ssi_private->ssi_on_imx) {
1330 if (!IS_ERR(ssi_private->baudclk))
1331 clk_disable_unprepare(ssi_private->baudclk);
1332 clk_disable_unprepare(ssi_private->clk);
1334 if (ssi_private->irq_stats)
1335 irq_dispose_mapping(ssi_private->irq);
1340 static struct platform_driver fsl_ssi_driver = {
1342 .name = "fsl-ssi-dai",
1343 .owner = THIS_MODULE,
1344 .of_match_table = fsl_ssi_ids,
1346 .probe = fsl_ssi_probe,
1347 .remove = fsl_ssi_remove,
1350 module_platform_driver(fsl_ssi_driver);
1352 MODULE_ALIAS("platform:fsl-ssi-dai");
1353 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1354 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1355 MODULE_LICENSE("GPL v2");