2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/platform_device.h>
28 #include <sound/pcm.h>
32 * initialize the PCI registers
34 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
35 unsigned char mask, unsigned char val)
39 pci_read_config_byte(pci, reg, &data);
42 pci_write_config_byte(pci, reg, data);
45 static void skl_init_pci(struct skl *skl)
47 struct hdac_ext_bus *ebus = &skl->ebus;
50 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
51 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
52 * Ensuring these bits are 0 clears playback static on some HD Audio
54 * The PCI register TCSEL is defined in the Intel manuals.
56 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
57 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
61 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
63 snd_pcm_period_elapsed(hstr->substream);
66 static irqreturn_t skl_interrupt(int irq, void *dev_id)
68 struct hdac_ext_bus *ebus = dev_id;
69 struct hdac_bus *bus = ebus_to_hbus(ebus);
72 if (!pm_runtime_active(bus->dev))
75 spin_lock(&bus->reg_lock);
77 status = snd_hdac_chip_readl(bus, INTSTS);
78 if (status == 0 || status == 0xffffffff) {
79 spin_unlock(&bus->reg_lock);
84 status = snd_hdac_chip_readb(bus, RIRBSTS);
85 if (status & RIRB_INT_MASK) {
86 if (status & RIRB_INT_RESPONSE)
87 snd_hdac_bus_update_rirb(bus);
88 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
91 spin_unlock(&bus->reg_lock);
93 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
96 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
98 struct hdac_ext_bus *ebus = dev_id;
99 struct hdac_bus *bus = ebus_to_hbus(ebus);
102 status = snd_hdac_chip_readl(bus, INTSTS);
104 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
109 static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
111 struct skl *skl = ebus_to_skl(ebus);
112 struct hdac_bus *bus = ebus_to_hbus(ebus);
115 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
116 skl_threaded_handler,
118 KBUILD_MODNAME, ebus);
121 "unable to grab IRQ %d, disabling device\n",
126 bus->irq = skl->pci->irq;
127 pci_intx(skl->pci, 1);
132 #ifdef CONFIG_PM_SLEEP
136 static int skl_suspend(struct device *dev)
138 struct pci_dev *pci = to_pci_dev(dev);
139 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
140 struct hdac_bus *bus = ebus_to_hbus(ebus);
142 snd_hdac_bus_stop_chip(bus);
143 snd_hdac_bus_enter_link_reset(bus);
148 static int skl_resume(struct device *dev)
150 struct pci_dev *pci = to_pci_dev(dev);
151 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
152 struct hdac_bus *bus = ebus_to_hbus(ebus);
153 struct skl *hda = ebus_to_skl(ebus);
157 snd_hdac_bus_init_chip(bus, 1);
161 #endif /* CONFIG_PM_SLEEP */
164 static int skl_runtime_suspend(struct device *dev)
166 struct pci_dev *pci = to_pci_dev(dev);
167 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
168 struct hdac_bus *bus = ebus_to_hbus(ebus);
170 dev_dbg(bus->dev, "in %s\n", __func__);
172 /* enable controller wake up event */
173 snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK);
175 snd_hdac_bus_stop_chip(bus);
176 snd_hdac_bus_enter_link_reset(bus);
181 static int skl_runtime_resume(struct device *dev)
183 struct pci_dev *pci = to_pci_dev(dev);
184 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
185 struct hdac_bus *bus = ebus_to_hbus(ebus);
186 struct skl *hda = ebus_to_skl(ebus);
189 dev_dbg(bus->dev, "in %s\n", __func__);
191 /* Read STATESTS before controller reset */
192 status = snd_hdac_chip_readw(bus, STATESTS);
195 snd_hdac_bus_init_chip(bus, true);
196 /* disable controller Wake Up event */
197 snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0);
201 #endif /* CONFIG_PM */
203 static const struct dev_pm_ops skl_pm = {
204 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
205 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
211 static int skl_free(struct hdac_ext_bus *ebus)
213 struct skl *skl = ebus_to_skl(ebus);
214 struct hdac_bus *bus = ebus_to_hbus(ebus);
216 skl->init_failed = 1; /* to be sure */
218 snd_hdac_ext_stop_streams(ebus);
221 free_irq(bus->irq, (void *)bus);
223 iounmap(bus->remap_addr);
225 snd_hdac_bus_free_stream_pages(bus);
226 snd_hdac_stream_free_all(ebus);
227 snd_hdac_link_free_all(ebus);
228 pci_release_regions(skl->pci);
229 pci_disable_device(skl->pci);
231 snd_hdac_ext_bus_exit(ebus);
236 static int skl_dmic_device_register(struct skl *skl)
238 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
239 struct platform_device *pdev;
242 /* SKL has one dmic port, so allocate dmic device for this */
243 pdev = platform_device_alloc("dmic-codec", -1);
245 dev_err(bus->dev, "failed to allocate dmic device\n");
249 ret = platform_device_add(pdev);
251 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
252 platform_device_put(pdev);
255 skl->dmic_dev = pdev;
260 static void skl_dmic_device_unregister(struct skl *skl)
263 platform_device_unregister(skl->dmic_dev);
267 * Probe the given codec address
269 static int probe_codec(struct hdac_ext_bus *ebus, int addr)
271 struct hdac_bus *bus = ebus_to_hbus(ebus);
272 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
273 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
276 mutex_lock(&bus->cmd_mutex);
277 snd_hdac_bus_send_cmd(bus, cmd);
278 snd_hdac_bus_get_response(bus, addr, &res);
279 mutex_unlock(&bus->cmd_mutex);
282 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
284 return snd_hdac_ext_bus_device_init(ebus, addr);
287 /* Codec initialization */
288 static int skl_codec_create(struct hdac_ext_bus *ebus)
290 struct hdac_bus *bus = ebus_to_hbus(ebus);
293 max_slots = HDA_MAX_CODECS;
295 /* First try to probe all given codec slots */
296 for (c = 0; c < max_slots; c++) {
297 if ((bus->codec_mask & (1 << c))) {
298 if (probe_codec(ebus, c) < 0) {
300 * Some BIOSen give you wrong codec addresses
304 "Codec #%d probe error; disabling it...\n", c);
305 bus->codec_mask &= ~(1 << c);
307 * More badly, accessing to a non-existing
308 * codec often screws up the controller bus,
309 * and disturbs the further communications.
310 * Thus if an error occurs during probing,
311 * better to reset the controller bus to get
312 * back to the sanity state.
314 snd_hdac_bus_stop_chip(bus);
315 snd_hdac_bus_init_chip(bus, true);
323 static const struct hdac_bus_ops bus_core_ops = {
324 .command = snd_hdac_bus_send_cmd,
325 .get_response = snd_hdac_bus_get_response,
331 static int skl_create(struct pci_dev *pci,
332 const struct hdac_io_ops *io_ops,
336 struct hdac_ext_bus *ebus;
342 err = pci_enable_device(pci);
346 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
348 pci_disable_device(pci);
352 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
353 ebus->bus.use_posbuf = 1;
356 ebus->bus.bdl_pos_adj = 0;
363 static int skl_first_init(struct hdac_ext_bus *ebus)
365 struct skl *skl = ebus_to_skl(ebus);
366 struct hdac_bus *bus = ebus_to_hbus(ebus);
367 struct pci_dev *pci = skl->pci;
370 int cp_streams, pb_streams, start_idx;
372 err = pci_request_regions(pci, "Skylake HD audio");
376 bus->addr = pci_resource_start(pci, 0);
377 bus->remap_addr = pci_ioremap_bar(pci, 0);
378 if (bus->remap_addr == NULL) {
379 dev_err(bus->dev, "ioremap error\n");
383 snd_hdac_ext_bus_parse_capabilities(ebus);
385 if (skl_acquire_irq(ebus, 0) < 0)
389 synchronize_irq(bus->irq);
391 gcap = snd_hdac_chip_readw(bus, GCAP);
392 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
394 /* allow 64bit DMA address if supported by H/W */
395 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
396 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
398 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
399 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
402 /* read number of streams from GCAP register */
403 cp_streams = (gcap >> 8) & 0x0f;
404 pb_streams = (gcap >> 12) & 0x0f;
406 if (!pb_streams && !cp_streams)
409 ebus->num_streams = cp_streams + pb_streams;
411 /* initialize streams */
412 snd_hdac_ext_stream_init_all
413 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
414 start_idx = cp_streams;
415 snd_hdac_ext_stream_init_all
416 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
418 err = snd_hdac_bus_alloc_stream_pages(bus);
422 /* initialize chip */
425 snd_hdac_bus_init_chip(bus, true);
427 /* codec detection */
428 if (!bus->codec_mask) {
429 dev_err(bus->dev, "no codecs found!\n");
436 static int skl_probe(struct pci_dev *pci,
437 const struct pci_device_id *pci_id)
440 struct hdac_ext_bus *ebus = NULL;
441 struct hdac_bus *bus = NULL;
444 /* we use ext core ops, so provide NULL for ops here */
445 err = skl_create(pci, NULL, &skl);
450 bus = ebus_to_hbus(ebus);
452 err = skl_first_init(ebus);
456 pci_set_drvdata(skl->pci, ebus);
458 /* check if dsp is there */
460 /* TODO register with dsp IPC */
461 dev_dbg(bus->dev, "Register dsp\n");
465 snd_hdac_ext_bus_get_ml_capabilities(ebus);
467 /* create device for soc dmic */
468 err = skl_dmic_device_register(skl);
472 /* register platform dai and controls */
473 err = skl_platform_register(bus->dev);
477 /* create codec instances */
478 err = skl_codec_create(ebus);
483 pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
484 pm_runtime_use_autosuspend(bus->dev);
485 pm_runtime_put_noidle(bus->dev);
486 pm_runtime_allow(bus->dev);
491 skl_platform_unregister(bus->dev);
493 skl_dmic_device_unregister(skl);
495 skl->init_failed = 1;
501 static void skl_remove(struct pci_dev *pci)
503 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
504 struct skl *skl = ebus_to_skl(ebus);
506 if (pci_dev_run_wake(pci))
507 pm_runtime_get_noresume(&pci->dev);
509 skl_platform_unregister(&pci->dev);
510 skl_dmic_device_unregister(skl);
512 dev_set_drvdata(&pci->dev, NULL);
516 static const struct pci_device_id skl_ids[] = {
517 /* Sunrise Point-LP */
518 { PCI_DEVICE(0x8086, 0x9d70), 0},
521 MODULE_DEVICE_TABLE(pci, skl_ids);
523 /* pci_driver definition */
524 static struct pci_driver skl_driver = {
525 .name = KBUILD_MODNAME,
528 .remove = skl_remove,
533 module_pci_driver(skl_driver);
535 MODULE_LICENSE("GPL v2");
536 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");