2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/time.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <asm/mach-types.h>
37 #define MXS_SET_ADDR 0x4
38 #define MXS_CLR_ADDR 0x8
40 static struct mxs_saif *mxs_saif[2];
43 * SAIF is a little different with other normal SOC DAIs on clock using.
45 * For MXS, two SAIF modules are instantiated on-chip.
46 * Each SAIF has a set of clock pins and can be operating in master
47 * mode simultaneously if they are connected to different off-chip codecs.
48 * Also, one of the two SAIFs can master or drive the clock pins while the
49 * other SAIF, in slave mode, receives clocking from the master SAIF.
50 * This also means that both SAIFs must operate at the same sample rate.
52 * We abstract this as each saif has a master, the master could be
53 * himself or other saifs. In the generic saif driver, saif does not need
54 * to know the different clkmux. Saif only needs to know who is his master
55 * and operating his master to generate the proper clock rate for him.
56 * The master id is provided in mach-specific layer according to different
60 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
61 int clk_id, unsigned int freq, int dir)
63 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
76 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
77 * is provided by other SAIF, we provide a interface here to get its master
79 * Note that the master could be himself.
81 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
83 return mxs_saif[saif->master_id];
87 * Set SAIF clock and MCLK
89 static int mxs_saif_set_clk(struct mxs_saif *saif,
95 struct mxs_saif *master_saif;
97 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
99 /* Set master saif to generate proper clock */
100 master_saif = mxs_saif_get_master(saif);
104 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
106 /* Checking if can playback and capture simutaneously */
107 if (master_saif->ongoing && rate != master_saif->cur_rate) {
109 "can not change clock, master saif%d(rate %d) is ongoing\n",
110 master_saif->id, master_saif->cur_rate);
114 scr = __raw_readl(master_saif->base + SAIF_CTRL);
115 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
116 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
121 * The SAIF clock should be either 384*fs or 512*fs.
122 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
123 * For 32x mclk, set saif clk as 512*fs.
124 * For 48x mclk, set saif clk as 384*fs.
126 * If MCLK is not used, we just set saif clk to 512*fs.
128 clk_prepare_enable(master_saif->clk);
130 if (master_saif->mclk_in_use) {
131 if (mclk % 32 == 0) {
132 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
133 ret = clk_set_rate(master_saif->clk, 512 * rate);
134 } else if (mclk % 48 == 0) {
135 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
136 ret = clk_set_rate(master_saif->clk, 384 * rate);
138 /* SAIF MCLK should be either 32x or 48x */
139 clk_disable_unprepare(master_saif->clk);
143 ret = clk_set_rate(master_saif->clk, 512 * rate);
144 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
147 clk_disable_unprepare(master_saif->clk);
152 master_saif->cur_rate = rate;
154 if (!master_saif->mclk_in_use) {
155 __raw_writel(scr, master_saif->base + SAIF_CTRL);
160 * Program the over-sample rate for MCLK output
162 * The available MCLK range is 32x, 48x... 512x. The rate
163 * could be from 8kHz to 192kH.
165 switch (mclk / rate) {
167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
173 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
176 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
188 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
191 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
197 __raw_writel(scr, master_saif->base + SAIF_CTRL);
203 * Put and disable MCLK.
205 int mxs_saif_put_mclk(unsigned int saif_id)
207 struct mxs_saif *saif = mxs_saif[saif_id];
213 stat = __raw_readl(saif->base + SAIF_STAT);
214 if (stat & BM_SAIF_STAT_BUSY) {
215 dev_err(saif->dev, "error: busy\n");
219 clk_disable_unprepare(saif->clk);
221 /* disable MCLK output */
222 __raw_writel(BM_SAIF_CTRL_CLKGATE,
223 saif->base + SAIF_CTRL + MXS_SET_ADDR);
224 __raw_writel(BM_SAIF_CTRL_RUN,
225 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
227 saif->mclk_in_use = 0;
230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
233 * Get MCLK and set clock rate, then enable it
235 * This interface is used for codecs who are using MCLK provided
238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
241 struct mxs_saif *saif = mxs_saif[saif_id];
244 struct mxs_saif *master_saif;
250 __raw_writel(BM_SAIF_CTRL_SFTRST,
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
253 /* FIXME: need clear clk gate for register r/w */
254 __raw_writel(BM_SAIF_CTRL_CLKGATE,
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
257 master_saif = mxs_saif_get_master(saif);
258 if (saif != master_saif) {
259 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
263 stat = __raw_readl(saif->base + SAIF_STAT);
264 if (stat & BM_SAIF_STAT_BUSY) {
265 dev_err(saif->dev, "error: busy\n");
269 saif->mclk_in_use = 1;
270 ret = mxs_saif_set_clk(saif, mclk, rate);
274 ret = clk_prepare_enable(saif->clk);
278 /* enable MCLK output */
279 __raw_writel(BM_SAIF_CTRL_RUN,
280 saif->base + SAIF_CTRL + MXS_SET_ADDR);
284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
287 * SAIF DAI format configuration.
288 * Should only be called when port is inactive.
290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
296 stat = __raw_readl(saif->base + SAIF_STAT);
297 if (stat & BM_SAIF_STAT_BUSY) {
298 dev_err(cpu_dai->dev, "error: busy\n");
302 scr0 = __raw_readl(saif->base + SAIF_CTRL);
303 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
304 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
309 case SND_SOC_DAIFMT_I2S:
310 /* data frame low 1clk before data */
311 scr |= BM_SAIF_CTRL_DELAY;
312 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
314 case SND_SOC_DAIFMT_LEFT_J:
315 /* data frame high with data */
316 scr &= ~BM_SAIF_CTRL_DELAY;
317 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
318 scr &= ~BM_SAIF_CTRL_JUSTIFY;
324 /* DAI clock inversion */
325 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
326 case SND_SOC_DAIFMT_IB_IF:
327 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
328 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
330 case SND_SOC_DAIFMT_IB_NF:
331 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
334 case SND_SOC_DAIFMT_NB_IF:
335 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
336 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
338 case SND_SOC_DAIFMT_NB_NF:
339 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
340 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
345 * Note: We simply just support master mode since SAIF TX can only
347 * Here the master is relative to codec side.
348 * Saif internally could be slave when working on EXTMASTER mode.
349 * We just hide this to machine driver.
351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
352 case SND_SOC_DAIFMT_CBS_CFS:
353 if (saif->id == saif->master_id)
354 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
356 scr |= BM_SAIF_CTRL_SLAVE_MODE;
358 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
367 static int mxs_saif_startup(struct snd_pcm_substream *substream,
368 struct snd_soc_dai *cpu_dai)
370 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
372 /* clear error status to 0 for each re-open */
373 saif->fifo_underrun = 0;
374 saif->fifo_overrun = 0;
376 /* Clear Reset for normal operations */
377 __raw_writel(BM_SAIF_CTRL_SFTRST,
378 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
380 /* clear clock gate */
381 __raw_writel(BM_SAIF_CTRL_CLKGATE,
382 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
388 * Should only be called when port is inactive.
389 * although can be called multiple times by upper layers.
391 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
392 struct snd_pcm_hw_params *params,
393 struct snd_soc_dai *cpu_dai)
395 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
396 struct mxs_saif *master_saif;
400 master_saif = mxs_saif_get_master(saif);
404 /* mclk should already be set */
405 if (!saif->mclk && saif->mclk_in_use) {
406 dev_err(cpu_dai->dev, "set mclk first\n");
410 stat = __raw_readl(saif->base + SAIF_STAT);
411 if (stat & BM_SAIF_STAT_BUSY) {
412 dev_err(cpu_dai->dev, "error: busy\n");
417 * Set saif clk based on sample rate.
418 * If mclk is used, we also set mclk, if not, saif->mclk is
419 * default 0, means not used.
421 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
423 dev_err(cpu_dai->dev, "unable to get proper clk\n");
427 /* prepare clk in hw_param, enable in trigger */
428 clk_prepare(saif->clk);
429 if (saif != master_saif) {
431 * Set an initial clock rate for the saif internal logic to work
432 * properly. This is important when working in EXTMASTER mode
433 * that uses the other saif's BITCLK&LRCLK but it still needs a
434 * basic clock which should be fast enough for the internal
437 clk_enable(saif->clk);
438 ret = clk_set_rate(saif->clk, 24000000);
439 clk_disable(saif->clk);
443 clk_prepare(master_saif->clk);
446 scr = __raw_readl(saif->base + SAIF_CTRL);
448 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
449 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
450 switch (params_format(params)) {
451 case SNDRV_PCM_FORMAT_S16_LE:
452 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
454 case SNDRV_PCM_FORMAT_S20_3LE:
455 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
456 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
458 case SNDRV_PCM_FORMAT_S24_LE:
459 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
460 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
469 scr &= ~BM_SAIF_CTRL_READ_MODE;
472 scr |= BM_SAIF_CTRL_READ_MODE;
475 __raw_writel(scr, saif->base + SAIF_CTRL);
479 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
480 struct snd_soc_dai *cpu_dai)
482 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
484 /* enable FIFO error irqs */
485 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
486 saif->base + SAIF_CTRL + MXS_SET_ADDR);
491 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
492 struct snd_soc_dai *cpu_dai)
494 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
495 struct mxs_saif *master_saif;
498 master_saif = mxs_saif_get_master(saif);
503 case SNDRV_PCM_TRIGGER_START:
504 case SNDRV_PCM_TRIGGER_RESUME:
505 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
506 dev_dbg(cpu_dai->dev, "start\n");
508 clk_enable(master_saif->clk);
509 if (!master_saif->mclk_in_use)
510 __raw_writel(BM_SAIF_CTRL_RUN,
511 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
514 * If the saif's master is not himself, we also need to enable
515 * itself clk for its internal basic logic to work.
517 if (saif != master_saif) {
518 clk_enable(saif->clk);
519 __raw_writel(BM_SAIF_CTRL_RUN,
520 saif->base + SAIF_CTRL + MXS_SET_ADDR);
523 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
525 * write data to saif data register to trigger
527 * For 24-bit format the 32-bit FIFO register stores
528 * only one channel, so we need to write twice.
529 * This is also safe for the other non 24-bit formats.
531 __raw_writel(0, saif->base + SAIF_DATA);
532 __raw_writel(0, saif->base + SAIF_DATA);
535 * read data from saif data register to trigger
537 * For 24-bit format the 32-bit FIFO register stores
538 * only one channel, so we need to read twice.
539 * This is also safe for the other non 24-bit formats.
541 __raw_readl(saif->base + SAIF_DATA);
542 __raw_readl(saif->base + SAIF_DATA);
545 master_saif->ongoing = 1;
547 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
548 __raw_readl(saif->base + SAIF_CTRL),
549 __raw_readl(saif->base + SAIF_STAT));
551 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
552 __raw_readl(master_saif->base + SAIF_CTRL),
553 __raw_readl(master_saif->base + SAIF_STAT));
555 case SNDRV_PCM_TRIGGER_SUSPEND:
556 case SNDRV_PCM_TRIGGER_STOP:
557 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
558 dev_dbg(cpu_dai->dev, "stop\n");
560 /* wait a while for the current sample to complete */
561 delay = USEC_PER_SEC / master_saif->cur_rate;
563 if (!master_saif->mclk_in_use) {
564 __raw_writel(BM_SAIF_CTRL_RUN,
565 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
568 clk_disable(master_saif->clk);
570 if (saif != master_saif) {
571 __raw_writel(BM_SAIF_CTRL_RUN,
572 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
574 clk_disable(saif->clk);
577 master_saif->ongoing = 0;
587 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
588 #define MXS_SAIF_FORMATS \
589 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
590 SNDRV_PCM_FMTBIT_S24_LE)
592 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
593 .startup = mxs_saif_startup,
594 .trigger = mxs_saif_trigger,
595 .prepare = mxs_saif_prepare,
596 .hw_params = mxs_saif_hw_params,
597 .set_sysclk = mxs_saif_set_dai_sysclk,
598 .set_fmt = mxs_saif_set_dai_fmt,
601 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
603 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
605 snd_soc_dai_set_drvdata(dai, saif);
610 static struct snd_soc_dai_driver mxs_saif_dai = {
612 .probe = mxs_saif_dai_probe,
616 .rates = MXS_SAIF_RATES,
617 .formats = MXS_SAIF_FORMATS,
622 .rates = MXS_SAIF_RATES,
623 .formats = MXS_SAIF_FORMATS,
625 .ops = &mxs_saif_dai_ops,
628 static const struct snd_soc_component_driver mxs_saif_component = {
632 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
634 struct mxs_saif *saif = dev_id;
637 stat = __raw_readl(saif->base + SAIF_STAT);
638 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
639 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
642 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
643 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
644 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
645 saif->base + SAIF_STAT + MXS_CLR_ADDR);
648 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
649 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
650 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
651 saif->base + SAIF_STAT + MXS_CLR_ADDR);
654 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
655 __raw_readl(saif->base + SAIF_CTRL),
656 __raw_readl(saif->base + SAIF_STAT));
661 static int mxs_saif_probe(struct platform_device *pdev)
663 struct device_node *np = pdev->dev.of_node;
664 struct resource *iores;
665 struct mxs_saif *saif;
667 struct device_node *master;
672 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
676 ret = of_alias_get_id(np, "saif");
683 * If there is no "fsl,saif-master" phandle, it's a saif
684 * master. Otherwise, it's a slave and its phandle points
687 master = of_parse_phandle(np, "fsl,saif-master", 0);
689 saif->master_id = saif->id;
691 ret = of_alias_get_id(master, "saif");
695 saif->master_id = ret;
698 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
699 dev_err(&pdev->dev, "get wrong master id\n");
703 mxs_saif[saif->id] = saif;
705 saif->clk = devm_clk_get(&pdev->dev, NULL);
706 if (IS_ERR(saif->clk)) {
707 ret = PTR_ERR(saif->clk);
708 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
713 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 saif->base = devm_ioremap_resource(&pdev->dev, iores);
716 if (IS_ERR(saif->base))
717 return PTR_ERR(saif->base);
719 saif->irq = platform_get_irq(pdev, 0);
722 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
727 saif->dev = &pdev->dev;
728 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0,
731 dev_err(&pdev->dev, "failed to request irq\n");
735 platform_set_drvdata(pdev, saif);
737 ret = snd_soc_register_component(&pdev->dev, &mxs_saif_component,
740 dev_err(&pdev->dev, "register DAI failed\n");
744 ret = mxs_pcm_platform_register(&pdev->dev);
746 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
747 goto failed_pdev_alloc;
753 snd_soc_unregister_component(&pdev->dev);
758 static int mxs_saif_remove(struct platform_device *pdev)
760 mxs_pcm_platform_unregister(&pdev->dev);
761 snd_soc_unregister_component(&pdev->dev);
766 static const struct of_device_id mxs_saif_dt_ids[] = {
767 { .compatible = "fsl,imx28-saif", },
770 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
772 static struct platform_driver mxs_saif_driver = {
773 .probe = mxs_saif_probe,
774 .remove = mxs_saif_remove,
778 .owner = THIS_MODULE,
779 .of_match_table = mxs_saif_dt_ids,
783 module_platform_driver(mxs_saif_driver);
785 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
786 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
787 MODULE_LICENSE("GPL");
788 MODULE_ALIAS("platform:mxs-saif");