sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/control.h>
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  43         xhandler_get, xhandler_put) \
  44 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  45         .info = omap_mcbsp_st_info_volsw, \
  46         .get = xhandler_get, .put = xhandler_put, \
  47         .private_value = (unsigned long) &(struct soc_mixer_control) \
  48         {.min = xmin, .max = xmax} }
  49
  50 struct omap_mcbsp_data {
  51         unsigned int                    bus_id;
  52         struct omap_mcbsp_reg_cfg       regs;
  53         unsigned int                    fmt;
  54         /*
  55          * Flags indicating is the bus already activated and configured by
  56          * another substream
  57          */
  58         int                             active;
  59         int                             configured;
  60         unsigned int                    in_freq;
  61         int                             clk_div;
  62         int                             wlen;
  63 };
  64
  65 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  66
  67 /*
  68  * Stream DMA parameters. DMA request line and port address are set runtime
  69  * since they are different between OMAP1 and later OMAPs
  70  */
  71 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  72
  73 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  74 static const int omap1_dma_reqs[][2] = {
  75         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  76         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  77         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  78 };
  79 static const unsigned long omap1_mcbsp_port[][2] = {
  80         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  81           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  82         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  83           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  84         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  85           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  86 };
  87 #else
  88 static const int omap1_dma_reqs[][2] = {};
  89 static const unsigned long omap1_mcbsp_port[][2] = {};
  90 #endif
  91
  92 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  93 static const int omap24xx_dma_reqs[][2] = {
  94         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  95         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  96 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  97         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  98         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  99         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
 100 #endif
 101 };
 102 #else
 103 static const int omap24xx_dma_reqs[][2] = {};
 104 #endif
 105
 106 #if defined(CONFIG_ARCH_OMAP2420)
 107 static const unsigned long omap2420_mcbsp_port[][2] = {
 108         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 109           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 110         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 111           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 112 };
 113 #else
 114 static const unsigned long omap2420_mcbsp_port[][2] = {};
 115 #endif
 116
 117 #if defined(CONFIG_ARCH_OMAP2430)
 118 static const unsigned long omap2430_mcbsp_port[][2] = {
 119         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 120           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 121         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 122           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 123         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 124           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 125         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 126           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 127         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 129 };
 130 #else
 131 static const unsigned long omap2430_mcbsp_port[][2] = {};
 132 #endif
 133
 134 #if defined(CONFIG_ARCH_OMAP3)
 135 static const unsigned long omap34xx_mcbsp_port[][2] = {
 136         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 137           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 138         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 139           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 140         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 141           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 142         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 143           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 144         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 145           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 146 };
 147 #else
 148 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 149 #endif
 150
 151 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 152 {
 153         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 154         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 155         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 156         struct omap_pcm_dma_data *dma_data;
 157         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 158         int words;
 159
 160         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 161
 162         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 163         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 164                 /*
 165                  * Configure McBSP threshold based on either:
 166                  * packet_size, when the sDMA is in packet mode, or
 167                  * based on the period size.
 168                  */
 169                 if (dma_data->packet_size)
 170                         words = dma_data->packet_size;
 171                 else
 172                         words = snd_pcm_lib_period_bytes(substream) /
 173                                                         (mcbsp_data->wlen / 8);
 174         else
 175                 words = 1;
 176
 177         /* Configure McBSP internal buffer usage */
 178         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 179                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
 180         else
 181                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
 182 }
 183
 184 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 185                                     struct snd_pcm_hw_rule *rule)
 186 {
 187         struct snd_interval *buffer_size = hw_param_interval(params,
 188                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 189         struct snd_interval *channels = hw_param_interval(params,
 190                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 191         struct omap_mcbsp_data *mcbsp_data = rule->private;
 192         struct snd_interval frames;
 193         int size;
 194
 195         snd_interval_any(&frames);
 196         size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
 197
 198         frames.min = size / channels->min;
 199         frames.integer = 1;
 200         return snd_interval_refine(buffer_size, &frames);
 201 }
 202
 203 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 204                                   struct snd_soc_dai *cpu_dai)
 205 {
 206         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 207         int bus_id = mcbsp_data->bus_id;
 208         int err = 0;
 209
 210         if (!cpu_dai->active)
 211                 err = omap_mcbsp_request(bus_id);
 212
 213         /*
 214          * OMAP3 McBSP FIFO is word structured.
 215          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 216          * McBSP1,3,4,5 has 128 word long buffer
 217          * This means that the size of the FIFO depends on the sample format.
 218          * For example on McBSP3:
 219          * 16bit samples: size is 128 * 2 = 256 bytes
 220          * 32bit samples: size is 128 * 4 = 512 bytes
 221          * It is simpler to place constraint for buffer and period based on
 222          * channels.
 223          * McBSP3 as example again (16 or 32 bit samples):
 224          * 1 channel (mono): size is 128 frames (128 words)
 225          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 226          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 227          */
 228         if (cpu_is_omap343x()) {
 229                 /*
 230                 * Rule for the buffer size. We should not allow
 231                 * smaller buffer than the FIFO size to avoid underruns
 232                 */
 233                 snd_pcm_hw_rule_add(substream->runtime, 0,
 234                                     SNDRV_PCM_HW_PARAM_CHANNELS,
 235                                     omap_mcbsp_hwrule_min_buffersize,
 236                                     mcbsp_data,
 237                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 238
 239                 /* Make sure, that the period size is always even */
 240                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 241                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 242         }
 243
 244         return err;
 245 }
 246
 247 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 248                                     struct snd_soc_dai *cpu_dai)
 249 {
 250         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 251
 252         if (!cpu_dai->active) {
 253                 omap_mcbsp_free(mcbsp_data->bus_id);
 254                 mcbsp_data->configured = 0;
 255         }
 256 }
 257
 258 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 259                                   struct snd_soc_dai *cpu_dai)
 260 {
 261         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 262         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 263
 264         switch (cmd) {
 265         case SNDRV_PCM_TRIGGER_START:
 266         case SNDRV_PCM_TRIGGER_RESUME:
 267         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 268                 mcbsp_data->active++;
 269                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 270                 break;
 271
 272         case SNDRV_PCM_TRIGGER_STOP:
 273         case SNDRV_PCM_TRIGGER_SUSPEND:
 274         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 275                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 276                 mcbsp_data->active--;
 277                 break;
 278         default:
 279                 err = -EINVAL;
 280         }
 281
 282         return err;
 283 }
 284
 285 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 286                         struct snd_pcm_substream *substream,
 287                         struct snd_soc_dai *dai)
 288 {
 289         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 290         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 291         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 292         u16 fifo_use;
 293         snd_pcm_sframes_t delay;
 294
 295         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 296                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
 297         else
 298                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
 299
 300         /*
 301          * Divide the used locations with the channel count to get the
 302          * FIFO usage in samples (don't care about partial samples in the
 303          * buffer).
 304          */
 305         delay = fifo_use / substream->runtime->channels;
 306
 307         return delay;
 308 }
 309
 310 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 311                                     struct snd_pcm_hw_params *params,
 312                                     struct snd_soc_dai *cpu_dai)
 313 {
 314         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 315         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 316         struct omap_pcm_dma_data *dma_data;
 317         int dma, bus_id = mcbsp_data->bus_id;
 318         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 319         int pkt_size = 0;
 320         unsigned long port;
 321         unsigned int format, div, framesize, master;
 322
 323         dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
 324         if (cpu_class_is_omap1()) {
 325                 dma = omap1_dma_reqs[bus_id][substream->stream];
 326                 port = omap1_mcbsp_port[bus_id][substream->stream];
 327         } else if (cpu_is_omap2420()) {
 328                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 329                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 330         } else if (cpu_is_omap2430()) {
 331                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 332                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 333         } else if (cpu_is_omap343x()) {
 334                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 335                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 336         } else {
 337                 return -ENODEV;
 338         }
 339         switch (params_format(params)) {
 340         case SNDRV_PCM_FORMAT_S16_LE:
 341                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 342                 wlen = 16;
 343                 break;
 344         case SNDRV_PCM_FORMAT_S32_LE:
 345                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 346                 wlen = 32;
 347                 break;
 348         default:
 349                 return -EINVAL;
 350         }
 351         if (cpu_is_omap343x()) {
 352                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 353                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 354                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 355                                                 MCBSP_DMA_MODE_THRESHOLD) {
 356                         int period_words, max_thrsh;
 357
 358                         period_words = params_period_bytes(params) / (wlen / 8);
 359                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 360                                 max_thrsh = omap_mcbsp_get_max_tx_threshold(
 361                                                             mcbsp_data->bus_id);
 362                         else
 363                                 max_thrsh = omap_mcbsp_get_max_rx_threshold(
 364                                                             mcbsp_data->bus_id);
 365                         /*
 366                          * If the period contains less or equal number of words,
 367                          * we are using the original threshold mode setup:
 368                          * McBSP threshold = sDMA frame size = period_size
 369                          * Otherwise we switch to sDMA packet mode:
 370                          * McBSP threshold = sDMA packet size
 371                          * sDMA frame size = period size
 372                          */
 373                         if (period_words > max_thrsh) {
 374                                 int divider = 0;
 375
 376                                 /*
 377                                  * Look for the biggest threshold value, which
 378                                  * divides the period size evenly.
 379                                  */
 380                                 divider = period_words / max_thrsh;
 381                                 if (period_words % max_thrsh)
 382                                         divider++;
 383                                 while (period_words % divider &&
 384                                         divider < period_words)
 385                                         divider++;
 386                                 if (divider == period_words)
 387                                         return -EINVAL;
 388
 389                                 pkt_size = period_words / divider;
 390                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 391                         } else {
 392                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 393                         }
 394                 }
 395         }
 396
 397         dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
 398         dma_data->dma_req = dma;
 399         dma_data->port_addr = port;
 400         dma_data->sync_mode = sync_mode;
 401         dma_data->packet_size = pkt_size;
 402
 403         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 404
 405         if (mcbsp_data->configured) {
 406                 /* McBSP already configured by another stream */
 407                 return 0;
 408         }
 409
 410         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 411         wpf = channels = params_channels(params);
 412         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 413                               format == SND_SOC_DAIFMT_LEFT_J)) {
 414                 /* Use dual-phase frames */
 415                 regs->rcr2      |= RPHASE;
 416                 regs->xcr2      |= XPHASE;
 417                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 418                 wpf--;
 419                 regs->rcr2      |= RFRLEN2(wpf - 1);
 420                 regs->xcr2      |= XFRLEN2(wpf - 1);
 421         }
 422
 423         regs->rcr1      |= RFRLEN1(wpf - 1);
 424         regs->xcr1      |= XFRLEN1(wpf - 1);
 425
 426         switch (params_format(params)) {
 427         case SNDRV_PCM_FORMAT_S16_LE:
 428                 /* Set word lengths */
 429                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 430                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 431                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 432                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 433                 break;
 434         case SNDRV_PCM_FORMAT_S32_LE:
 435                 /* Set word lengths */
 436                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 437                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 438                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 439                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 440                 break;
 441         default:
 442                 /* Unsupported PCM format */
 443                 return -EINVAL;
 444         }
 445
 446         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 447          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 448         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 449         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 450                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 451                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 452
 453                 if (framesize < wlen * channels) {
 454                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 455                                         "channels\n", __func__);
 456                         return -EINVAL;
 457                 }
 458         } else
 459                 framesize = wlen * channels;
 460
 461         /* Set FS period and length in terms of bit clock periods */
 462         switch (format) {
 463         case SND_SOC_DAIFMT_I2S:
 464         case SND_SOC_DAIFMT_LEFT_J:
 465                 regs->srgr2     |= FPER(framesize - 1);
 466                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 467                 break;
 468         case SND_SOC_DAIFMT_DSP_A:
 469         case SND_SOC_DAIFMT_DSP_B:
 470                 regs->srgr2     |= FPER(framesize - 1);
 471                 regs->srgr1     |= FWID(0);
 472                 break;
 473         }
 474
 475         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 476         mcbsp_data->wlen = wlen;
 477         mcbsp_data->configured = 1;
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 484  * cache is initialized here
 485  */
 486 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 487                                       unsigned int fmt)
 488 {
 489         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 490         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 491         unsigned int temp_fmt = fmt;
 492
 493         if (mcbsp_data->configured)
 494                 return 0;
 495
 496         mcbsp_data->fmt = fmt;
 497         memset(regs, 0, sizeof(*regs));
 498         /* Generic McBSP register settings */
 499         regs->spcr2     |= XINTM(3) | FREE;
 500         regs->spcr1     |= RINTM(3);
 501         /* RFIG and XFIG are not defined in 34xx */
 502         if (!cpu_is_omap34xx()) {
 503                 regs->rcr2      |= RFIG;
 504                 regs->xcr2      |= XFIG;
 505         }
 506         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 507                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 508                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 509         }
 510
 511         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 512         case SND_SOC_DAIFMT_I2S:
 513                 /* 1-bit data delay */
 514                 regs->rcr2      |= RDATDLY(1);
 515                 regs->xcr2      |= XDATDLY(1);
 516                 break;
 517         case SND_SOC_DAIFMT_LEFT_J:
 518                 /* 0-bit data delay */
 519                 regs->rcr2      |= RDATDLY(0);
 520                 regs->xcr2      |= XDATDLY(0);
 521                 regs->spcr1     |= RJUST(2);
 522                 /* Invert FS polarity configuration */
 523                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 524                 break;
 525         case SND_SOC_DAIFMT_DSP_A:
 526                 /* 1-bit data delay */
 527                 regs->rcr2      |= RDATDLY(1);
 528                 regs->xcr2      |= XDATDLY(1);
 529                 /* Invert FS polarity configuration */
 530                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 531                 break;
 532         case SND_SOC_DAIFMT_DSP_B:
 533                 /* 0-bit data delay */
 534                 regs->rcr2      |= RDATDLY(0);
 535                 regs->xcr2      |= XDATDLY(0);
 536                 /* Invert FS polarity configuration */
 537                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 538                 break;
 539         default:
 540                 /* Unsupported data format */
 541                 return -EINVAL;
 542         }
 543
 544         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 545         case SND_SOC_DAIFMT_CBS_CFS:
 546                 /* McBSP master. Set FS and bit clocks as outputs */
 547                 regs->pcr0      |= FSXM | FSRM |
 548                                    CLKXM | CLKRM;
 549                 /* Sample rate generator drives the FS */
 550                 regs->srgr2     |= FSGM;
 551                 break;
 552         case SND_SOC_DAIFMT_CBM_CFM:
 553                 /* McBSP slave */
 554                 break;
 555         default:
 556                 /* Unsupported master/slave configuration */
 557                 return -EINVAL;
 558         }
 559
 560         /* Set bit clock (CLKX/CLKR) and FS polarities */
 561         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 562         case SND_SOC_DAIFMT_NB_NF:
 563                 /*
 564                  * Normal BCLK + FS.
 565                  * FS active low. TX data driven on falling edge of bit clock
 566                  * and RX data sampled on rising edge of bit clock.
 567                  */
 568                 regs->pcr0      |= FSXP | FSRP |
 569                                    CLKXP | CLKRP;
 570                 break;
 571         case SND_SOC_DAIFMT_NB_IF:
 572                 regs->pcr0      |= CLKXP | CLKRP;
 573                 break;
 574         case SND_SOC_DAIFMT_IB_NF:
 575                 regs->pcr0      |= FSXP | FSRP;
 576                 break;
 577         case SND_SOC_DAIFMT_IB_IF:
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582
 583         return 0;
 584 }
 585
 586 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 587                                      int div_id, int div)
 588 {
 589         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 590         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 591
 592         if (div_id != OMAP_MCBSP_CLKGDV)
 593                 return -ENODEV;
 594
 595         mcbsp_data->clk_div = div;
 596         regs->srgr1     |= CLKGDV(div - 1);
 597
 598         return 0;
 599 }
 600
 601 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 602                                        int clk_id)
 603 {
 604         int sel_bit;
 605         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 606
 607         if (cpu_class_is_omap1()) {
 608                 /* OMAP1's can use only external source clock */
 609                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 610                         return -EINVAL;
 611                 else
 612                         return 0;
 613         }
 614
 615         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 616                 return -EINVAL;
 617
 618         if (cpu_is_omap343x())
 619                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 620
 621         switch (mcbsp_data->bus_id) {
 622         case 0:
 623                 reg = OMAP2_CONTROL_DEVCONF0;
 624                 sel_bit = 2;
 625                 break;
 626         case 1:
 627                 reg = OMAP2_CONTROL_DEVCONF0;
 628                 sel_bit = 6;
 629                 break;
 630         case 2:
 631                 reg = reg_devconf1;
 632                 sel_bit = 0;
 633                 break;
 634         case 3:
 635                 reg = reg_devconf1;
 636                 sel_bit = 2;
 637                 break;
 638         case 4:
 639                 reg = reg_devconf1;
 640                 sel_bit = 4;
 641                 break;
 642         default:
 643                 return -EINVAL;
 644         }
 645
 646         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 647                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 648         else
 649                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 650
 651         return 0;
 652 }
 653
 654 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
 655                                        int clk_id)
 656 {
 657         int sel_bit, set = 0;
 658         u16 reg = OMAP2_CONTROL_DEVCONF0;
 659
 660         if (cpu_class_is_omap1())
 661                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
 662         if (mcbsp_data->bus_id != 0)
 663                 return -EINVAL;
 664
 665         switch (clk_id) {
 666         case OMAP_MCBSP_CLKR_SRC_CLKX:
 667                 set = 1;
 668         case OMAP_MCBSP_CLKR_SRC_CLKR:
 669                 sel_bit = 3;
 670                 break;
 671         case OMAP_MCBSP_FSR_SRC_FSX:
 672                 set = 1;
 673         case OMAP_MCBSP_FSR_SRC_FSR:
 674                 sel_bit = 4;
 675                 break;
 676         default:
 677                 return -EINVAL;
 678         }
 679
 680         if (set)
 681                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 682         else
 683                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 684
 685         return 0;
 686 }
 687
 688 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 689                                          int clk_id, unsigned int freq,
 690                                          int dir)
 691 {
 692         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 693         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 694         int err = 0;
 695
 696         mcbsp_data->in_freq = freq;
 697
 698         switch (clk_id) {
 699         case OMAP_MCBSP_SYSCLK_CLK:
 700                 regs->srgr2     |= CLKSM;
 701                 break;
 702         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 703         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 704                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 705                 break;
 706
 707         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 708                 regs->srgr2     |= CLKSM;
 709         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 710                 regs->pcr0      |= SCLKME;
 711                 break;
 712
 713         case OMAP_MCBSP_CLKR_SRC_CLKR:
 714         case OMAP_MCBSP_CLKR_SRC_CLKX:
 715         case OMAP_MCBSP_FSR_SRC_FSR:
 716         case OMAP_MCBSP_FSR_SRC_FSX:
 717                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
 718                 break;
 719         default:
 720                 err = -ENODEV;
 721         }
 722
 723         return err;
 724 }
 725
 726 static struct snd_soc_dai_ops mcbsp_dai_ops = {
 727         .startup        = omap_mcbsp_dai_startup,
 728         .shutdown       = omap_mcbsp_dai_shutdown,
 729         .trigger        = omap_mcbsp_dai_trigger,
 730         .delay          = omap_mcbsp_dai_delay,
 731         .hw_params      = omap_mcbsp_dai_hw_params,
 732         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 733         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 734         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 735 };
 736
 737 static int mcbsp_dai_probe(struct snd_soc_dai *dai)
 738 {
 739         mcbsp_data[dai->id].bus_id = dai->id;
 740         snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
 741         return 0;
 742 }
 743
 744 static struct snd_soc_dai_driver omap_mcbsp_dai =
 745 {
 746         .probe = mcbsp_dai_probe,
 747         .playback = {
 748                 .channels_min = 1,
 749                 .channels_max = 16,
 750                 .rates = OMAP_MCBSP_RATES,
 751                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 752         },
 753         .capture = {
 754                 .channels_min = 1,
 755                 .channels_max = 16,
 756                 .rates = OMAP_MCBSP_RATES,
 757                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 758         },
 759         .ops = &mcbsp_dai_ops,
 760 };
 761
 762 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 763                         struct snd_ctl_elem_info *uinfo)
 764 {
 765         struct soc_mixer_control *mc =
 766                 (struct soc_mixer_control *)kcontrol->private_value;
 767         int max = mc->max;
 768         int min = mc->min;
 769
 770         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 771         uinfo->count = 1;
 772         uinfo->value.integer.min = min;
 773         uinfo->value.integer.max = max;
 774         return 0;
 775 }
 776
 777 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
 778 static int                                                              \
 779 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 780                                         struct snd_ctl_elem_value *uc)  \
 781 {                                                                       \
 782         struct soc_mixer_control *mc =                                  \
 783                 (struct soc_mixer_control *)kc->private_value;          \
 784         int max = mc->max;                                              \
 785         int min = mc->min;                                              \
 786         int val = uc->value.integer.value[0];                           \
 787                                                                         \
 788         if (val < min || val > max)                                     \
 789                 return -EINVAL;                                         \
 790                                                                         \
 791         /* OMAP McBSP implementation uses index values 0..4 */          \
 792         return omap_st_set_chgain((id)-1, channel, val);                \
 793 }
 794
 795 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
 796 static int                                                              \
 797 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 798                                         struct snd_ctl_elem_value *uc)  \
 799 {                                                                       \
 800         s16 chgain;                                                     \
 801                                                                         \
 802         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
 803                 return -EAGAIN;                                         \
 804                                                                         \
 805         uc->value.integer.value[0] = chgain;                            \
 806         return 0;                                                       \
 807 }
 808
 809 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
 810 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
 811 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
 812 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
 813 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
 814 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
 815 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
 816 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
 817
 818 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 819                                 struct snd_ctl_elem_value *ucontrol)
 820 {
 821         struct soc_mixer_control *mc =
 822                 (struct soc_mixer_control *)kcontrol->private_value;
 823         u8 value = ucontrol->value.integer.value[0];
 824
 825         if (value == omap_st_is_enabled(mc->reg))
 826                 return 0;
 827
 828         if (value)
 829                 omap_st_enable(mc->reg);
 830         else
 831                 omap_st_disable(mc->reg);
 832
 833         return 1;
 834 }
 835
 836 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 837                                 struct snd_ctl_elem_value *ucontrol)
 838 {
 839         struct soc_mixer_control *mc =
 840                 (struct soc_mixer_control *)kcontrol->private_value;
 841
 842         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
 843         return 0;
 844 }
 845
 846 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 847         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 848                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 849         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 850                                       -32768, 32767,
 851                                       omap_mcbsp2_get_st_ch0_volume,
 852                                       omap_mcbsp2_set_st_ch0_volume),
 853         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 854                                       -32768, 32767,
 855                                       omap_mcbsp2_get_st_ch1_volume,
 856                                       omap_mcbsp2_set_st_ch1_volume),
 857 };
 858
 859 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 860         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 861                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 862         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 863                                       -32768, 32767,
 864                                       omap_mcbsp3_get_st_ch0_volume,
 865                                       omap_mcbsp3_set_st_ch0_volume),
 866         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 867                                       -32768, 32767,
 868                                       omap_mcbsp3_get_st_ch1_volume,
 869                                       omap_mcbsp3_set_st_ch1_volume),
 870 };
 871
 872 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
 873 {
 874         if (!cpu_is_omap34xx())
 875                 return -ENODEV;
 876
 877         switch (mcbsp_id) {
 878         case 1: /* McBSP 2 */
 879                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
 880                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 881         case 2: /* McBSP 3 */
 882                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
 883                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 884         default:
 885                 break;
 886         }
 887
 888         return -EINVAL;
 889 }
 890 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 891
 892 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 893 {
 894         return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 895 }
 896
 897 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 898 {
 899         snd_soc_unregister_dai(&pdev->dev);
 900         return 0;
 901 }
 902
 903 static struct platform_driver asoc_mcbsp_driver = {
 904         .driver = {
 905                         .name = "omap-mcbsp-dai",
 906                         .owner = THIS_MODULE,
 907         },
 908
 909         .probe = asoc_mcbsp_probe,
 910         .remove = __devexit_p(asoc_mcbsp_remove),
 911 };
 912
 913 static int __init snd_omap_mcbsp_init(void)
 914 {
 915         return platform_driver_register(&asoc_mcbsp_driver);
 916 }
 917 module_init(snd_omap_mcbsp_init);
 918
 919 static void __exit snd_omap_mcbsp_exit(void)
 920 {
 921         platform_driver_unregister(&asoc_mcbsp_driver);
 922 }
 923 module_exit(snd_omap_mcbsp_exit);
 924
 925 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 926 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 927 MODULE_LICENSE("GPL");