2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
30 #include <linux/of_device.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/initval.h>
35 #include <sound/soc.h>
38 #include <plat/mcbsp.h>
40 #include "omap-mcbsp.h"
43 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
45 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
46 xhandler_get, xhandler_put) \
47 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
48 .info = omap_mcbsp_st_info_volsw, \
49 .get = xhandler_get, .put = xhandler_put, \
50 .private_value = (unsigned long) &(struct soc_mixer_control) \
51 {.min = xmin, .max = xmax} }
54 OMAP_MCBSP_WORD_8 = 0,
63 * Stream DMA parameters. DMA request line and port address are set runtime
64 * since they are different between OMAP1 and later OMAPs
66 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
68 struct snd_soc_pcm_runtime *rtd = substream->private_data;
69 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
70 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
71 struct omap_pcm_dma_data *dma_data;
74 dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
77 * Configure McBSP threshold based on either:
78 * packet_size, when the sDMA is in packet mode, or based on the
79 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
82 if (dma_data->packet_size)
83 words = dma_data->packet_size;
84 else if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
85 words = snd_pcm_lib_period_bytes(substream) /
90 /* Configure McBSP internal buffer usage */
91 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
92 omap_mcbsp_set_tx_threshold(mcbsp, words);
94 omap_mcbsp_set_rx_threshold(mcbsp, words);
97 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
98 struct snd_pcm_hw_rule *rule)
100 struct snd_interval *buffer_size = hw_param_interval(params,
101 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
102 struct snd_interval *channels = hw_param_interval(params,
103 SNDRV_PCM_HW_PARAM_CHANNELS);
104 struct omap_mcbsp *mcbsp = rule->private;
105 struct snd_interval frames;
108 snd_interval_any(&frames);
109 size = mcbsp->pdata->buffer_size;
111 frames.min = size / channels->min;
113 return snd_interval_refine(buffer_size, &frames);
116 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
119 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
122 if (!cpu_dai->active)
123 err = omap_mcbsp_request(mcbsp);
126 * OMAP3 McBSP FIFO is word structured.
127 * McBSP2 has 1024 + 256 = 1280 word long buffer,
128 * McBSP1,3,4,5 has 128 word long buffer
129 * This means that the size of the FIFO depends on the sample format.
130 * For example on McBSP3:
131 * 16bit samples: size is 128 * 2 = 256 bytes
132 * 32bit samples: size is 128 * 4 = 512 bytes
133 * It is simpler to place constraint for buffer and period based on
135 * McBSP3 as example again (16 or 32 bit samples):
136 * 1 channel (mono): size is 128 frames (128 words)
137 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
138 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
140 if (mcbsp->pdata->buffer_size) {
142 * Rule for the buffer size. We should not allow
143 * smaller buffer than the FIFO size to avoid underruns.
144 * This applies only for the playback stream.
146 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
147 snd_pcm_hw_rule_add(substream->runtime, 0,
148 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
149 omap_mcbsp_hwrule_min_buffersize,
151 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
153 /* Make sure, that the period size is always even */
154 snd_pcm_hw_constraint_step(substream->runtime, 0,
155 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
161 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
162 struct snd_soc_dai *cpu_dai)
164 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
166 if (!cpu_dai->active) {
167 omap_mcbsp_free(mcbsp);
168 mcbsp->configured = 0;
172 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
173 struct snd_soc_dai *cpu_dai)
175 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
176 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
179 case SNDRV_PCM_TRIGGER_START:
180 case SNDRV_PCM_TRIGGER_RESUME:
181 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
183 omap_mcbsp_start(mcbsp, play, !play);
186 case SNDRV_PCM_TRIGGER_STOP:
187 case SNDRV_PCM_TRIGGER_SUSPEND:
188 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
189 omap_mcbsp_stop(mcbsp, play, !play);
199 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
200 struct snd_pcm_substream *substream,
201 struct snd_soc_dai *dai)
203 struct snd_soc_pcm_runtime *rtd = substream->private_data;
204 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
205 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
207 snd_pcm_sframes_t delay;
209 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
210 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
212 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
215 * Divide the used locations with the channel count to get the
216 * FIFO usage in samples (don't care about partial samples in the
219 delay = fifo_use / substream->runtime->channels;
224 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *cpu_dai)
228 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
229 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
230 struct omap_pcm_dma_data *dma_data;
231 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
233 unsigned int format, div, framesize, master;
235 dma_data = &mcbsp->dma_data[substream->stream];
236 channels = params_channels(params);
238 switch (params_format(params)) {
239 case SNDRV_PCM_FORMAT_S16_LE:
240 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
243 case SNDRV_PCM_FORMAT_S32_LE:
244 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
250 if (mcbsp->pdata->buffer_size) {
251 dma_data->set_threshold = omap_mcbsp_set_threshold;
252 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
253 int period_words, max_thrsh;
255 period_words = params_period_bytes(params) / (wlen / 8);
256 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257 max_thrsh = mcbsp->max_tx_thres;
259 max_thrsh = mcbsp->max_rx_thres;
261 * If the period contains less or equal number of words,
262 * we are using the original threshold mode setup:
263 * McBSP threshold = sDMA frame size = period_size
264 * Otherwise we switch to sDMA packet mode:
265 * McBSP threshold = sDMA packet size
266 * sDMA frame size = period size
268 if (period_words > max_thrsh) {
272 * Look for the biggest threshold value, which
273 * divides the period size evenly.
275 divider = period_words / max_thrsh;
276 if (period_words % max_thrsh)
278 while (period_words % divider &&
279 divider < period_words)
281 if (divider == period_words)
284 pkt_size = period_words / divider;
285 sync_mode = OMAP_DMA_SYNC_PACKET;
287 sync_mode = OMAP_DMA_SYNC_FRAME;
289 } else if (channels > 1) {
290 /* Use packet mode for non mono streams */
292 sync_mode = OMAP_DMA_SYNC_PACKET;
296 dma_data->sync_mode = sync_mode;
297 dma_data->packet_size = pkt_size;
299 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
301 if (mcbsp->configured) {
302 /* McBSP already configured by another stream */
306 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
307 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
308 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
309 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
310 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
312 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
313 format == SND_SOC_DAIFMT_LEFT_J)) {
314 /* Use dual-phase frames */
315 regs->rcr2 |= RPHASE;
316 regs->xcr2 |= XPHASE;
317 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
319 regs->rcr2 |= RFRLEN2(wpf - 1);
320 regs->xcr2 |= XFRLEN2(wpf - 1);
323 regs->rcr1 |= RFRLEN1(wpf - 1);
324 regs->xcr1 |= XFRLEN1(wpf - 1);
326 switch (params_format(params)) {
327 case SNDRV_PCM_FORMAT_S16_LE:
328 /* Set word lengths */
329 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
330 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
331 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
332 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
334 case SNDRV_PCM_FORMAT_S32_LE:
335 /* Set word lengths */
336 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
337 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
338 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
339 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
342 /* Unsupported PCM format */
346 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
347 * by _counting_ BCLKs. Calculate frame size in BCLKs */
348 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
349 if (master == SND_SOC_DAIFMT_CBS_CFS) {
350 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
351 framesize = (mcbsp->in_freq / div) / params_rate(params);
353 if (framesize < wlen * channels) {
354 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
355 "channels\n", __func__);
359 framesize = wlen * channels;
361 /* Set FS period and length in terms of bit clock periods */
362 regs->srgr2 &= ~FPER(0xfff);
363 regs->srgr1 &= ~FWID(0xff);
365 case SND_SOC_DAIFMT_I2S:
366 case SND_SOC_DAIFMT_LEFT_J:
367 regs->srgr2 |= FPER(framesize - 1);
368 regs->srgr1 |= FWID((framesize >> 1) - 1);
370 case SND_SOC_DAIFMT_DSP_A:
371 case SND_SOC_DAIFMT_DSP_B:
372 regs->srgr2 |= FPER(framesize - 1);
373 regs->srgr1 |= FWID(0);
377 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
379 mcbsp->configured = 1;
385 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
386 * cache is initialized here
388 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
391 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
392 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
395 if (mcbsp->configured)
399 memset(regs, 0, sizeof(*regs));
400 /* Generic McBSP register settings */
401 regs->spcr2 |= XINTM(3) | FREE;
402 regs->spcr1 |= RINTM(3);
403 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
404 if (!mcbsp->pdata->has_ccr) {
409 /* Configure XCCR/RCCR only for revisions which have ccr registers */
410 if (mcbsp->pdata->has_ccr) {
411 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
412 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
415 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
416 case SND_SOC_DAIFMT_I2S:
417 /* 1-bit data delay */
418 regs->rcr2 |= RDATDLY(1);
419 regs->xcr2 |= XDATDLY(1);
421 case SND_SOC_DAIFMT_LEFT_J:
422 /* 0-bit data delay */
423 regs->rcr2 |= RDATDLY(0);
424 regs->xcr2 |= XDATDLY(0);
425 regs->spcr1 |= RJUST(2);
426 /* Invert FS polarity configuration */
429 case SND_SOC_DAIFMT_DSP_A:
430 /* 1-bit data delay */
431 regs->rcr2 |= RDATDLY(1);
432 regs->xcr2 |= XDATDLY(1);
433 /* Invert FS polarity configuration */
436 case SND_SOC_DAIFMT_DSP_B:
437 /* 0-bit data delay */
438 regs->rcr2 |= RDATDLY(0);
439 regs->xcr2 |= XDATDLY(0);
440 /* Invert FS polarity configuration */
444 /* Unsupported data format */
448 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
449 case SND_SOC_DAIFMT_CBS_CFS:
450 /* McBSP master. Set FS and bit clocks as outputs */
451 regs->pcr0 |= FSXM | FSRM |
453 /* Sample rate generator drives the FS */
456 case SND_SOC_DAIFMT_CBM_CFM:
460 /* Unsupported master/slave configuration */
464 /* Set bit clock (CLKX/CLKR) and FS polarities */
465 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
466 case SND_SOC_DAIFMT_NB_NF:
469 * FS active low. TX data driven on falling edge of bit clock
470 * and RX data sampled on rising edge of bit clock.
472 regs->pcr0 |= FSXP | FSRP |
475 case SND_SOC_DAIFMT_NB_IF:
476 regs->pcr0 |= CLKXP | CLKRP;
478 case SND_SOC_DAIFMT_IB_NF:
479 regs->pcr0 |= FSXP | FSRP;
481 case SND_SOC_DAIFMT_IB_IF:
487 regs->pcr0 ^= FSXP | FSRP;
492 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
495 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
496 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
498 if (div_id != OMAP_MCBSP_CLKGDV)
501 mcbsp->clk_div = div;
502 regs->srgr1 &= ~CLKGDV(0xff);
503 regs->srgr1 |= CLKGDV(div - 1);
508 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
509 int clk_id, unsigned int freq,
512 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
513 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
517 if (freq == mcbsp->in_freq)
523 mcbsp->in_freq = freq;
524 regs->srgr2 &= ~CLKSM;
525 regs->pcr0 &= ~SCLKME;
528 case OMAP_MCBSP_SYSCLK_CLK:
529 regs->srgr2 |= CLKSM;
531 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
532 if (cpu_class_is_omap1()) {
536 err = omap2_mcbsp_set_clks_src(mcbsp,
537 MCBSP_CLKS_PRCM_SRC);
539 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
540 if (cpu_class_is_omap1()) {
544 err = omap2_mcbsp_set_clks_src(mcbsp,
548 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
549 regs->srgr2 |= CLKSM;
550 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
551 regs->pcr0 |= SCLKME;
560 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
561 .startup = omap_mcbsp_dai_startup,
562 .shutdown = omap_mcbsp_dai_shutdown,
563 .trigger = omap_mcbsp_dai_trigger,
564 .delay = omap_mcbsp_dai_delay,
565 .hw_params = omap_mcbsp_dai_hw_params,
566 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
567 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
568 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
571 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
573 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
575 pm_runtime_enable(mcbsp->dev);
580 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
582 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
584 pm_runtime_disable(mcbsp->dev);
589 static struct snd_soc_dai_driver omap_mcbsp_dai = {
590 .probe = omap_mcbsp_probe,
591 .remove = omap_mcbsp_remove,
595 .rates = OMAP_MCBSP_RATES,
596 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
601 .rates = OMAP_MCBSP_RATES,
602 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
604 .ops = &mcbsp_dai_ops,
607 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_info *uinfo)
610 struct soc_mixer_control *mc =
611 (struct soc_mixer_control *)kcontrol->private_value;
615 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
617 uinfo->value.integer.min = min;
618 uinfo->value.integer.max = max;
622 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(channel) \
624 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
625 struct snd_ctl_elem_value *uc) \
627 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
628 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
629 struct soc_mixer_control *mc = \
630 (struct soc_mixer_control *)kc->private_value; \
633 int val = uc->value.integer.value[0]; \
635 if (val < min || val > max) \
638 /* OMAP McBSP implementation uses index values 0..4 */ \
639 return omap_st_set_chgain(mcbsp, channel, val); \
642 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(channel) \
644 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
645 struct snd_ctl_elem_value *uc) \
647 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
648 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
651 if (omap_st_get_chgain(mcbsp, channel, &chgain)) \
654 uc->value.integer.value[0] = chgain; \
658 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(0)
659 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(1)
660 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(0)
661 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(1)
663 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
664 struct snd_ctl_elem_value *ucontrol)
666 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
667 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
668 u8 value = ucontrol->value.integer.value[0];
670 if (value == omap_st_is_enabled(mcbsp))
674 omap_st_enable(mcbsp);
676 omap_st_disable(mcbsp);
681 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
682 struct snd_ctl_elem_value *ucontrol)
684 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
685 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
687 ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
691 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
692 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
693 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
694 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
696 omap_mcbsp_get_st_ch0_volume,
697 omap_mcbsp_set_st_ch0_volume),
698 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
700 omap_mcbsp_get_st_ch1_volume,
701 omap_mcbsp_set_st_ch1_volume),
704 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
705 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
706 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
707 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
709 omap_mcbsp_get_st_ch0_volume,
710 omap_mcbsp_set_st_ch0_volume),
711 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
713 omap_mcbsp_get_st_ch1_volume,
714 omap_mcbsp_set_st_ch1_volume),
717 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
719 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
720 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
725 switch (cpu_dai->id) {
726 case 2: /* McBSP 2 */
727 return snd_soc_add_dai_controls(cpu_dai,
728 omap_mcbsp2_st_controls,
729 ARRAY_SIZE(omap_mcbsp2_st_controls));
730 case 3: /* McBSP 3 */
731 return snd_soc_add_dai_controls(cpu_dai,
732 omap_mcbsp3_st_controls,
733 ARRAY_SIZE(omap_mcbsp3_st_controls));
740 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
742 static struct omap_mcbsp_platform_data omap2420_pdata = {
747 static struct omap_mcbsp_platform_data omap2430_pdata = {
753 static struct omap_mcbsp_platform_data omap3_pdata = {
760 static struct omap_mcbsp_platform_data omap4_pdata = {
767 static const struct of_device_id omap_mcbsp_of_match[] = {
769 .compatible = "ti,omap2420-mcbsp",
770 .data = &omap2420_pdata,
773 .compatible = "ti,omap2430-mcbsp",
774 .data = &omap2430_pdata,
777 .compatible = "ti,omap3-mcbsp",
778 .data = &omap3_pdata,
781 .compatible = "ti,omap4-mcbsp",
782 .data = &omap4_pdata,
786 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
788 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
790 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
791 struct omap_mcbsp *mcbsp;
792 const struct of_device_id *match;
795 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
797 struct device_node *node = pdev->dev.of_node;
800 pdata = devm_kzalloc(&pdev->dev,
801 sizeof(struct omap_mcbsp_platform_data),
806 memcpy(pdata, match->data, sizeof(*pdata));
807 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
808 pdata->buffer_size = buffer_size;
810 dev_err(&pdev->dev, "missing platform data.\n");
813 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
817 mcbsp->id = pdev->id;
818 mcbsp->pdata = pdata;
819 mcbsp->dev = &pdev->dev;
820 platform_set_drvdata(pdev, mcbsp);
822 ret = omap_mcbsp_init(pdev);
824 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
829 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
831 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
833 snd_soc_unregister_dai(&pdev->dev);
835 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
836 mcbsp->pdata->ops->free(mcbsp->id);
838 omap_mcbsp_sysfs_remove(mcbsp);
840 clk_put(mcbsp->fclk);
842 platform_set_drvdata(pdev, NULL);
847 static struct platform_driver asoc_mcbsp_driver = {
849 .name = "omap-mcbsp",
850 .owner = THIS_MODULE,
851 .of_match_table = omap_mcbsp_of_match,
854 .probe = asoc_mcbsp_probe,
855 .remove = __devexit_p(asoc_mcbsp_remove),
858 module_platform_driver(asoc_mcbsp_driver);
860 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
861 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
862 MODULE_LICENSE("GPL");
863 MODULE_ALIAS("platform:omap-mcbsp");