sound/soc/rk29/rk30_i2s.c

   1 /*
   2  * rk29_i2s.c  --  ALSA SoC ROCKCHIP IIS Audio Layer Platform driver
   3  *
   4  * Driver for rockchip iis audio
   5  *
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/device.h>
  18 #include <linux/delay.h>
  19 #include <linux/clk.h>
  20 #include <linux/version.h>
  21
  22 #include <asm/dma.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/initval.h>
  27 #include <sound/soc.h>
  28 #include <asm/io.h>
  29
  30 #include <mach/board.h>
  31 #include <mach/hardware.h>
  32 #include <mach/io.h>
  33 #include <mach/gpio.h>
  34 #include <mach/iomux.h>
  35 #include <mach/dma-pl330.h>
  36
  37 #include "rk29_pcm.h"
  38 #include "rk29_i2s.h"
  39
  40
  41 #if 0
  42 #define I2S_DBG(x...) printk(KERN_INFO x)
  43 #else
  44 #define I2S_DBG(x...) do { } while (0)
  45 #endif
  46
  47 #define pheadi2s  ((pI2S_REG)(i2s->regs))
  48
  49 #define MAX_I2S         3
  50
  51 struct rk29_i2s_info {
  52         struct device   *dev;
  53         void __iomem    *regs;
  54
  55         u32     feature;
  56
  57         struct clk      *iis_clk;
  58         struct clk      *iis_pclk;
  59
  60         unsigned char   master;
  61
  62         struct rockchip_pcm_dma_params  *dma_playback;
  63         struct rockchip_pcm_dma_params  *dma_capture;
  64
  65         u32              suspend_iismod;
  66         u32              suspend_iiscon;
  67         u32              suspend_iispsr;
  68 };
  69
  70 static struct rk29_dma_client rk29_dma_client_out = {
  71         .name = "I2S PCM Stereo Out"
  72 };
  73
  74 static struct rk29_dma_client rk29_dma_client_in = {
  75         .name = "I2S PCM Stereo In"
  76 };
  77
  78 static inline struct rk29_i2s_info *to_info(struct snd_soc_dai *cpu_dai)
  79 {
  80         return snd_soc_dai_get_drvdata(cpu_dai);
  81 }
  82
  83 static struct rockchip_pcm_dma_params rk29_i2s_pcm_stereo_out[MAX_I2S];
  84 static struct rockchip_pcm_dma_params rk29_i2s_pcm_stereo_in[MAX_I2S];
  85 static struct rk29_i2s_info rk29_i2s[MAX_I2S];
  86
  87 struct snd_soc_dai_driver rk29_i2s_dai[MAX_I2S];
  88 EXPORT_SYMBOL_GPL(rk29_i2s_dai);
  89
  90 static u32 i2s0_clk_enter(void)
  91 {
  92   return 0;
  93 }
  94
  95 static void i2s0_clk_exit(u32 clk)
  96 {
  97 }
  98
  99 /*
 100  *Turn on or off the transmission path.
 101  */
 102
 103 static int flag_i2s_tx = 0;
 104 static int flag_i2s_rx = 0;
 105 static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
 106 {
 107         u32 opr,xfer;
 108         u32 clk;
 109
 110         opr  = readl(&(pheadi2s->I2S_DMACR));
 111         xfer = readl(&(pheadi2s->I2S_XFER));
 112
 113         if (on)
 114         {
 115                 I2S_DBG("rockchip_snd_txctrl: on\n");
 116
 117                 //start tx
 118                 //if ((flag_i2s_tx == 0) && (flag_i2s_rx == 0))
 119                 if ((xfer&I2S_TX_TRAN_START)==0 || (xfer&I2S_RX_TRAN_START)==0)
 120                 {
 121                         clk = i2s0_clk_enter();
 122
 123                         //if start tx & rx clk, need reset i2s
 124                         xfer |= I2S_TX_TRAN_START;
 125                         xfer |= I2S_RX_TRAN_START;
 126                         writel(xfer, &(pheadi2s->I2S_XFER));
 127
 128                         i2s0_clk_exit(clk);
 129                 }
 130
 131                 if ((opr & I2S_TRAN_DMA_ENABLE) == 0)
 132                 {
 133                         opr  |= I2S_TRAN_DMA_ENABLE;
 134                         writel(opr, &(pheadi2s->I2S_DMACR));
 135                 }
 136
 137                 flag_i2s_tx = 1;
 138         }
 139         else
 140         {
 141                 //stop tx
 142                 flag_i2s_tx = 0;
 143                 if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
 144                 {
 145                         opr  &= ~I2S_TRAN_DMA_ENABLE;
 146                         writel(opr, &(pheadi2s->I2S_DMACR));
 147                         if(stopI2S)
 148                         {
 149                                 clk = i2s0_clk_enter();
 150
 151                                 xfer &= ~I2S_RX_TRAN_START;
 152                                 xfer &= ~I2S_TX_TRAN_START;
 153                                 writel(xfer, &(pheadi2s->I2S_XFER));
 154
 155                                 i2s0_clk_exit(clk);
 156                         }
 157
 158                         //after stop rx & tx clk, reset i2s
 159                         //writel(0x001,&(pheadi2s->I2S_TXRST));
 160                         //writel(0x001,&(pheadi2s->I2S_RXRST));
 161                 }
 162
 163                 I2S_DBG("rockchip_snd_txctrl: off\n");
 164         }
 165 }
 166
 167 static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on, bool stopI2S)
 168 {
 169         u32 opr,xfer;
 170         u32 clk;
 171
 172         opr  = readl(&(pheadi2s->I2S_DMACR));
 173         xfer = readl(&(pheadi2s->I2S_XFER));
 174
 175         if (on)
 176         {
 177             I2S_DBG("rockchip_snd_rxctrl: on\n");
 178
 179                 //start rx
 180                 //if ((flag_i2s_tx == 0) && (flag_i2s_rx == 0))
 181                 if ((xfer&I2S_TX_TRAN_START)==0 || (xfer&I2S_RX_TRAN_START)==0)
 182                 {
 183                         clk = i2s0_clk_enter();
 184
 185                         xfer |= I2S_TX_TRAN_START;
 186                         xfer |= I2S_RX_TRAN_START;
 187                         writel(xfer, &(pheadi2s->I2S_XFER));
 188
 189                         i2s0_clk_exit(clk);
 190                 }
 191
 192                 if ((opr & I2S_RECE_DMA_ENABLE) == 0)
 193                 {
 194                         opr  |= I2S_RECE_DMA_ENABLE;
 195                         writel(opr, &(pheadi2s->I2S_DMACR));
 196                 }
 197
 198           flag_i2s_rx = 1;
 199         }
 200         else
 201         {
 202                 //stop rx
 203                 flag_i2s_rx = 0;
 204                 if ((flag_i2s_rx == 0) && (flag_i2s_tx == 0))
 205                 {
 206                         opr  &= ~I2S_RECE_DMA_ENABLE;
 207                         writel(opr, &(pheadi2s->I2S_DMACR));
 208
 209                         if(stopI2S)
 210                         {
 211                                 clk = i2s0_clk_enter();
 212
 213                                 xfer &= ~I2S_RX_TRAN_START;
 214                                 xfer &= ~I2S_TX_TRAN_START;
 215                                 writel(xfer, &(pheadi2s->I2S_XFER));
 216
 217                                 i2s0_clk_exit(clk);
 218                         }
 219
 220                         //after stop rx & tx clk, reset i2s
 221                         //writel(0x001,&(pheadi2s->I2S_TXRST));
 222                         //writel(0x001,&(pheadi2s->I2S_RXRST));
 223                 }
 224
 225                 I2S_DBG("rockchip_snd_rxctrl: off\n");
 226         }
 227 }
 228
 229 /*
 230  * Set Rockchip I2S DAI format
 231  */
 232 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 233                                                 unsigned int fmt)
 234 {
 235         struct rk29_i2s_info *i2s = to_info(cpu_dai);
 236         u32 tx_ctl,rx_ctl;
 237         u32 iis_ckr_value;//clock generation register
 238
 239         I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 240
 241         tx_ctl = readl(&(pheadi2s->I2S_TXCR));
 242         iis_ckr_value = readl(&(pheadi2s->I2S_CKR));
 243
 244         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 245                 case SND_SOC_DAIFMT_CBM_CFM:
 246                         iis_ckr_value &= ~I2S_MODE_MASK;
 247                         iis_ckr_value |= I2S_MASTER_MODE;
 248                         break;
 249                 case SND_SOC_DAIFMT_CBS_CFS:
 250                         iis_ckr_value &= ~I2S_MODE_MASK;
 251                         iis_ckr_value |= I2S_SLAVE_MODE;
 252                         break;
 253                 default:
 254                         I2S_DBG("unknwon master/slave format\n");
 255                         return -EINVAL;
 256         }
 257         writel(iis_ckr_value, &(pheadi2s->I2S_CKR));
 258         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 259                 case SND_SOC_DAIFMT_RIGHT_J:
 260                         tx_ctl &= ~I2S_BUS_MODE_MASK;    //I2S Bus Mode
 261                         tx_ctl |= I2S_BUS_MODE_RSJM;
 262                         break;
 263                 case SND_SOC_DAIFMT_LEFT_J:
 264                         tx_ctl &= ~I2S_BUS_MODE_MASK;    //I2S Bus Mode
 265                         tx_ctl |= I2S_BUS_MODE_LSJM;
 266                         break;
 267                 case SND_SOC_DAIFMT_I2S:
 268                         tx_ctl &= ~I2S_BUS_MODE_MASK;    //I2S Bus Mode
 269                         tx_ctl |= I2S_BUS_MODE_NOR;
 270                         break;
 271                 default:
 272                         I2S_DBG("Unknown data format\n");
 273                         return -EINVAL;
 274         }
 275         I2S_DBG("Enter::%s----%d, I2S_TXCR=0x%X\n",__FUNCTION__,__LINE__,tx_ctl);
 276 #if 0//defined(CONFIG_SND_RK29_SOC_alc5631) || defined(CONFIG_SND_RK29_SOC_alc5621)
 277         rx_ctl = tx_ctl;
 278         rx_ctl &= ~I2S_MODE_MASK;
 279         rx_ctl |= I2S_SLAVE_MODE;  // set tx slave, rx master
 280         writel(rx_ctl, &(pheadi2s->I2S_TXCR));
 281 #else
 282         writel(tx_ctl, &(pheadi2s->I2S_TXCR));
 283 #endif
 284         rx_ctl = tx_ctl & 0x00007FFF;
 285         writel(rx_ctl, &(pheadi2s->I2S_RXCR));
 286         return 0;
 287 }
 288
 289 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 290                                 struct snd_pcm_hw_params *params, struct snd_soc_dai *socdai)
 291 {
 292         struct rk29_i2s_info *i2s = to_info(socdai);
 293         u32 iismod;
 294         u32 dmarc;
 295         u32 iis_ckr_value;//clock generation register
 296
 297         I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
 298
 299         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 300                 snd_soc_dai_set_dma_data(socdai, substream, i2s->dma_playback);
 301         else
 302                 snd_soc_dai_set_dma_data(socdai, substream, i2s->dma_capture);
 303
 304         /* Working copies of register */
 305         iismod = readl(&(pheadi2s->I2S_TXCR));
 306
 307 //      iismod &= (~((1<<5)-1));
 308         switch (params_format(params)) {
 309         case SNDRV_PCM_FORMAT_S8:
 310                 iismod |= SAMPLE_DATA_8bit;
 311                 break;
 312         case SNDRV_PCM_FORMAT_S16_LE:
 313                 iismod |= I2S_DATA_WIDTH(15);
 314                 break;
 315         case SNDRV_PCM_FORMAT_S20_3LE:
 316                         iismod |= I2S_DATA_WIDTH(19);
 317                         break;
 318         case SNDRV_PCM_FORMAT_S24_LE:
 319                         iismod |= I2S_DATA_WIDTH(23);
 320                         break;
 321         case SNDRV_PCM_FORMAT_S32_LE:
 322                         iismod |= I2S_DATA_WIDTH(31);
 323                         break;
 324         }
 325
 326         iis_ckr_value = readl(&(pheadi2s->I2S_CKR));
 327         #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
 328         iis_ckr_value &= ~I2S_SLAVE_MODE;
 329         #endif
 330         #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
 331         iis_ckr_value |= I2S_SLAVE_MODE;
 332         #endif
 333         writel(iis_ckr_value, &(pheadi2s->I2S_CKR));
 334
 335 //      writel((16<<24) |(16<<18)|(16<<12)|(16<<6)|16, &(pheadi2s->I2S_FIFOLR));
 336         dmarc = readl(&(pheadi2s->I2S_DMACR));
 337
 338         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 339                 dmarc = ((dmarc & 0xFFFFFE00) | 16);
 340         else
 341                 dmarc = ((dmarc & 0xFE00FFFF) | 16<<16);
 342
 343         writel(dmarc, &(pheadi2s->I2S_DMACR));
 344         I2S_DBG("Enter %s, %d I2S_TXCR=0x%08X\n", __func__, __LINE__, iismod);
 345 #if 0//defined(CONFIG_SND_RK29_SOC_alc5631) || defined(CONFIG_SND_RK29_SOC_alc5621)
 346         dmarc = iismod;
 347         dmarc &= ~I2S_MODE_MASK;
 348         dmarc |= I2S_SLAVE_MODE;     // set tx slave, rx master
 349         writel(dmarc, &(pheadi2s->I2S_TXCR));
 350 #else
 351         writel(iismod, &(pheadi2s->I2S_TXCR));
 352 #endif
 353         iismod = iismod & 0x00007FFF;
 354         writel(iismod, &(pheadi2s->I2S_RXCR));
 355
 356         return 0;
 357 }
 358
 359 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
 360 {
 361         int ret = 0;
 362         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 363         struct rk29_i2s_info *i2s = to_info(rtd->cpu_dai);
 364         bool stopI2S = false;
 365
 366         I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 367         switch (cmd) {
 368         case SNDRV_PCM_TRIGGER_START:
 369         case SNDRV_PCM_TRIGGER_RESUME:
 370         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 371                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 372                         rockchip_snd_rxctrl(i2s, 1, stopI2S);
 373                 else
 374                         rockchip_snd_txctrl(i2s, 1, stopI2S);
 375                 break;
 376
 377         case SNDRV_PCM_TRIGGER_SUSPEND:
 378                 stopI2S = true;
 379         case SNDRV_PCM_TRIGGER_STOP:
 380         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 381                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 382                         rockchip_snd_rxctrl(i2s, 0, stopI2S);
 383                 else
 384                         rockchip_snd_txctrl(i2s, 0, stopI2S);
 385                 break;
 386         default:
 387                 ret = -EINVAL;
 388                 break;
 389         }
 390
 391         return ret;
 392 }
 393
 394 /*
 395  * Set Rockchip I2S MCLK source
 396  */
 397 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 398         int clk_id, unsigned int freq, int dir)
 399 {
 400         struct rk29_i2s_info *i2s;
 401
 402         i2s = to_info(cpu_dai);
 403
 404         I2S_DBG("Enter:%s, %d, i2s=0x%p, freq=%d\n", __FUNCTION__, __LINE__, i2s, freq);
 405         /*add scu clk source and enable clk*/
 406         clk_set_rate(i2s->iis_clk, freq);
 407         return 0;
 408 }
 409
 410 /*
 411  * Set Rockchip Clock dividers
 412  */
 413 static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
 414         int div_id, int div)
 415 {
 416         struct rk29_i2s_info *i2s;
 417         u32 reg;
 418
 419         i2s = to_info(cpu_dai);
 420
 421         //stereo mode MCLK/SCK=4
 422         reg = readl(&(pheadi2s->I2S_CKR));
 423
 424         I2S_DBG("Enter:%s, %d, div_id=0x%08X, div=0x%08X\n", __FUNCTION__, __LINE__, div_id, div);
 425
 426         //when i2s in master mode ,must set codec pll div
 427         switch (div_id) {
 428         case ROCKCHIP_DIV_BCLK:
 429             reg &= ~I2S_TX_SCLK_DIV_MASK;
 430             reg |= I2S_TX_SCLK_DIV(div);
 431             reg &= ~I2S_RX_SCLK_DIV_MASK;
 432             reg |= I2S_RX_SCLK_DIV(div);
 433             break;
 434         case ROCKCHIP_DIV_MCLK:
 435             reg &= ~I2S_MCLK_DIV_MASK;
 436             reg |= I2S_MCLK_DIV(div);
 437             break;
 438         case ROCKCHIP_DIV_PRESCALER:
 439             break;
 440         default:
 441                         return -EINVAL;
 442         }
 443         writel(reg, &(pheadi2s->I2S_CKR));
 444
 445         return 0;
 446 }
 447
 448 #ifdef CONFIG_PM
 449 int rockchip_i2s_suspend(struct snd_soc_dai *cpu_dai)
 450 {
 451         I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 452 //      clk_disable(clk);
 453         return 0;
 454 }
 455
 456 int rockchip_i2s_resume(struct snd_soc_dai *cpu_dai)
 457 {
 458         I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 459 //      clk_enable(clk);
 460         return 0;
 461 }
 462 #else
 463 #define rockchip_i2s_suspend NULL
 464 #define rockchip_i2s_resume NULL
 465 #endif
 466
 467 #if defined(CONFIG_SND_RK29_SOC_alc5631) || defined(CONFIG_SND_RK29_SOC_alc5621)
 468 #define ROCKCHIP_I2S_RATES (SNDRV_PCM_RATE_44100)  //zyy 20110704, playback and record use same sample rate
 469 #else
 470 #define ROCKCHIP_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 471                             SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
 472                             SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 473 #endif
 474
 475 static struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 476         .trigger = rockchip_i2s_trigger,
 477         .hw_params = rockchip_i2s_hw_params,
 478         .set_fmt = rockchip_i2s_set_fmt,
 479         .set_clkdiv = rockchip_i2s_set_clkdiv,
 480         .set_sysclk = rockchip_i2s_set_sysclk,
 481 };
 482
 483 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 484 {
 485         I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
 486         switch(dai->id) {
 487 #ifdef CONFIG_ARCH_RK30
 488         case 0:
 489                         rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME, GPIO0A_I2S_8CH_SDI);
 490                         rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME, GPIO0B_I2S_8CH_CLK);
 491                         rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B_I2S_8CH_SCLK);
 492                         rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B_I2S_8CH_LRCK_RX);
 493                         rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B_I2S_8CH_LRCK_TX);
 494                         rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B_I2S_8CH_SDO0);
 495                         //rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B_I2S_8CH_SDO1);
 496                         //rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B_I2S_8CH_SDO2);
 497                         //rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B_I2S_8CH_SDO3);
 498                         break;
 499         case 1:
 500                         rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME, GPIO0C_I2S1_2CH_CLK);
 501                         rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C_I2S1_2CH_SCLK);
 502                         rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME, GPIO0C_I2S1_2CH_LRCK_RX);
 503                         rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C_I2S1_2CH_LRCK_TX);
 504                         rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME, GPIO0C_I2S1_2CH_SDI);
 505                         rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME, GPIO0C_I2S1_2CH_SDO);
 506                         break;
 507         case 2:
 508                         rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
 509                         rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME, GPIO0D_I2S2_2CH_SCLK);
 510                         rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME, GPIO0D_I2S2_2CH_LRCK_RX);
 511                         rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME, GPIO0D_I2S2_2CH_LRCK_TX);
 512             rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME, GPIO0D_I2S2_2CH_SDI);
 513             rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D_I2S2_2CH_SDO);
 514             break;
 515 #endif
 516 #ifdef CONFIG_ARCH_RK2928
 517         case 0:
 518                 rk30_mux_api_set(GPIO1A0_I2S_MCLK_NAME, GPIO1A_I2S_MCLK);
 519                 rk30_mux_api_set(GPIO1A1_I2S_SCLK_NAME, GPIO1A_I2S_SCLK);
 520                 rk30_mux_api_set(GPIO1A2_I2S_LRCKRX_NAME, GPIO1A_I2S_LRCKRX);
 521                 rk30_mux_api_set(GPIO1A3_I2S_LRCKTX_NAME, GPIO1A_I2S_LRCKTX);
 522                 rk30_mux_api_set(GPIO1A4_I2S_SDO_NAME, GPIO1A_I2S_SDO);
 523                 rk30_mux_api_set(GPIO1A5_I2S_SDI_NAME, GPIO1A_I2S_SDI);
 524 #endif
 525         default:
 526             I2S_DBG("Enter:%s, %d, Error For DevId!!!", __FUNCTION__, __LINE__);
 527             return -EINVAL;
 528         }
 529         return 0;
 530 }
 531
 532 static int rk29_i2s_probe(struct platform_device *pdev,
 533                           struct snd_soc_dai_driver *dai,
 534                           struct rk29_i2s_info *i2s,
 535                           unsigned long base)
 536 {
 537         struct device *dev = &pdev->dev;
 538         struct resource *res;
 539
 540         I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
 541
 542         i2s->dev = dev;
 543
 544         /* record our i2s structure for later use in the callbacks */
 545         dev_set_drvdata(&pdev->dev, i2s);
 546
 547         if (!base) {
 548                 res = platform_get_resource(pdev,
 549                                              IORESOURCE_MEM,
 550                                              0);
 551                 if (!res) {
 552                         dev_err(dev, "Unable to get register resource\n");
 553                         return -ENXIO;
 554                 }
 555
 556                 if (!request_mem_region(res->start, resource_size(res),
 557                                         "rk29_i2s")) {
 558                         dev_err(dev, "Unable to request register region\n");
 559                         return -EBUSY;
 560                 }
 561
 562                 base = res->start;
 563         }
 564
 565         i2s->regs = ioremap(base, (res->end - res->start) + 1); ////res));
 566         if (i2s->regs == NULL) {
 567                 dev_err(dev, "cannot ioremap registers\n");
 568                 return -ENXIO;
 569         }
 570
 571         i2s->iis_pclk = clk_get(dev, "hclk_i2s");
 572         if (IS_ERR(i2s->iis_pclk)) {
 573                 dev_err(dev, "failed to get iis_clock\n");
 574                 iounmap(i2s->regs);
 575                 return -ENOENT;
 576         }
 577         clk_enable(i2s->iis_pclk);
 578
 579
 580         /* Mark ourselves as in TXRX mode so we can run through our cleanup
 581          * process without warnings. */
 582         rockchip_snd_txctrl(i2s, 0, true);
 583         rockchip_snd_rxctrl(i2s, 0, true);
 584
 585         return 0;
 586 }
 587
 588 static int __devinit rockchip_i2s_probe(struct platform_device *pdev)
 589 {
 590         struct rk29_i2s_info *i2s;
 591         struct snd_soc_dai_driver *dai;
 592         int    ret;
 593
 594         I2S_DBG("Enter %s, %d pdev->id = %d >>>>>>>>>>>\n", __func__, __LINE__, pdev->id);
 595
 596         if(pdev->id >= MAX_I2S) {
 597                 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
 598                 return -EINVAL;
 599         }
 600
 601         i2s = &rk29_i2s[pdev->id];
 602         dai = &rk29_i2s_dai[pdev->id];
 603         dai->id = pdev->id;
 604         dai->symmetric_rates = 1;
 605
 606         switch(pdev->id)
 607         {
 608         case 0:
 609                 dai->name = "rk29_i2s.0";
 610                 dai->playback.channels_min = 2;
 611                 dai->playback.channels_max = 8;
 612                 break;
 613         case 1:
 614                 dai->name = "rk29_i2s.1";
 615                 dai->playback.channels_min = 2;
 616                 dai->playback.channels_max = 2;
 617                 break;
 618         case 2:
 619                 dai->name = "rk29_i2s.2";
 620                 dai->playback.channels_min = 2;
 621                 dai->playback.channels_max = 2;
 622                 break;
 623         }
 624
 625         dai->playback.rates = ROCKCHIP_I2S_RATES;
 626         dai->playback.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE;
 627         dai->capture.channels_min = 2;
 628         dai->capture.channels_max = 2;
 629         dai->capture.rates = ROCKCHIP_I2S_RATES;//;SNDRV_PCM_RATE_44100
 630         dai->capture.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE;
 631         dai->probe = rockchip_i2s_dai_probe;
 632         dai->ops = &rockchip_i2s_dai_ops;
 633         dai->suspend = rockchip_i2s_suspend;
 634         dai->resume = rockchip_i2s_resume;
 635
 636         i2s->dma_capture = &rk29_i2s_pcm_stereo_in[pdev->id];
 637         i2s->dma_playback = &rk29_i2s_pcm_stereo_out[pdev->id];
 638
 639         switch(pdev->id)
 640         {
 641 #ifdef CONFIG_ARCH_RK30
 642         case 0:
 643                 i2s->dma_capture->channel = DMACH_I2S0_8CH_RX;
 644                 i2s->dma_capture->dma_addr = RK30_I2S0_8CH_PHYS + I2S_RXR_BUFF;
 645                 i2s->dma_playback->channel = DMACH_I2S0_8CH_TX;
 646                 i2s->dma_playback->dma_addr = RK30_I2S0_8CH_PHYS + I2S_TXR_BUFF;
 647                 break;
 648         case 1:
 649                 i2s->dma_capture->channel = DMACH_I2S1_2CH_RX;
 650                 i2s->dma_capture->dma_addr = RK30_I2S1_2CH_PHYS + I2S_RXR_BUFF;
 651                 i2s->dma_playback->channel = DMACH_I2S1_2CH_TX;
 652                 i2s->dma_playback->dma_addr = RK30_I2S1_2CH_PHYS + I2S_TXR_BUFF;
 653                 break;
 654         case 2:
 655                 i2s->dma_capture->channel = DMACH_I2S2_2CH_RX;
 656                 i2s->dma_capture->dma_addr = RK30_I2S2_2CH_PHYS + I2S_RXR_BUFF;
 657                 i2s->dma_playback->channel = DMACH_I2S2_2CH_TX;
 658                 i2s->dma_playback->dma_addr = RK30_I2S2_2CH_PHYS + I2S_TXR_BUFF;
 659                 break;
 660 #endif
 661 #ifdef CONFIG_ARCH_RK2928
 662         case 0:
 663                 i2s->dma_capture->channel = DMACH_I2S0_8CH_RX;
 664                 i2s->dma_capture->dma_addr = RK2928_I2S_PHYS + I2S_RXR_BUFF;
 665                 i2s->dma_playback->channel = DMACH_I2S0_8CH_TX;
 666                 i2s->dma_playback->dma_addr = RK2928_I2S_PHYS + I2S_TXR_BUFF;
 667                 break;
 668 #endif
 669         }
 670
 671         i2s->dma_capture->client = &rk29_dma_client_in;
 672         i2s->dma_capture->dma_size = 4;
 673         i2s->dma_capture->flag = 0;                     //add by sxj, used for burst change
 674         i2s->dma_playback->client = &rk29_dma_client_out;
 675         i2s->dma_playback->dma_size = 4;
 676         i2s->dma_playback->flag = 0;                    //add by sxj, used for burst change
 677 #ifdef CONFIG_SND_I2S_DMA_EVENT_STATIC
 678          WARN_ON(rk29_dma_request(i2s->dma_playback->channel, i2s->dma_playback->client, NULL));
 679          WARN_ON(rk29_dma_request(i2s->dma_capture->channel, i2s->dma_capture->client, NULL));
 680 #endif
 681
 682         i2s->iis_clk = clk_get(&pdev->dev, "i2s");
 683         I2S_DBG("Enter:%s, %d, iis_clk=%p\n", __FUNCTION__, __LINE__, i2s->iis_clk);
 684         if (IS_ERR(i2s->iis_clk)) {
 685                 dev_err(&pdev->dev, "failed to get i2s clk\n");
 686                 ret = PTR_ERR(i2s->iis_clk);
 687                 goto err;
 688         }
 689
 690         clk_enable(i2s->iis_clk);
 691         clk_set_rate(i2s->iis_clk, 11289600);
 692
 693         ret = rk29_i2s_probe(pdev, dai, i2s, 0);
 694         if (ret)
 695                 goto err_clk;
 696
 697         ret = snd_soc_register_dai(&pdev->dev, dai);
 698         if (ret != 0)
 699                 goto err_i2sv2;
 700 #if 0
 701                 writel(0x0000000F, &(pheadi2s->I2S_TXCR));
 702                 writel(0x0000000F, &(pheadi2s->I2S_RXCR));
 703                 writel(0x00071f1F, &(pheadi2s->I2S_CKR));
 704                 writel(0x001F0110, &(pheadi2s->I2S_DMACR));
 705                 writel(0x00000003, &(pheadi2s->I2S_XFER));
 706                 while(1)
 707                 {
 708                         writel(0x5555aaaa, &(pheadi2s->I2S_TXDR));
 709                 //      msleep(1);
 710                 //      printk("-----------------------\n");
 711                 }
 712 #endif
 713
 714
 715
 716         return 0;
 717
 718 err_i2sv2:
 719         /* Not implemented for I2Sv2 core yet */
 720 err_clk:
 721         clk_put(i2s->iis_clk);
 722 err:
 723         return ret;
 724 }
 725
 726 static int __devexit rockchip_i2s_remove(struct platform_device *pdev)
 727 {
 728         snd_soc_unregister_dai(&pdev->dev);
 729         return 0;
 730 }
 731
 732 static struct platform_driver rockchip_i2s_driver = {
 733         .probe  = rockchip_i2s_probe,
 734         .remove = __devexit_p(rockchip_i2s_remove),
 735         .driver = {
 736                 .name   = "rk29_i2s",
 737                 .owner  = THIS_MODULE,
 738         },
 739 };
 740
 741 static int __init rockchip_i2s_init(void)
 742 {
 743         I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
 744
 745         return  platform_driver_register(&rockchip_i2s_driver);
 746 }
 747 module_init(rockchip_i2s_init);
 748
 749 static void __exit rockchip_i2s_exit(void)
 750 {
 751         platform_driver_unregister(&rockchip_i2s_driver);
 752 }
 753 module_exit(rockchip_i2s_exit);
 754
 755 /* Module information */
 756 MODULE_AUTHOR("rockchip");
 757 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 758 MODULE_LICENSE("GPL");
 759
 760
 761 #ifdef CONFIG_PROC_FS
 762 #include <linux/proc_fs.h>
 763 #include <linux/seq_file.h>
 764 static int proc_i2s_show(struct seq_file *s, void *v)
 765 {
 766 #ifdef CONFIG_SND_RK29_SOC_I2S_8CH
 767         struct rk29_i2s_info *i2s=&rk29_i2s[0];
 768 #else
 769 #ifdef CONFIG_SND_RK29_SOC_I2S_2CH
 770         struct rk29_i2s_info *i2s=&rk29_i2s[1];
 771 #else
 772         struct rk29_i2s_info *i2s=&rk29_i2s[2];
 773 #endif
 774 #endif
 775         printk("========Show I2S reg========\n");
 776
 777         printk("I2S_TXCR = 0x%08X\n", readl(&(pheadi2s->I2S_TXCR)));
 778         printk("I2S_RXCR = 0x%08X\n", readl(&(pheadi2s->I2S_RXCR)));
 779         printk("I2S_CKR = 0x%08X\n", readl(&(pheadi2s->I2S_CKR)));
 780         printk("I2S_DMACR = 0x%08X\n", readl(&(pheadi2s->I2S_DMACR)));
 781         printk("I2S_INTCR = 0x%08X\n", readl(&(pheadi2s->I2S_INTCR)));
 782         printk("I2S_INTSR = 0x%08X\n", readl(&(pheadi2s->I2S_INTSR)));
 783         printk("I2S_XFER = 0x%08X\n", readl(&(pheadi2s->I2S_XFER)));
 784
 785         printk("========Show I2S reg========\n");
 786         return 0;
 787 }
 788
 789 static int proc_i2s_open(struct inode *inode, struct file *file)
 790 {
 791         return single_open(file, proc_i2s_show, NULL);
 792 }
 793
 794 static const struct file_operations proc_i2s_fops = {
 795         .open           = proc_i2s_open,
 796         .read           = seq_read,
 797         .llseek         = seq_lseek,
 798         .release        = single_release,
 799 };
 800
 801 static int __init i2s_proc_init(void)
 802 {
 803         proc_create("i2s_reg", 0, NULL, &proc_i2s_fops);
 804         return 0;
 805 }
 806 late_initcall(i2s_proc_init);
 807 #endif /* CONFIG_PROC_FS */
 808