sound/soc/rockchip/rk_i2s.c

   1 /*
   2  * Rockchip I2S ALSA SoC Digital Audio Interface(DAI)  driver
   3  *
   4  * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23 #include <linux/version.h>
  24 #include <linux/of.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/io.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/regmap.h>
  30 #include <linux/rockchip/cpu.h>
  31 #include <linux/rockchip/cru.h>
  32 #include <linux/rockchip/grf.h>
  33 #include <linux/slab.h>
  34 #include <asm/dma.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/initval.h>
  39 #include <sound/soc.h>
  40 #include <sound/dmaengine_pcm.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/workqueue.h>
  43
  44 #include "rk_pcm.h"
  45 #include "rk_i2s.h"
  46
  47 #define CLK_SET_LATER
  48 #define I2S_DEFAULT_FREQ        (11289600)
  49 #define I2S_DMA_BURST_SIZE      (16) /* size * width: 16*4 = 64 bytes */
  50 static DEFINE_SPINLOCK(lock);
  51
  52 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
  53 extern int snd_config_hdmi_audio(struct snd_pcm_hw_params *params);
  54 #endif
  55
  56 struct rk_i2s_dev {
  57         struct device *dev;
  58         struct clk *clk; /* bclk */
  59         struct clk *mclk; /*mclk output only */
  60         struct clk *hclk; /*ahb clk */
  61         struct snd_dmaengine_dai_dma_data capture_dma_data;
  62         struct snd_dmaengine_dai_dma_data playback_dma_data;
  63         struct regmap *regmap;
  64         bool tx_start;
  65         bool rx_start;
  66         int xfer_mode; /* 0: i2s, 1: pcm */
  67 #ifdef CLK_SET_LATER
  68         struct delayed_work clk_delayed_work;
  69 #endif
  70 };
  71
  72 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  73 {
  74         return snd_soc_dai_get_drvdata(dai);
  75 }
  76
  77 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  78 {
  79         unsigned long flags;
  80         unsigned int val = 0;
  81         int retry = 10;
  82
  83         spin_lock_irqsave(&lock, flags);
  84
  85         dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
  86
  87         if (on) {
  88                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  89                                    I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_ENABLE);
  90
  91                 regmap_update_bits(i2s->regmap, I2S_XFER,
  92                                    I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
  93                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
  94
  95                 i2s->tx_start = true;
  96         } else {
  97                 i2s->tx_start = false;
  98
  99                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 100                                    I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_DISABLE);
 101
 102
 103                 if (!i2s->rx_start) {
 104                         regmap_update_bits(i2s->regmap, I2S_XFER,
 105                                            I2S_XFER_TXS_MASK |
 106                                            I2S_XFER_RXS_MASK,
 107                                            I2S_XFER_TXS_STOP |
 108                                            I2S_XFER_RXS_STOP);
 109
 110                         regmap_update_bits(i2s->regmap, I2S_CLR,
 111                                            I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
 112                                            I2S_CLR_TXC | I2S_CLR_RXC);
 113
 114                         regmap_read(i2s->regmap, I2S_CLR, &val);
 115
 116                         /* Should wait for clear operation to finish */
 117                         while (val) {
 118                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 119                                 retry--;
 120                                 if (!retry) {
 121                                         dev_warn(i2s->dev, "fail to clear\n");
 122                                         break;
 123                                 }
 124                         }
 125                         dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
 126                                 __func__, __LINE__);
 127                 }
 128         }
 129
 130         spin_unlock_irqrestore(&lock, flags);
 131 }
 132
 133 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 134 {
 135         unsigned long flags;
 136         unsigned int val = 0;
 137         int retry = 10;
 138
 139         spin_lock_irqsave(&lock, flags);
 140
 141         dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
 142
 143         if (on) {
 144                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 145                                    I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_ENABLE);
 146
 147                 regmap_update_bits(i2s->regmap, I2S_XFER,
 148                                    I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
 149                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 150
 151                 i2s->rx_start = true;
 152         } else {
 153                 i2s->rx_start = false;
 154
 155                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 156                                    I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_DISABLE);
 157
 158                 if (!i2s->tx_start) {
 159                         regmap_update_bits(i2s->regmap, I2S_XFER,
 160                                            I2S_XFER_TXS_MASK |
 161                                            I2S_XFER_RXS_MASK,
 162                                            I2S_XFER_TXS_STOP |
 163                                            I2S_XFER_RXS_STOP);
 164
 165                         regmap_update_bits(i2s->regmap, I2S_CLR,
 166                                            I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
 167                                            I2S_CLR_TXC | I2S_CLR_RXC);
 168
 169                         regmap_read(i2s->regmap, I2S_CLR, &val);
 170
 171                         /* Should wait for clear operation to finish */
 172                         while (val) {
 173                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 174                                 retry--;
 175                                 if (!retry) {
 176                                         dev_warn(i2s->dev, "fail to clear\n");
 177                                         break;
 178                                 }
 179                         }
 180                         dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
 181                                 __func__, __LINE__);
 182                 }
 183         }
 184
 185         spin_unlock_irqrestore(&lock, flags);
 186 }
 187
 188 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 189                                 unsigned int fmt)
 190 {
 191         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 192         unsigned int mask = 0, val = 0;
 193         int ret = 0;
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&lock, flags);
 197
 198         mask = I2S_CKR_MSS_MASK;
 199         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 200         case SND_SOC_DAIFMT_CBS_CFS:
 201                 /* Codec is slave, so set cpu master */
 202                 val = I2S_CKR_MSS_MASTER;
 203                 break;
 204         case SND_SOC_DAIFMT_CBM_CFM:
 205                 /* Codec is master, so set cpu slave */
 206                 val = I2S_CKR_MSS_SLAVE;
 207                 break;
 208         default:
 209                 ret = -EINVAL;
 210                 goto err_fmt;
 211         }
 212
 213         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 214
 215         mask = I2S_TXCR_IBM_MASK;
 216         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 217         case SND_SOC_DAIFMT_RIGHT_J:
 218                 val = I2S_TXCR_IBM_RSJM;
 219                 break;
 220         case SND_SOC_DAIFMT_LEFT_J:
 221                 val = I2S_TXCR_IBM_LSJM;
 222                 break;
 223         case SND_SOC_DAIFMT_I2S:
 224                 val = I2S_TXCR_IBM_NORMAL;
 225                 break;
 226         default:
 227                 ret = -EINVAL;
 228                 goto err_fmt;
 229         }
 230
 231         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 232
 233         mask = I2S_RXCR_IBM_MASK;
 234         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 235         case SND_SOC_DAIFMT_RIGHT_J:
 236                 val = I2S_RXCR_IBM_RSJM;
 237                 break;
 238         case SND_SOC_DAIFMT_LEFT_J:
 239                 val = I2S_RXCR_IBM_LSJM;
 240                 break;
 241         case SND_SOC_DAIFMT_I2S:
 242                 val = I2S_RXCR_IBM_NORMAL;
 243                 break;
 244         default:
 245                 ret = -EINVAL;
 246                 goto err_fmt;
 247         }
 248
 249         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 250
 251 err_fmt:
 252
 253         spin_unlock_irqrestore(&lock, flags);
 254         return ret;
 255 }
 256
 257 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 258                                   struct snd_pcm_hw_params *params,
 259                                   struct snd_soc_dai *dai)
 260 {
 261         struct rk_i2s_dev *i2s = to_info(dai);
 262         unsigned int val = 0;
 263         unsigned long flags;
 264
 265         spin_lock_irqsave(&lock, flags);
 266
 267         dev_dbg(i2s->dev, "%s: %d\n", __func__, __LINE__);
 268
 269         switch (params_format(params)) {
 270         case SNDRV_PCM_FORMAT_S8:
 271                 val |= I2S_TXCR_VDW(8);
 272                 break;
 273         case SNDRV_PCM_FORMAT_S16_LE:
 274                 val |= I2S_TXCR_VDW(16);
 275                 break;
 276         case SNDRV_PCM_FORMAT_S20_3LE:
 277                 val |= I2S_TXCR_VDW(20);
 278                 break;
 279         case SNDRV_PCM_FORMAT_S24_LE:
 280         case SNDRV_PCM_FORMAT_S24_3LE:
 281                 val |= I2S_TXCR_VDW(24);
 282                 break;
 283         case SNDRV_PCM_FORMAT_S32_LE:
 284                 val |= I2S_TXCR_VDW(32);
 285                 break;
 286         default:
 287                 dev_err(i2s->dev, "invalid fmt: %d\n", params_format(params));
 288                 spin_unlock_irqrestore(&lock, flags);
 289                 return -EINVAL;
 290         }
 291
 292         switch (params_channels(params)) {
 293         case I2S_CHANNEL_8:
 294                 val |= I2S_TXCR_CHN_8;
 295                 break;
 296         case I2S_CHANNEL_6:
 297                 val |= I2S_TXCR_CHN_6;
 298                 break;
 299         case I2S_CHANNEL_4:
 300                 val |= I2S_TXCR_CHN_4;
 301                 break;
 302         case I2S_CHANNEL_2:
 303                 val |= I2S_TXCR_CHN_2;
 304                 break;
 305         default:
 306                 dev_err(i2s->dev, "invalid channel: %d\n",
 307                         params_channels(params));
 308                 spin_unlock_irqrestore(&lock, flags);
 309                 return -EINVAL;
 310         }
 311
 312         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 313                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 314                                    I2S_TXCR_VDW_MASK |
 315                                    I2S_TXCR_CSR_MASK,
 316                                    val);
 317         } else {
 318                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 319                                    I2S_RXCR_VDW_MASK, val);
 320         }
 321
 322         regmap_update_bits(i2s->regmap, I2S_DMACR,
 323                            I2S_DMACR_TDL_MASK | I2S_DMACR_RDL_MASK,
 324                            I2S_DMACR_TDL(16) | I2S_DMACR_RDL(16));
 325
 326 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
 327         snd_config_hdmi_audio(params);
 328 #endif
 329         spin_unlock_irqrestore(&lock, flags);
 330
 331         return 0;
 332 }
 333
 334 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 335                                 struct snd_soc_dai *dai)
 336 {
 337         struct rk_i2s_dev *i2s = to_info(dai);
 338         int ret = 0;
 339
 340         switch (cmd) {
 341         case SNDRV_PCM_TRIGGER_START:
 342         case SNDRV_PCM_TRIGGER_RESUME:
 343         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 344                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 345                         rockchip_snd_rxctrl(i2s, 1);
 346                 else
 347                         rockchip_snd_txctrl(i2s, 1);
 348                 break;
 349         case SNDRV_PCM_TRIGGER_SUSPEND:
 350         case SNDRV_PCM_TRIGGER_STOP:
 351         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 352                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 353                         rockchip_snd_rxctrl(i2s, 0);
 354                 else
 355                         rockchip_snd_txctrl(i2s, 0);
 356                 break;
 357         default:
 358                 ret = -EINVAL;
 359                 break;
 360         }
 361
 362         return ret;
 363 }
 364
 365 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 366                                    int clk_id, unsigned int freq, int dir)
 367 {
 368         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 369         int ret;
 370
 371         ret = clk_set_rate(i2s->clk, freq);
 372         if (ret)
 373                 dev_err(i2s->dev, "fail set clk: freq: %d\n", freq);
 374
 375         return ret;
 376 }
 377
 378 static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
 379                                    int div_id, int div)
 380 {
 381         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 382         unsigned int val = 0;
 383         unsigned long flags;
 384
 385         spin_lock_irqsave(&lock, flags);
 386
 387         dev_dbg(i2s->dev, "%s: div_id=%d, div=%d\n", __func__, div_id, div);
 388
 389         switch (div_id) {
 390         case ROCKCHIP_DIV_BCLK:
 391                 val |= I2S_CKR_TSD(div);
 392                 val |= I2S_CKR_RSD(div);
 393                 regmap_update_bits(i2s->regmap, I2S_CKR,
 394                                    I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
 395                                    val);
 396                 break;
 397         case ROCKCHIP_DIV_MCLK:
 398                 val |= I2S_CKR_MDIV(div);
 399                 regmap_update_bits(i2s->regmap, I2S_CKR,
 400                                    I2S_CKR_MDIV_MASK, val);
 401                 break;
 402         default:
 403                 spin_unlock_irqrestore(&lock, flags);
 404                 return -EINVAL;
 405         }
 406
 407         spin_unlock_irqrestore(&lock, flags);
 408
 409         return 0;
 410 }
 411
 412 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 413 {
 414         struct rk_i2s_dev *i2s = to_info(dai);
 415
 416         dai->capture_dma_data = &i2s->capture_dma_data;
 417         dai->playback_dma_data = &i2s->playback_dma_data;
 418
 419         return 0;
 420 }
 421
 422 static struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 423         .trigger = rockchip_i2s_trigger,
 424         .hw_params = rockchip_i2s_hw_params,
 425         .set_fmt = rockchip_i2s_set_fmt,
 426         .set_clkdiv = rockchip_i2s_set_clkdiv,
 427         .set_sysclk = rockchip_i2s_set_sysclk,
 428 };
 429
 430 #define ROCKCHIP_I2S_RATES SNDRV_PCM_RATE_8000_192000
 431 #define ROCKCHIP_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 432                               SNDRV_PCM_FMTBIT_S20_3LE | \
 433                               SNDRV_PCM_FMTBIT_S24_LE | \
 434                               SNDRV_PCM_FORMAT_S32_LE)
 435
 436 struct snd_soc_dai_driver rockchip_i2s_dai[] = {
 437         {
 438                 .probe = rockchip_i2s_dai_probe,
 439                 .name = "rockchip-i2s.0",
 440                 .id = 0,
 441                 .playback = {
 442                         .channels_min = 2,
 443                         .channels_max = 8,
 444                         .rates = ROCKCHIP_I2S_RATES,
 445                         .formats = ROCKCHIP_I2S_FORMATS,
 446                 },
 447                 .capture = {
 448                         .channels_min = 2,
 449                         .channels_max = 2,
 450                         .rates = ROCKCHIP_I2S_RATES,
 451                         .formats = ROCKCHIP_I2S_FORMATS,
 452                 },
 453                 .ops = &rockchip_i2s_dai_ops,
 454                 .symmetric_rates = 1,
 455         },
 456         {
 457                 .probe = rockchip_i2s_dai_probe,
 458                 .name = "rockchip-i2s.1",
 459                 .id = 1,
 460                 .playback = {
 461                         .channels_min = 2,
 462                         .channels_max = 2,
 463                         .rates = ROCKCHIP_I2S_RATES,
 464                         .formats = ROCKCHIP_I2S_FORMATS,
 465                 },
 466                 .capture = {
 467                         .channels_min = 2,
 468                         .channels_max = 2,
 469                         .rates = ROCKCHIP_I2S_RATES,
 470                         .formats = ROCKCHIP_I2S_FORMATS,
 471                 },
 472                 .ops = &rockchip_i2s_dai_ops,
 473                 .symmetric_rates = 1,
 474         },
 475 };
 476
 477 static const struct snd_soc_component_driver rockchip_i2s_component = {
 478         .name = "rockchip-i2s",
 479 };
 480
 481 #ifdef CONFIG_PM
 482 static int rockchip_i2s_runtime_suspend(struct device *dev)
 483 {
 484         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 485
 486         dev_dbg(i2s->dev, "%s\n", __func__);
 487         return 0;
 488 }
 489
 490 static int rockchip_i2s_runtime_resume(struct device *dev)
 491 {
 492         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 493
 494         dev_dbg(i2s->dev, "%s\n", __func__);
 495         return 0;
 496 }
 497 #else
 498 #define i2s_runtime_suspend NULL
 499 #define i2s_runtime_resume NULL
 500 #endif
 501
 502 #ifdef CLK_SET_LATER
 503 static void set_clk_later_work(struct work_struct *work)
 504 {
 505         struct rk_i2s_dev *i2s = container_of(work, struct rk_i2s_dev,
 506                                                  clk_delayed_work.work);
 507
 508         clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
 509         if (!IS_ERR(i2s->mclk))
 510                 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
 511 }
 512 #endif
 513
 514 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 515 {
 516         switch (reg) {
 517         case I2S_TXCR:
 518         case I2S_RXCR:
 519         case I2S_CKR:
 520         case I2S_DMACR:
 521         case I2S_INTCR:
 522         case I2S_XFER:
 523         case I2S_CLR:
 524         case I2S_TXDR:
 525                 return true;
 526         default:
 527                 return false;
 528         }
 529 }
 530
 531 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 532 {
 533         switch (reg) {
 534         case I2S_TXCR:
 535         case I2S_RXCR:
 536         case I2S_CKR:
 537         case I2S_DMACR:
 538         case I2S_INTCR:
 539         case I2S_XFER:
 540         case I2S_CLR:
 541         case I2S_RXDR:
 542         case I2S_FIFOLR:
 543         case I2S_INTSR:
 544                 return true;
 545         default:
 546                 return false;
 547         }
 548 }
 549
 550 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 551 {
 552         switch (reg) {
 553         case I2S_INTSR:
 554         case I2S_CLR:
 555                 return true;
 556         default:
 557                 return false;
 558         }
 559 }
 560
 561 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 562 {
 563         switch (reg) {
 564         default:
 565                 return false;
 566         }
 567 }
 568
 569 static const struct regmap_config rockchip_i2s_regmap_config = {
 570         .reg_bits = 32,
 571         .reg_stride = 4,
 572         .val_bits = 32,
 573         .max_register = I2S_RXDR,
 574         .writeable_reg = rockchip_i2s_wr_reg,
 575         .readable_reg = rockchip_i2s_rd_reg,
 576         .volatile_reg = rockchip_i2s_volatile_reg,
 577         .precious_reg = rockchip_i2s_precious_reg,
 578         .cache_type = REGCACHE_FLAT,
 579 };
 580
 581 static int rockchip_i2s_probe(struct platform_device *pdev)
 582 {
 583         struct device_node *node = pdev->dev.of_node;
 584         struct rk_i2s_dev *i2s;
 585         struct resource *res;
 586         void __iomem *regs;
 587         int ret;
 588
 589         ret = of_property_read_u32(node, "i2s-id", &pdev->id);
 590         if (ret < 0) {
 591                 dev_err(&pdev->dev, "Property 'i2s-id' missing or invalid\n");
 592                 ret = -EINVAL;
 593                 goto err;
 594         }
 595
 596         if (soc_is_rk3126b()) {
 597                 int sdi_src = 0;
 598
 599                 /* rk3126b has no i2s1 controller(i2s_8ch) */
 600                 if (1 == pdev->id) {
 601                         pr_info("rk3126b has no i2s1 controller\n");
 602                         ret = -ENODEV;
 603                         goto err;
 604                 }
 605
 606                 ret = of_property_read_u32(node, "sdi_source",
 607                                            &sdi_src);
 608                 if (ret < 0)
 609                         sdi_src = 0;
 610
 611                 if (1 == sdi_src) {
 612                         int val;
 613
 614                         /*GRF_SOC_CON*/
 615                         val = readl_relaxed(RK_GRF_VIRT + 0x0140);
 616                         val = val | 0x04000400;
 617                         writel_relaxed(val, RK_GRF_VIRT + 0x0140);
 618                 }
 619         }
 620
 621         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 622         if (!i2s) {
 623                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 624                 ret = -ENOMEM;
 625                 goto err;
 626         }
 627
 628         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 629         if (IS_ERR(i2s->hclk)) {
 630                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 631                 ret = PTR_ERR(i2s->hclk);
 632                 goto err;
 633         } else {
 634                 clk_prepare_enable(i2s->hclk);
 635         }
 636
 637         i2s->clk = devm_clk_get(&pdev->dev, "i2s_clk");
 638         if (IS_ERR(i2s->clk)) {
 639                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 640                 ret = PTR_ERR(i2s->clk);
 641                 goto err;
 642         }
 643 #ifdef CLK_SET_LATER
 644         INIT_DELAYED_WORK(&i2s->clk_delayed_work, set_clk_later_work);
 645         schedule_delayed_work(&i2s->clk_delayed_work, msecs_to_jiffies(10));
 646 #else
 647         clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
 648 #endif
 649         clk_prepare_enable(i2s->clk);
 650
 651         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_mclk");
 652         if (IS_ERR(i2s->mclk)) {
 653                 dev_info(&pdev->dev, "i2s%d has no mclk\n", pdev->id);
 654         } else {
 655         #ifndef CLK_SET_LATER
 656                 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
 657         #endif
 658                 clk_prepare_enable(i2s->mclk);
 659         }
 660
 661         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 662         regs = devm_ioremap_resource(&pdev->dev, res);
 663         if (IS_ERR(regs)) {
 664                 ret = PTR_ERR(regs);
 665                 goto err;
 666         }
 667
 668         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 669                                             &rockchip_i2s_regmap_config);
 670         if (IS_ERR(i2s->regmap)) {
 671                 dev_err(&pdev->dev,
 672                         "Failed to initialise managed register map\n");
 673                 ret = PTR_ERR(i2s->regmap);
 674                 goto err;
 675         }
 676
 677         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 678         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 679         i2s->playback_dma_data.maxburst = I2S_DMA_BURST_SIZE;
 680
 681         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 682         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 683         i2s->capture_dma_data.maxburst = I2S_DMA_BURST_SIZE;
 684
 685         i2s->tx_start = false;
 686         i2s->rx_start = false;
 687
 688         i2s->dev = &pdev->dev;
 689         dev_set_drvdata(&pdev->dev, i2s);
 690
 691         pm_runtime_enable(&pdev->dev);
 692         if (!pm_runtime_enabled(&pdev->dev)) {
 693                 ret = rockchip_i2s_runtime_resume(&pdev->dev);
 694                 if (ret)
 695                         goto err_pm_disable;
 696         }
 697
 698         ret = snd_soc_register_component(&pdev->dev, &rockchip_i2s_component,
 699                                          &rockchip_i2s_dai[pdev->id], 1);
 700
 701         if (ret) {
 702                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 703                 ret = -ENOMEM;
 704                 goto err_suspend;
 705         }
 706
 707         ret = rockchip_pcm_platform_register(&pdev->dev);
 708         if (ret) {
 709                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 710                 goto err_unregister_component;
 711         }
 712
 713         ret = of_property_read_u32(node, "rockchip,xfer-mode", &i2s->xfer_mode);
 714         if (ret < 0)
 715                 i2s->xfer_mode = I2S_XFER_MODE;
 716
 717         if (PCM_XFER_MODE == i2s->xfer_mode) {
 718                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 719                                    I2S_TXCR_TFS_MASK,
 720                                    I2S_TXCR_TFS_PCM);
 721                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 722                                    I2S_RXCR_TFS_MASK,
 723                                    I2S_RXCR_TFS_PCM);
 724         }
 725
 726         rockchip_snd_txctrl(i2s, 0);
 727         rockchip_snd_rxctrl(i2s, 0);
 728
 729         return 0;
 730
 731 err_unregister_component:
 732         snd_soc_unregister_component(&pdev->dev);
 733 err_suspend:
 734         if (!pm_runtime_status_suspended(&pdev->dev))
 735                 rockchip_i2s_runtime_suspend(&pdev->dev);
 736 err_pm_disable:
 737         pm_runtime_disable(&pdev->dev);
 738 err:
 739         return ret;
 740 }
 741
 742 static int rockchip_i2s_remove(struct platform_device *pdev)
 743 {
 744         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 745
 746         pm_runtime_disable(&pdev->dev);
 747         if (!pm_runtime_status_suspended(&pdev->dev))
 748                 rockchip_i2s_runtime_suspend(&pdev->dev);
 749
 750         if (!IS_ERR(i2s->mclk))
 751                 clk_disable_unprepare(i2s->mclk);
 752
 753         clk_disable_unprepare(i2s->clk);
 754         clk_disable_unprepare(i2s->hclk);
 755         rockchip_pcm_platform_unregister(&pdev->dev);
 756         snd_soc_unregister_component(&pdev->dev);
 757
 758         return 0;
 759 }
 760
 761 #ifdef CONFIG_OF
 762 static const struct of_device_id rockchip_i2s_match[] = {
 763         { .compatible = "rockchip-i2s", },
 764         {},
 765 };
 766 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
 767 #endif
 768
 769 #ifdef CONFIG_PM_SLEEP
 770 static int rockchip_i2s_suspend(struct device *dev)
 771 {
 772         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 773
 774         dev_dbg(i2s->dev, "%s\n", __func__);
 775         return pinctrl_pm_select_sleep_state(dev);
 776 }
 777
 778 static int rockchip_i2s_resume(struct device *dev)
 779 {
 780         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 781         int ret;
 782
 783         ret = pm_runtime_get_sync(dev);
 784         if (ret < 0)
 785                 return ret;
 786         ret = pinctrl_pm_select_default_state(dev);
 787         if (ret < 0)
 788                 return ret;
 789         ret = regmap_reinit_cache(i2s->regmap, &rockchip_i2s_regmap_config);
 790
 791         if (PCM_XFER_MODE == i2s->xfer_mode) {
 792                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 793                                    I2S_TXCR_TFS_MASK,
 794                                    I2S_TXCR_TFS_PCM);
 795                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 796                                    I2S_RXCR_TFS_MASK,
 797                                    I2S_RXCR_TFS_PCM);
 798         }
 799
 800         pm_runtime_put(dev);
 801
 802         dev_dbg(i2s->dev, "%s\n", __func__);
 803         return ret;
 804 }
 805 #endif
 806
 807 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 808         SET_RUNTIME_PM_OPS(rockchip_i2s_runtime_suspend, rockchip_i2s_runtime_resume,
 809                            NULL)
 810         SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_suspend, rockchip_i2s_resume)
 811 };
 812
 813 static struct platform_driver rockchip_i2s_driver = {
 814         .probe  = rockchip_i2s_probe,
 815         .remove = rockchip_i2s_remove,
 816         .driver = {
 817                 .name   = "rockchip-i2s",
 818                 .owner  = THIS_MODULE,
 819                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 820                 .pm     = &rockchip_i2s_pm_ops,
 821         },
 822 };
 823
 824 static int __init rockchip_i2s_init(void)
 825 {
 826         return platform_driver_register(&rockchip_i2s_driver);
 827 }
 828 subsys_initcall_sync(rockchip_i2s_init);
 829
 830 static void __exit rockchip_i2s_exit(void)
 831 {
 832         platform_driver_unregister(&rockchip_i2s_driver);
 833 }
 834 module_exit(rockchip_i2s_exit);
 835
 836 MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
 837 MODULE_DESCRIPTION("Rockchip I2S Controller Driver");
 838 MODULE_LICENSE("GPL v2");