2 * Rockchip I2S ALSA SoC Digital Audio Interface(DAI) driver
4 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
22 * transmit operation control register
24 #define I2S_TXCR_RCNT_SHIFT 17
25 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
26 #define I2S_TXCR_CSR_SHIFT 15
27 #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
28 #define I2S_TXCR_CHN_2 (0 << I2S_TXCR_CSR_SHIFT)
29 #define I2S_TXCR_CHN_4 (1 << I2S_TXCR_CSR_SHIFT)
30 #define I2S_TXCR_CHN_6 (2 << I2S_TXCR_CSR_SHIFT)
31 #define I2S_TXCR_CHN_8 (3 << I2S_TXCR_CSR_SHIFT)
32 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
33 #define I2S_TXCR_HWT BIT(14)
34 #define I2S_TXCR_SJM_SHIFT 12
35 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
36 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
37 #define I2S_TXCR_FBM_SHIFT 11
38 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
39 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
40 #define I2S_TXCR_IBM_SHIFT 9
41 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
42 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
43 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
44 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
45 #define I2S_TXCR_PBM_SHIFT 7
46 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
47 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
48 #define I2S_TXCR_TFS_SHIFT 5
49 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
50 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
51 #define I2S_TXCR_VDW_SHIFT 0
52 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
53 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
57 * receive operation control register
59 #define I2S_RXCR_HWT BIT(14)
60 #define I2S_RXCR_SJM_SHIFT 12
61 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
62 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
63 #define I2S_RXCR_FBM_SHIFT 11
64 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
65 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
66 #define I2S_RXCR_IBM_SHIFT 9
67 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
68 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
69 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
70 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
71 #define I2S_RXCR_PBM_SHIFT 7
72 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
73 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
74 #define I2S_RXCR_TFS_SHIFT 5
75 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
76 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
77 #define I2S_RXCR_VDW_SHIFT 0
78 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
79 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
83 * clock generation register
85 #define I2S_CKR_MSS_SHIFT 27
86 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
87 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
88 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
89 #define I2S_CKR_CKP_SHIFT 26
90 #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
91 #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
92 #define I2S_CKR_RLP_SHIFT 25
93 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
94 #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
95 #define I2S_CKR_TLP_SHIFT 24
96 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
97 #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
98 #define I2S_CKR_MDIV_SHIFT 16
99 #define I2S_CKR_MDIV(x) ((x) << I2S_CKR_MDIV_SHIFT)
100 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
101 #define I2S_CKR_RSD_SHIFT 8
102 #define I2S_CKR_RSD(x) ((x) << I2S_CKR_RSD_SHIFT)
103 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
104 #define I2S_CKR_TSD_SHIFT 0
105 #define I2S_CKR_TSD(x) ((x) << I2S_CKR_TSD_SHIFT)
106 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
110 * FIFO level register
112 #define I2S_FIFOLR_RFL_SHIFT 24
113 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
114 #define I2S_FIFOLR_TFL3_SHIFT 18
115 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
116 #define I2S_FIFOLR_TFL2_SHIFT 12
117 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
118 #define I2S_FIFOLR_TFL1_SHIFT 6
119 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
120 #define I2S_FIFOLR_TFL0_SHIFT 0
121 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
125 * DMA control register
127 #define I2S_DMACR_RDE_SHIFT 24
128 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
129 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
130 #define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT)
131 #define I2S_DMACR_RDL_SHIFT 16
132 #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
133 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
134 #define I2S_DMACR_TDE_SHIFT 8
135 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
136 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
137 #define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT)
138 #define I2S_DMACR_TDL_SHIFT 0
139 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
140 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
144 * interrupt control register
146 #define I2S_INTCR_RFT_SHIFT 20
147 #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
148 #define I2S_INTCR_RXOIC BIT(18)
149 #define I2S_INTCR_RXOIE_SHIFT 17
150 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
151 #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
152 #define I2S_INTCR_RXFIE_SHIFT 16
153 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
154 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
155 #define I2S_INTCR_TFT_SHIFT 4
156 #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
157 #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
158 #define I2S_INTCR_TXUIC BIT(2)
159 #define I2S_INTCR_TXUIE_SHIFT 1
160 #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
161 #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
165 * interrupt status register
167 #define I2S_INTSR_RXOI_SHIFT 17
168 #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
169 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
170 #define I2S_INTSR_RXFI_SHIFT 16
171 #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
172 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
173 #define I2S_INTSR_TXUI_SHIFT 1
174 #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
175 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
176 #define I2S_INTSR_TXEI_SHIFT 0
177 #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
178 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
182 * Transfer start register
184 #define I2S_XFER_RXS_SHIFT 1
185 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
186 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
187 #define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT)
188 #define I2S_XFER_TXS_SHIFT 0
189 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
190 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
191 #define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT)
195 * clear SCLK domain logic register
197 #define I2S_CLR_RXC BIT(1)
198 #define I2S_CLR_RXC_MASK BIT(1)
199 #define I2S_CLR_TXC BIT(0)
200 #define I2S_CLR_TXC_MASK BIT(0)
203 #define I2S_TXCR (0x0000)
204 #define I2S_RXCR (0x0004)
205 #define I2S_CKR (0x0008)
206 #define I2S_FIFOLR (0x000c)
207 #define I2S_DMACR (0x0010)
208 #define I2S_INTCR (0x0014)
209 #define I2S_INTSR (0x0018)
210 #define I2S_XFER (0x001c)
211 #define I2S_CLR (0x0020)
212 #define I2S_TXDR (0x0024)
213 #define I2S_RXDR (0x0028)
216 #define ROCKCHIP_DIV_MCLK 0
217 #define ROCKCHIP_DIV_BCLK 1
218 #define ROCKCHIP_DIV_PRESCALER 2
221 #define I2S_CHANNEL_8 8
222 #define I2S_CHANNEL_6 6
223 #define I2S_CHANNEL_4 4
224 #define I2S_CHANNEL_2 2
226 #endif /* __RK_I2S_H__ */