1 /*$_FOR_ROCKCHIP_RBOX_$*/
2 /*$_rbox_$_modify_$_huangzhibao for spdif output*/
4 /* sound/soc/rockchip/rk_spdif.c
6 * ALSA SoC Audio Layer - rockchip S/PDIF Controller driver
8 * Copyright (c) 2010 rockchip Electronics Co. Ltd
9 * http://www.rockchip.com/
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/version.h>
24 #include <linux/of_gpio.h>
25 #include <linux/clk.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regmap.h>
30 #include <linux/slab.h>
32 #include <linux/rockchip/iomap.h>
33 #include <linux/rockchip/grf.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/initval.h>
40 #include <sound/soc.h>
41 #include <sound/dmaengine_pcm.h>
44 #include <linux/spinlock.h>
49 #define RK_SPDIF_DBG(x...) printk(KERN_INFO "rk_spdif:"x)
51 #define RK_SPDIF_DBG(x...) do { } while (0)
64 #define SPDIF_CHNSR00_ADDR 0xC0
65 #define SPDIF_CHNSR01_ADDR 0xC4
66 #define SPDIF_CHNSR02_ADDR 0xC8
67 #define SPDIF_CHNSR03_ADDR 0xCC
68 #define SPDIF_CHNSR04_ADDR 0xD0
69 #define SPDIF_CHNSR05_ADDR 0xD4
70 #define SPDIF_CHNSR06_ADDR 0xD8
71 #define SPDIF_CHNSR07_ADDR 0xDC
72 #define SPDIF_CHNSR08_ADDR 0xE0
73 #define SPDIF_CHNSR09_ADDR 0xE4
74 #define SPDIF_CHNSR10_ADDR 0xE8
75 #define SPDIF_CHNSR11_ADDR 0xEC
77 #define SPDIF_BURSTINFO 0x100
78 #define SPDIF_REPETTION 0x104
80 #define DATA_OUTBUF 0x20
82 #define SPDIF_CHANNEL_SEL_8CH ((0x2<<16)|(0x0<<0))
83 #define SPDIF_CHANNEL_SEL_2CH ((0x2<<16)|(0x2<<0))
85 //BURSTINFO bit0:6 //AC-3:0x01, DTS-I -II -III:11,12,13
86 #define BURSTINFO_DATA_TYPE_AC3 0x01
87 #define BURSTINFO_DATA_TYPE_EAC3 0x15
88 #define BURSTINFO_DATA_TYPE_DTS_I 0x0b
90 #define CFGR_MASK 0x0ffffff
91 #define CFGR_VALID_DATA_16bit (00)
92 #define CFGR_VALID_DATA_20bit (01)
93 #define CFGR_VALID_DATA_24bit (10)
94 #define CFGR_VALID_DATA_MASK (11)
96 #define CFGR_HALFWORD_TX_ENABLE (0x1<<2)
97 #define CFGR_HALFWORD_TX_DISABLE (0x0<<2)
98 #define CFGR_HALFWORD_TX_MASK (0x1<<2)
100 #define CFGR_CLK_RATE_MASK (0xFF<<16)
102 #define CFGR_JUSTIFIED_RIGHT (0<<3)
103 #define CFGR_JUSTIFIED_LEFT (1<<3)
104 #define CFGR_JUSTIFIED_MASK (1<<3)
106 //CSE:channel status enable
107 //The bit should be set to 1 when the channel conveys non-linear PCM
108 #define CFGR_CSE_DISABLE (0<<6)
109 #define CFGR_CSE_ENABLE (1<<6)
110 #define CFGR_CSE_MASK (1<<6)
113 #define CFGR_MCLK_CLR (1<<7)
116 #define CFGR_LINEAR_PCM (0<<8)
117 #define CFGR_NON_LINEAR_PCM (1<<8)
118 #define CFGR_LINEAR_MASK (1<<8)
120 //support 7.1 amplifier,new
121 #define CFGR_PRE_CHANGE_ENALBLE (1<<9)
122 #define CFGR_PRE_CHANGE_DISABLE (0<<9)
123 #define CFGR_PRE_CHANGE_MASK (1<<9)
125 #define XFER_TRAN_STOP (0)
126 #define XFER_TRAN_START (1)
127 #define XFER_MASK (1)
129 #define DMACR_TRAN_DMA_DISABLE (0<<5)
130 #define DMACR_TRAN_DMA_ENABLE (1<<5)
131 #define DMACR_TRAN_DMA_CTL_MASK (1<<5)
133 #define DMACR_TRAN_DATA_LEVEL 0x10
134 #define DMACR_TRAN_DATA_LEVEL_MASK 0x1F
135 #define DMACR_TRAN_DMA_MASK 0x3F
137 //Sample Date Buffer empty interrupt enable,new
138 #define INTCR_SDBEIE_DISABLE (0<<4)
139 #define INTCR_SDBEIE_ENABLE (1<<4)
140 #define INTCR_SDBEIE_MASK (1<<4)
143 struct rockchip_spdif_info {
146 unsigned long clk_rate;
148 struct snd_dmaengine_dai_dma_data dma_playback;
151 static inline struct rockchip_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
153 return snd_soc_dai_get_drvdata(cpu_dai);
156 static void spdif_snd_txctrl(struct rockchip_spdif_info *spdif, int on)
158 void __iomem *regs = spdif->regs;
161 RK_SPDIF_DBG( "Entered %s\n", __func__);
163 xfer = readl(regs + XFER) & XFER_MASK;
164 opr = readl(regs + DMACR) & DMACR_TRAN_DMA_MASK & (~DMACR_TRAN_DMA_CTL_MASK);
167 xfer |= XFER_TRAN_START;
168 opr |= DMACR_TRAN_DMA_ENABLE;
169 writel(xfer, regs + XFER);
170 writel(opr, regs + DMACR);
171 RK_SPDIF_DBG("on xfer=0x%x,opr=0x%x\n",readl(regs + XFER),readl(regs + DMACR));
173 xfer &= ~XFER_TRAN_START;
174 opr &= ~DMACR_TRAN_DMA_ENABLE;
175 writel(xfer, regs + XFER);
176 writel(opr, regs + DMACR);
177 writel(1<<7, regs + CFGR);
178 RK_SPDIF_DBG("off xfer=0x%x,opr=0x%x\n",readl(regs + XFER),readl(regs + DMACR));
182 static int spdif_set_syclk(struct snd_soc_dai *cpu_dai,
183 int clk_id, unsigned int freq, int dir)
185 struct rockchip_spdif_info *spdif = to_info(cpu_dai);
187 RK_SPDIF_DBG("Entered %s\n", __func__);
189 spdif->clk_rate = freq;
194 static int spdif_trigger(struct snd_pcm_substream *substream, int cmd,
195 struct snd_soc_dai *dai)
197 struct snd_soc_pcm_runtime *rtd = substream->private_data;
198 struct rockchip_spdif_info *spdif = to_info(rtd->cpu_dai);
201 RK_SPDIF_DBG( "Entered %s\n", __func__);
204 case SNDRV_PCM_TRIGGER_START:
205 case SNDRV_PCM_TRIGGER_RESUME:
206 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
207 spin_lock_irqsave(&spdif->lock, flags);
208 spdif_snd_txctrl(spdif, 1);
209 spin_unlock_irqrestore(&spdif->lock, flags);
211 case SNDRV_PCM_TRIGGER_STOP:
212 case SNDRV_PCM_TRIGGER_SUSPEND:
213 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
214 spin_lock_irqsave(&spdif->lock, flags);
215 spdif_snd_txctrl(spdif, 0);
216 spin_unlock_irqrestore(&spdif->lock, flags);
226 static int spdif_hw_params(struct snd_pcm_substream *substream,
227 struct snd_pcm_hw_params *params,
228 struct snd_soc_dai *dai)
230 struct rockchip_spdif_info *spdif = to_info(dai);
231 void __iomem *regs = spdif->regs;
233 int cfgr, dmac,intcr,chnsr_byte[5]={0};
234 int dataType,ErrFlag,DataLen,DataInfo,BsNum,Repetition,BurstInfo;
236 RK_SPDIF_DBG("Entered %s\n", __func__);
238 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
239 dai->playback_dma_data = &spdif->dma_playback;
241 printk("spdif:Capture is not supported\n");
245 spin_lock_irqsave(&spdif->lock, flags);
247 cfgr = readl(regs + CFGR) & CFGR_VALID_DATA_MASK;
249 cfgr &= ~CFGR_VALID_DATA_MASK;
250 switch (params_format(params)) {
251 case SNDRV_PCM_FORMAT_S16_LE:
252 cfgr |= CFGR_VALID_DATA_16bit;
254 case SNDRV_PCM_FORMAT_S20_3LE :
255 cfgr |= CFGR_VALID_DATA_20bit;
257 case SNDRV_PCM_FORMAT_S24_LE:
258 cfgr |= CFGR_VALID_DATA_24bit;
264 cfgr &= ~CFGR_HALFWORD_TX_MASK;
265 cfgr |= CFGR_HALFWORD_TX_ENABLE;
267 cfgr &= ~CFGR_CLK_RATE_MASK;//set most MCLK:192kHz
270 cfgr &= ~CFGR_JUSTIFIED_MASK;
271 cfgr |= CFGR_JUSTIFIED_RIGHT;
273 cfgr &= ~CFGR_CSE_MASK;
274 cfgr |= CFGR_CSE_DISABLE;
276 cfgr &= ~CFGR_LINEAR_MASK;
277 cfgr |= CFGR_LINEAR_PCM;
278 if(!snd_pcm_format_linear(params_format(params))){//stream type
279 cfgr |= CFGR_NON_LINEAR_PCM;
282 cfgr &= ~CFGR_PRE_CHANGE_MASK;
283 cfgr |= CFGR_PRE_CHANGE_ENALBLE;
285 writel(cfgr, regs + CFGR);
287 intcr = readl(regs + INTCR) & INTCR_SDBEIE_MASK;
288 intcr |= INTCR_SDBEIE_ENABLE;
289 writel(intcr, regs + INTCR);
291 dmac = readl(regs + DMACR) & DMACR_TRAN_DMA_MASK & (~DMACR_TRAN_DATA_LEVEL_MASK);
293 writel(dmac, regs + DMACR);
296 Bit 1 1 Main data field represents linear PCM samples.
297 0 Main data field used for purposes other purposes.
299 chnsr_byte[0]= (0x0)|(0x0<<1)|(0x0<<2)|(0x0<<3)|(0x00<<6);//consumer|pcm|copyright?|pre-emphasis|(0x00<<6);
300 chnsr_byte[1]= (0x0);//category code general mode??
301 chnsr_byte[2]= (0x0)|(0x0<<4)|(0x0<<6);//
302 chnsr_byte[3]= (0x00)|(0x00);//khz;clock acurracy
303 chnsr_byte[4]= (0x0<<4)|(0x01<<1|0x0);//16 bit;
305 if(!snd_pcm_format_linear(params_format(params))){//set stream type
306 chnsr_byte[0] |= (0x1<<1);//set 0:represent main data is linear
307 chnsr_byte[4] = (0x0<<4)|(0x00<<1|0x0);//16 bit;
309 writel((chnsr_byte[4]<<16)|(chnsr_byte[4]),regs+SPDIF_CHNSR02_ADDR);
310 writel((chnsr_byte[3]<<24)|(chnsr_byte[2]<<16)|(chnsr_byte[3]<<8)|(chnsr_byte[2]),regs+SPDIF_CHNSR01_ADDR);
311 writel((chnsr_byte[1]<<24)|(chnsr_byte[0]<<16)|(chnsr_byte[1]<<8)|(chnsr_byte[0]),regs+SPDIF_CHNSR00_ADDR);
313 if(!snd_pcm_format_linear(params_format(params))) {//set non-linear params
314 switch(params_format(params)){
315 case SNDRV_NON_LINEAR_PCM_FORMAT_AC3:
316 //bit0:6 //AC-3:0x01, DTS-I -II -III:11,12,13
317 dataType = BURSTINFO_DATA_TYPE_AC3;
318 //Repetition:AC-3:1536 DTS-I -II -III:512,1024,2048 EAC3:6144
321 case SNDRV_NON_LINEAR_PCM_FORMAT_DTS_I:
322 dataType = BURSTINFO_DATA_TYPE_DTS_I;
325 case SNDRV_NON_LINEAR_PCM_FORMAT_EAC3:
326 dataType = BURSTINFO_DATA_TYPE_EAC3;
333 DataLen=params_period_size(params)*2*16;//bit32:16 //640kbps:0x5000 448kbps:0x3800
336 BurstInfo = (DataLen<<16)|(BsNum<<13)|(DataInfo<<8)|(ErrFlag<<7)|dataType;
337 writel(BurstInfo,regs+SPDIF_BURSTINFO);
338 writel(Repetition,regs+SPDIF_REPETTION);
340 spin_unlock_irqrestore(&spdif->lock, flags);
344 spin_unlock_irqrestore(&spdif->lock, flags);
349 static int spdif_suspend(struct snd_soc_dai *cpu_dai)
351 RK_SPDIF_DBG( "spdif:Entered %s\n", __func__);
356 static int spdif_resume(struct snd_soc_dai *cpu_dai)
358 RK_SPDIF_DBG( "spdif:Entered %s\n", __func__);
363 #define spdif_suspend NULL
364 #define spdif_resume NULL
367 static struct snd_soc_dai_ops spdif_dai_ops = {
368 .set_sysclk = spdif_set_syclk,
369 .trigger = spdif_trigger,
370 .hw_params = spdif_hw_params,
373 struct snd_soc_dai_driver rockchip_spdif_dai = {
374 .name = "rockchip-spdif",
376 .stream_name = "SPDIF Playback",
379 .rates = (SNDRV_PCM_RATE_32000 |
380 SNDRV_PCM_RATE_44100 |
381 SNDRV_PCM_RATE_48000 |
382 SNDRV_PCM_RATE_96000),
383 .formats = SNDRV_PCM_FMTBIT_S16_LE|
384 SNDRV_PCM_FMTBIT_S20_3LE|
385 SNDRV_PCM_FMTBIT_S24_LE, },
386 .ops = &spdif_dai_ops,
387 .suspend = spdif_suspend,
388 .resume = spdif_resume,
391 static const struct snd_soc_component_driver rockchip_spdif_component = {
392 .name = "rockchip-spdif",
395 static int spdif_probe(struct platform_device *pdev)
397 struct resource *mem_res;
398 struct rockchip_spdif_info *spdif;
401 RK_SPDIF_DBG("Entered %s\n", __func__);
403 spdif = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_spdif_info), GFP_KERNEL);
405 dev_err(&pdev->dev, "Can't allocate spdif info\n");
409 spin_lock_init(&spdif->lock);
411 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
413 printk("spdif:Unable to get register resource.\n");
417 spdif->clk= clk_get(&pdev->dev, "spdif_mclk");
418 if (IS_ERR(spdif->clk)) {
419 dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
420 return PTR_ERR(spdif->clk);
422 clk_set_rate(spdif->clk, 12288000);//clk have some problem
423 clk_set_rate(spdif->clk, 11289600);
424 clk_prepare_enable(spdif->clk);
427 /* Request S/PDIF Register's memory region */
428 if (!request_mem_region(mem_res->start,
429 resource_size(mem_res), "rockchip-spdif")) {
430 printk("spdif:Unable to request register region\n");
435 spdif->regs = devm_ioremap(&pdev->dev, mem_res->start, resource_size(mem_res));
437 dev_err(&pdev->dev, "ioremap failed\n");
442 spdif->dma_playback.addr = mem_res->start + DATA_OUTBUF;
443 spdif->dma_playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
444 spdif->dma_playback.maxburst = 4;
446 //set dev name to driver->name for sound card register
447 dev_set_name(&pdev->dev, "%s", pdev->dev.driver->name);
449 ret = snd_soc_register_component(&pdev->dev, &rockchip_spdif_component,
450 &rockchip_spdif_dai, 1);
452 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
457 ret = rockchip_pcm_platform_register(&pdev->dev);
459 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
460 goto err_unregister_component;
463 dev_set_drvdata(&pdev->dev, spdif);
464 writel_relaxed(SPDIF_CHANNEL_SEL_8CH, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
466 RK_SPDIF_DBG("spdif:spdif probe ok!\n");
470 err_unregister_component:
471 snd_soc_unregister_component(&pdev->dev);
477 static int spdif_remove(struct platform_device *pdev)
479 RK_SPDIF_DBG("Entered %s\n", __func__);
481 rockchip_pcm_platform_unregister(&pdev->dev);
482 snd_soc_unregister_component(&pdev->dev);
488 static const struct of_device_id exynos_spdif_match[] = {
489 { .compatible = "rockchip-spdif"},
492 MODULE_DEVICE_TABLE(of, exynos_spdif_match);
495 static struct platform_driver rockchip_spdif_driver = {
496 .probe = spdif_probe,
497 .remove = spdif_remove,
499 .name = "rockchip-spdif",
500 .owner = THIS_MODULE,
501 .of_match_table = of_match_ptr(exynos_spdif_match),
504 module_platform_driver(rockchip_spdif_driver);
506 MODULE_AUTHOR("Seungwhan Youn, <sw.youn@rockchip.com>");
507 MODULE_DESCRIPTION("rockchip S/PDIF Controller Driver");
508 MODULE_LICENSE("GPL");
509 MODULE_ALIAS("platform:rockchip-spdif");