2 * Rockchip S/PDIF ALSA SoC Digital Audio Interface(DAI) driver
4 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/version.h>
25 #include <linux/of_gpio.h>
26 #include <linux/clk.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regmap.h>
31 #include <linux/slab.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/pcm_params.h>
40 #include <sound/initval.h>
41 #include <sound/soc.h>
42 #include <sound/dmaengine_pcm.h>
43 #include <linux/spinlock.h>
47 * channel status register
48 * 192 frame channel status bits: include 384 subframe bits
50 #define SPDIF_CHNSR00_ADDR 0xC0
51 #define SPDIF_CHNSR01_ADDR 0xC4
52 #define SPDIF_CHNSR02_ADDR 0xC8
53 #define SPDIF_CHNSR03_ADDR 0xCC
54 #define SPDIF_CHNSR04_ADDR 0xD0
55 #define SPDIF_CHNSR05_ADDR 0xD4
56 #define SPDIF_CHNSR06_ADDR 0xD8
57 #define SPDIF_CHNSR07_ADDR 0xDC
58 #define SPDIF_CHNSR08_ADDR 0xE0
59 #define SPDIF_CHNSR09_ADDR 0xE4
60 #define SPDIF_CHNSR10_ADDR 0xE8
61 #define SPDIF_CHNSR11_ADDR 0xEC
64 * according to iec958, we only care about
65 * the first meaningful 5 bytes(40 bits)
67 #define CHNSTA_BYTES (5)
68 #define BIT_1_LPCM (0X0<<1)
69 #define BIT_1_NLPCM (0x1<<1)
71 /* sample word length bit 32~35 */
72 #define CHNS_SAMPLE_WORD_LEN_16 (0x2)
73 #define CHNS_SAMPLE_WORD_LEN_24 (0xb)
85 /* transfer configuration register */
86 #define CFGR_VALID_DATA_16bit (0x0 << 0)
87 #define CFGR_VALID_DATA_20bit (0x1 << 0)
88 #define CFGR_VALID_DATA_24bit (0x2 << 0)
89 #define CFGR_VALID_DATA_MASK (0x3 << 0)
90 #define CFGR_HALFWORD_TX_ENABLE (0x1 << 2)
91 #define CFGR_HALFWORD_TX_DISABLE (0x0 << 2)
92 #define CFGR_HALFWORD_TX_MASK (0x1 << 2)
93 #define CFGR_JUSTIFIED_RIGHT (0x0 << 3)
94 #define CFGR_JUSTIFIED_LEFT (0x1 << 3)
95 #define CFGR_JUSTIFIED_MASK (0x1 << 3)
96 #define CFGR_CSE_DISABLE (0x0 << 6)
97 #define CFGR_CSE_ENABLE (0x1 << 6)
98 #define CFGR_CSE_MASK (0x1 << 6)
99 #define CFGR_MCLK_CLR (0x1 << 7)
100 #define CFGR_LINEAR_PCM (0x0 << 8)
101 #define CFGR_NON_LINEAR_PCM (0x1 << 8)
102 #define CFGR_LINEAR_MASK (0x1 << 8)
103 #define CFGR_PRE_CHANGE_ENALBLE (0x1 << 9)
104 #define CFGR_PRE_CHANGE_DISABLE (0x0 << 9)
105 #define CFGR_PRE_CHANGE_MASK (0x1 << 9)
106 #define CFGR_CLK_RATE_MASK (0xFF << 16)
108 /* transfer start register */
109 #define XFER_TRAN_STOP (0x0 << 0)
110 #define XFER_TRAN_START (0x1 << 0)
111 #define XFER_MASK (0x1 << 0)
113 /* dma control register */
114 #define DMACR_TRAN_DMA_DISABLE (0x0 << 5)
115 #define DMACR_TRAN_DMA_ENABLE (0x1 << 5)
116 #define DMACR_TRAN_DMA_CTL_MASK (0x1 << 5)
117 #define DMACR_TRAN_DATA_LEVEL (0x10)
118 #define DMACR_TRAN_DATA_LEVEL_MASK (0x1F)
119 #define DMACR_TRAN_DMA_MASK (0x3F)
120 #define DMA_DATA_LEVEL_16 (0x10)
122 /* interrupt control register */
123 #define INTCR_SDBEIE_DISABLE (0x0 << 4)
124 #define INTCR_SDBEIE_ENABLE (0x1 << 4)
125 #define INTCR_SDBEIE_MASK (0x1 << 4)
127 struct rockchip_spdif_info {
128 spinlock_t lock;/*lock parmeter setting.*/
130 unsigned long clk_rate;
134 struct snd_dmaengine_dai_dma_data dma_playback;
137 static inline struct rockchip_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
139 return snd_soc_dai_get_drvdata(cpu_dai);
142 static void spdif_snd_txctrl(struct rockchip_spdif_info *spdif, int on)
144 void __iomem *regs = spdif->regs;
147 xfer = readl(regs + XFER) & (~XFER_MASK);
148 dmacr = readl(regs + DMACR) & (~DMACR_TRAN_DMA_CTL_MASK);
151 xfer |= XFER_TRAN_START;
152 dmacr |= DMACR_TRAN_DMA_ENABLE;
153 writel(dmacr, regs + DMACR);
154 writel(xfer, regs + XFER);
156 xfer &= XFER_TRAN_STOP;
157 dmacr &= DMACR_TRAN_DMA_DISABLE;
158 writel(xfer, regs + XFER);
159 writel(dmacr, regs + DMACR);
160 writel(CFGR_MCLK_CLR, regs + CFGR);
163 dev_dbg(spdif->dev, "on: %d, xfer = 0x%x, dmacr = 0x%x\n",
164 on, readl(regs + XFER), readl(regs + DMACR));
167 static int spdif_set_syclk(struct snd_soc_dai *cpu_dai, int clk_id,
168 unsigned int freq, int dir)
170 struct rockchip_spdif_info *spdif = to_info(cpu_dai);
172 dev_dbg(spdif->dev, "%s: sysclk = %d\n", __func__, freq);
174 spdif->clk_rate = freq;
175 clk_set_rate(spdif->clk, freq);
180 static int spdif_trigger(struct snd_pcm_substream *substream, int cmd,
181 struct snd_soc_dai *dai)
183 struct snd_soc_pcm_runtime *rtd = substream->private_data;
184 struct rockchip_spdif_info *spdif = to_info(rtd->cpu_dai);
187 dev_dbg(spdif->dev, "%s: cmd: %d\n", __func__, cmd);
190 case SNDRV_PCM_TRIGGER_START:
191 case SNDRV_PCM_TRIGGER_RESUME:
192 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
193 spin_lock_irqsave(&spdif->lock, flags);
194 spdif_snd_txctrl(spdif, 1);
195 spin_unlock_irqrestore(&spdif->lock, flags);
197 case SNDRV_PCM_TRIGGER_STOP:
198 case SNDRV_PCM_TRIGGER_SUSPEND:
199 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
200 spin_lock_irqsave(&spdif->lock, flags);
201 spdif_snd_txctrl(spdif, 0);
202 spin_unlock_irqrestore(&spdif->lock, flags);
211 static int spdif_hw_params(struct snd_pcm_substream *substream,
212 struct snd_pcm_hw_params *params,
213 struct snd_soc_dai *dai)
215 struct rockchip_spdif_info *spdif = to_info(dai);
216 void __iomem *regs = spdif->regs;
218 int cfgr, dmac, intcr, chnsta[CHNSTA_BYTES], chnregval;
220 dev_dbg(spdif->dev, "%s\n", __func__);
222 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
223 dai->playback_dma_data = &spdif->dma_playback;
225 dev_err(spdif->dev, "capture is not supported\n");
229 spin_lock_irqsave(&spdif->lock, flags);
231 cfgr = readl(regs + CFGR);
233 cfgr &= ~CFGR_VALID_DATA_MASK;
234 switch (params_format(params)) {
235 case SNDRV_PCM_FORMAT_S16_LE:
236 cfgr |= CFGR_VALID_DATA_16bit;
238 case SNDRV_PCM_FORMAT_S20_3LE:
239 cfgr |= CFGR_VALID_DATA_20bit;
241 case SNDRV_PCM_FORMAT_S24_LE:
242 cfgr |= CFGR_VALID_DATA_24bit;
248 cfgr &= ~CFGR_HALFWORD_TX_MASK;
249 cfgr |= CFGR_HALFWORD_TX_ENABLE;
251 /* no need divder, let set_syclk care about this */
252 cfgr &= ~CFGR_CLK_RATE_MASK;
255 cfgr &= ~CFGR_JUSTIFIED_MASK;
256 cfgr |= CFGR_JUSTIFIED_RIGHT;
258 cfgr &= ~CFGR_CSE_MASK;
259 cfgr |= CFGR_CSE_ENABLE;
261 cfgr &= ~CFGR_LINEAR_MASK;
262 cfgr |= CFGR_LINEAR_PCM;
264 cfgr &= ~CFGR_PRE_CHANGE_MASK;
265 cfgr |= CFGR_PRE_CHANGE_ENALBLE;
267 writel(cfgr, regs + CFGR);
269 intcr = readl(regs + INTCR) & (~INTCR_SDBEIE_MASK);
270 intcr |= INTCR_SDBEIE_DISABLE;
271 writel(intcr, regs + INTCR);
273 dmac = readl(regs + DMACR) & (~DMACR_TRAN_DATA_LEVEL_MASK);
274 dmac |= DMA_DATA_LEVEL_16;
275 writel(dmac, regs + DMACR);
277 /* channel status bit */
278 memset(chnsta, 0x0, CHNSTA_BYTES);
279 chnsta[0] |= BIT_1_LPCM;
280 chnsta[4] |= CHNS_SAMPLE_WORD_LEN_16;
282 chnregval = (chnsta[4] << 16) | (chnsta[4]);
283 writel(chnregval, regs + SPDIF_CHNSR02_ADDR);
284 chnregval = (chnsta[1] << 24) | (chnsta[0] << 16) |
285 (chnsta[1] << 8) | (chnsta[0]);
286 writel(chnregval, regs + SPDIF_CHNSR00_ADDR);
288 spin_unlock_irqrestore(&spdif->lock, flags);
292 spin_unlock_irqrestore(&spdif->lock, flags);
297 static int spdif_suspend(struct snd_soc_dai *cpu_dai)
299 struct rockchip_spdif_info *spdif = to_info(cpu_dai);
301 dev_dbg(spdif->dev, "%s\n", __func__);
305 static int spdif_resume(struct snd_soc_dai *cpu_dai)
307 struct rockchip_spdif_info *spdif = to_info(cpu_dai);
309 dev_dbg(spdif->dev, "%s\n", __func__);
313 #define spdif_suspend NULL
314 #define spdif_resume NULL
317 static struct snd_soc_dai_ops spdif_dai_ops = {
318 .set_sysclk = spdif_set_syclk,
319 .trigger = spdif_trigger,
320 .hw_params = spdif_hw_params,
323 struct snd_soc_dai_driver rockchip_spdif_dai = {
324 .name = "rockchip-spdif",
326 .stream_name = "SPDIF Playback",
329 .rates = SNDRV_PCM_RATE_8000_192000,
330 .formats = SNDRV_PCM_FMTBIT_S16_LE |
331 SNDRV_PCM_FMTBIT_S20_3LE |
332 SNDRV_PCM_FMTBIT_S24_LE, },
333 .ops = &spdif_dai_ops,
334 .suspend = spdif_suspend,
335 .resume = spdif_resume,
338 static const struct snd_soc_component_driver rockchip_spdif_component = {
339 .name = "rockchip-spdif",
342 static int spdif_probe(struct platform_device *pdev)
344 struct resource *memregion;
345 struct resource *mem_res;
346 struct rockchip_spdif_info *spdif;
349 spdif = devm_kzalloc(&pdev->dev, sizeof(
350 struct rockchip_spdif_info), GFP_KERNEL);
352 dev_err(&pdev->dev, "Can't allocate spdif info\n");
356 spdif->dev = &pdev->dev;
357 platform_set_drvdata(pdev, spdif);
359 spin_lock_init(&spdif->lock);
361 /* get spdif register region. */
362 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 dev_err(&pdev->dev, "No memory resource\n");
368 memregion = devm_request_mem_region(&pdev->dev,
370 resource_size(mem_res),
373 dev_err(&pdev->dev, "Memory region already claimed\n");
377 spdif->regs = devm_ioremap(&pdev->dev,
379 resource_size(memregion));
381 dev_err(&pdev->dev, "ioremap failed\n");
386 /* get spdif clock and init. */
387 spdif->hclk = devm_clk_get(&pdev->dev, "spdif_hclk");
388 if (IS_ERR(spdif->hclk)) {
389 dev_err(&pdev->dev, "Can't retrieve spdif hclk\n");
392 clk_prepare_enable(spdif->hclk);
394 spdif->clk = devm_clk_get(&pdev->dev, "spdif_mclk");
395 if (IS_ERR(spdif->clk)) {
396 dev_err(&pdev->dev, "Can't retrieve spdif mclk\n");
401 clk_set_rate(spdif->clk, 11289600);
402 clk_prepare_enable(spdif->clk);
404 spdif->dma_playback.addr = mem_res->start + SMPDR;
405 spdif->dma_playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
406 spdif->dma_playback.maxburst = 4;
408 ret = snd_soc_register_component(&pdev->dev,
409 &rockchip_spdif_component,
410 &rockchip_spdif_dai, 1);
412 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
417 ret = rockchip_pcm_platform_register(&pdev->dev);
419 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
423 dev_info(&pdev->dev, "spdif ready.\n");
428 platform_set_drvdata(pdev, NULL);
433 static int spdif_remove(struct platform_device *pdev)
435 rockchip_pcm_platform_unregister(&pdev->dev);
436 snd_soc_unregister_component(&pdev->dev);
442 static const struct of_device_id rockchip_spdif_match[] = {
443 { .compatible = "rockchip-spdif", },
446 MODULE_DEVICE_TABLE(of, rockchip_spdif_match);
449 static struct platform_driver rockchip_spdif_driver = {
450 .probe = spdif_probe,
451 .remove = spdif_remove,
453 .name = "rockchip-spdif",
454 .owner = THIS_MODULE,
455 .of_match_table = of_match_ptr(rockchip_spdif_match),
458 module_platform_driver(rockchip_spdif_driver);
460 MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
461 MODULE_DESCRIPTION("Rockchip S/PDIF Controller Driver");
462 MODULE_LICENSE("GPL v2");
463 MODULE_ALIAS("platform:rockchip-spdif");