1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/of_gpio.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_i2s.h"
24 #define DRV_NAME "rockchip-i2s"
32 struct snd_dmaengine_dai_dma_data capture_dma_data;
33 struct snd_dmaengine_dai_dma_data playback_dma_data;
35 struct regmap *regmap;
38 * Used to indicate the tx/rx status.
39 * I2S controller hopes to start the tx and rx together,
40 * also to stop them when they are both try to stop.
47 static int i2s_runtime_suspend(struct device *dev)
49 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
51 clk_disable_unprepare(i2s->mclk);
56 static int i2s_runtime_resume(struct device *dev)
58 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
61 ret = clk_prepare_enable(i2s->mclk);
63 dev_err(i2s->dev, "clock enable failed %d\n", ret);
70 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
72 return snd_soc_dai_get_drvdata(dai);
75 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
81 regmap_update_bits(i2s->regmap, I2S_DMACR,
82 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
84 regmap_update_bits(i2s->regmap, I2S_XFER,
85 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
86 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
90 i2s->tx_start = false;
92 regmap_update_bits(i2s->regmap, I2S_DMACR,
93 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
96 regmap_update_bits(i2s->regmap, I2S_XFER,
102 regmap_update_bits(i2s->regmap, I2S_CLR,
103 I2S_CLR_TXC | I2S_CLR_RXC,
104 I2S_CLR_TXC | I2S_CLR_RXC);
106 regmap_read(i2s->regmap, I2S_CLR, &val);
108 /* Should wait for clear operation to finish */
110 regmap_read(i2s->regmap, I2S_CLR, &val);
113 dev_warn(i2s->dev, "fail to clear\n");
121 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
123 unsigned int val = 0;
127 regmap_update_bits(i2s->regmap, I2S_DMACR,
128 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
130 regmap_update_bits(i2s->regmap, I2S_XFER,
131 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
132 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
134 i2s->rx_start = true;
136 i2s->rx_start = false;
138 regmap_update_bits(i2s->regmap, I2S_DMACR,
139 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
141 if (!i2s->tx_start) {
142 regmap_update_bits(i2s->regmap, I2S_XFER,
148 regmap_update_bits(i2s->regmap, I2S_CLR,
149 I2S_CLR_TXC | I2S_CLR_RXC,
150 I2S_CLR_TXC | I2S_CLR_RXC);
152 regmap_read(i2s->regmap, I2S_CLR, &val);
154 /* Should wait for clear operation to finish */
156 regmap_read(i2s->regmap, I2S_CLR, &val);
159 dev_warn(i2s->dev, "fail to clear\n");
167 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
170 struct rk_i2s_dev *i2s = to_info(cpu_dai);
171 unsigned int mask = 0, val = 0;
173 mask = I2S_CKR_MSS_MASK;
174 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
175 case SND_SOC_DAIFMT_CBS_CFS:
176 /* Set source clock in Master mode */
177 val = I2S_CKR_MSS_MASTER;
178 i2s->is_master_mode = true;
180 case SND_SOC_DAIFMT_CBM_CFM:
181 val = I2S_CKR_MSS_SLAVE;
182 i2s->is_master_mode = false;
188 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
190 mask = I2S_TXCR_IBM_MASK;
191 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
192 case SND_SOC_DAIFMT_RIGHT_J:
193 val = I2S_TXCR_IBM_RSJM;
195 case SND_SOC_DAIFMT_LEFT_J:
196 val = I2S_TXCR_IBM_LSJM;
198 case SND_SOC_DAIFMT_I2S:
199 val = I2S_TXCR_IBM_NORMAL;
205 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
207 mask = I2S_RXCR_IBM_MASK;
208 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
209 case SND_SOC_DAIFMT_RIGHT_J:
210 val = I2S_RXCR_IBM_RSJM;
212 case SND_SOC_DAIFMT_LEFT_J:
213 val = I2S_RXCR_IBM_LSJM;
215 case SND_SOC_DAIFMT_I2S:
216 val = I2S_RXCR_IBM_NORMAL;
222 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
227 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
228 struct snd_pcm_hw_params *params,
229 struct snd_soc_dai *dai)
231 struct rk_i2s_dev *i2s = to_info(dai);
232 struct snd_soc_pcm_runtime *rtd = substream->private_data;
233 unsigned int val = 0;
234 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
236 if (i2s->is_master_mode) {
237 mclk_rate = clk_get_rate(i2s->mclk);
238 bclk_rate = 2 * 32 * params_rate(params);
239 if (bclk_rate && mclk_rate % bclk_rate)
242 div_bclk = mclk_rate / bclk_rate;
243 div_lrck = bclk_rate / params_rate(params);
244 regmap_update_bits(i2s->regmap, I2S_CKR,
246 I2S_CKR_MDIV(div_bclk));
248 regmap_update_bits(i2s->regmap, I2S_CKR,
251 I2S_CKR_TSD(div_lrck) |
252 I2S_CKR_RSD(div_lrck));
255 switch (params_format(params)) {
256 case SNDRV_PCM_FORMAT_S8:
257 val |= I2S_TXCR_VDW(8);
259 case SNDRV_PCM_FORMAT_S16_LE:
260 val |= I2S_TXCR_VDW(16);
262 case SNDRV_PCM_FORMAT_S20_3LE:
263 val |= I2S_TXCR_VDW(20);
265 case SNDRV_PCM_FORMAT_S24_LE:
266 val |= I2S_TXCR_VDW(24);
272 switch (params_channels(params)) {
286 dev_err(i2s->dev, "invalid channel: %d\n",
287 params_channels(params));
291 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
292 regmap_update_bits(i2s->regmap, I2S_RXCR,
293 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
296 regmap_update_bits(i2s->regmap, I2S_TXCR,
297 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
300 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
302 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
305 val = I2S_CKR_TRCM_TXRX;
306 if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
307 val = I2S_CKR_TRCM_TXSHARE;
309 regmap_update_bits(i2s->regmap, I2S_CKR,
315 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
316 int cmd, struct snd_soc_dai *dai)
318 struct rk_i2s_dev *i2s = to_info(dai);
322 case SNDRV_PCM_TRIGGER_START:
323 case SNDRV_PCM_TRIGGER_RESUME:
324 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
325 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
326 rockchip_snd_rxctrl(i2s, 1);
328 rockchip_snd_txctrl(i2s, 1);
330 case SNDRV_PCM_TRIGGER_SUSPEND:
331 case SNDRV_PCM_TRIGGER_STOP:
332 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
333 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
334 rockchip_snd_rxctrl(i2s, 0);
336 rockchip_snd_txctrl(i2s, 0);
346 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
347 unsigned int freq, int dir)
349 struct rk_i2s_dev *i2s = to_info(cpu_dai);
352 ret = clk_set_rate(i2s->mclk, freq);
354 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
359 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
361 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
363 dai->capture_dma_data = &i2s->capture_dma_data;
364 dai->playback_dma_data = &i2s->playback_dma_data;
369 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
370 .hw_params = rockchip_i2s_hw_params,
371 .set_sysclk = rockchip_i2s_set_sysclk,
372 .set_fmt = rockchip_i2s_set_fmt,
373 .trigger = rockchip_i2s_trigger,
376 static struct snd_soc_dai_driver rockchip_i2s_dai = {
377 .probe = rockchip_i2s_dai_probe,
379 .stream_name = "Playback",
382 .rates = SNDRV_PCM_RATE_8000_192000,
383 .formats = (SNDRV_PCM_FMTBIT_S8 |
384 SNDRV_PCM_FMTBIT_S16_LE |
385 SNDRV_PCM_FMTBIT_S20_3LE |
386 SNDRV_PCM_FMTBIT_S24_LE),
389 .stream_name = "Capture",
392 .rates = SNDRV_PCM_RATE_8000_192000,
393 .formats = (SNDRV_PCM_FMTBIT_S8 |
394 SNDRV_PCM_FMTBIT_S16_LE |
395 SNDRV_PCM_FMTBIT_S20_3LE |
396 SNDRV_PCM_FMTBIT_S24_LE),
398 .ops = &rockchip_i2s_dai_ops,
399 .symmetric_rates = 1,
402 static const struct snd_soc_component_driver rockchip_i2s_component = {
406 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
423 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
442 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
453 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
461 static const struct reg_default rockchip_i2s_reg_defaults[] = {
469 static const struct regmap_config rockchip_i2s_regmap_config = {
473 .max_register = I2S_RXDR,
474 .reg_defaults = rockchip_i2s_reg_defaults,
475 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
476 .writeable_reg = rockchip_i2s_wr_reg,
477 .readable_reg = rockchip_i2s_rd_reg,
478 .volatile_reg = rockchip_i2s_volatile_reg,
479 .precious_reg = rockchip_i2s_precious_reg,
480 .cache_type = REGCACHE_FLAT,
483 static int rockchip_i2s_probe(struct platform_device *pdev)
485 struct device_node *node = pdev->dev.of_node;
486 struct rk_i2s_dev *i2s;
487 struct snd_soc_dai_driver *soc_dai;
488 struct resource *res;
493 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
495 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
499 /* try to prepare related clocks */
500 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
501 if (IS_ERR(i2s->hclk)) {
502 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
503 return PTR_ERR(i2s->hclk);
505 ret = clk_prepare_enable(i2s->hclk);
507 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
511 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
512 if (IS_ERR(i2s->mclk)) {
513 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
514 return PTR_ERR(i2s->mclk);
517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
518 regs = devm_ioremap_resource(&pdev->dev, res);
520 return PTR_ERR(regs);
522 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
523 &rockchip_i2s_regmap_config);
524 if (IS_ERR(i2s->regmap)) {
526 "Failed to initialise managed register map\n");
527 return PTR_ERR(i2s->regmap);
530 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
531 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
532 i2s->playback_dma_data.maxburst = 4;
534 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
535 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
536 i2s->capture_dma_data.maxburst = 4;
538 i2s->dev = &pdev->dev;
539 dev_set_drvdata(&pdev->dev, i2s);
541 pm_runtime_enable(&pdev->dev);
542 if (!pm_runtime_enabled(&pdev->dev)) {
543 ret = i2s_runtime_resume(&pdev->dev);
548 soc_dai = devm_kzalloc(&pdev->dev,
549 sizeof(*soc_dai), GFP_KERNEL);
553 memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
554 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
555 if (val >= 2 && val <= 8)
556 soc_dai->playback.channels_max = val;
559 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
560 if (val >= 2 && val <= 8)
561 soc_dai->capture.channels_max = val;
564 ret = devm_snd_soc_register_component(&pdev->dev,
565 &rockchip_i2s_component,
569 dev_err(&pdev->dev, "Could not register DAI\n");
573 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
575 dev_err(&pdev->dev, "Could not register PCM\n");
582 if (!pm_runtime_status_suspended(&pdev->dev))
583 i2s_runtime_suspend(&pdev->dev);
585 pm_runtime_disable(&pdev->dev);
590 static int rockchip_i2s_remove(struct platform_device *pdev)
592 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
594 pm_runtime_disable(&pdev->dev);
595 if (!pm_runtime_status_suspended(&pdev->dev))
596 i2s_runtime_suspend(&pdev->dev);
598 clk_disable_unprepare(i2s->mclk);
599 clk_disable_unprepare(i2s->hclk);
604 static const struct of_device_id rockchip_i2s_match[] = {
605 { .compatible = "rockchip,rk3066-i2s", },
609 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
610 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
614 static struct platform_driver rockchip_i2s_driver = {
615 .probe = rockchip_i2s_probe,
616 .remove = rockchip_i2s_remove,
619 .of_match_table = of_match_ptr(rockchip_i2s_match),
620 .pm = &rockchip_i2s_pm_ops,
623 module_platform_driver(rockchip_i2s_driver);
625 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
626 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
627 MODULE_LICENSE("GPL v2");
628 MODULE_ALIAS("platform:" DRV_NAME);
629 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);