1 /* sound/soc/rockchip/rk_spdif.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
7 * Copyright (c) 2015 Collabora Ltd.
8 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/of_gpio.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <sound/pcm_params.h>
23 #include <sound/dmaengine_pcm.h>
25 #include "rockchip_spdif.h"
34 #define RK3288_GRF_SOC_CON2 0x24c
42 struct snd_dmaengine_dai_dma_data playback_dma_data;
44 struct regmap *regmap;
47 static const struct of_device_id rk_spdif_match[] = {
48 { .compatible = "rockchip,rk3066-spdif",
49 .data = (void *)RK_SPDIF_RK3066 },
50 { .compatible = "rockchip,rk3188-spdif",
51 .data = (void *)RK_SPDIF_RK3188 },
52 { .compatible = "rockchip,rk3288-spdif",
53 .data = (void *)RK_SPDIF_RK3288 },
54 { .compatible = "rockchip,rk3328-spdif",
55 .data = (void *)RK_SPDIF_RK3366 },
56 { .compatible = "rockchip,rk3366-spdif",
57 .data = (void *)RK_SPDIF_RK3366 },
58 { .compatible = "rockchip,rk3368-spdif",
59 .data = (void *)RK_SPDIF_RK3366 },
60 { .compatible = "rockchip,rk3399-spdif",
61 .data = (void *)RK_SPDIF_RK3366 },
64 MODULE_DEVICE_TABLE(of, rk_spdif_match);
66 static int rk_spdif_runtime_suspend(struct device *dev)
68 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
70 clk_disable_unprepare(spdif->mclk);
71 clk_disable_unprepare(spdif->hclk);
76 static int rk_spdif_runtime_resume(struct device *dev)
78 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
81 ret = clk_prepare_enable(spdif->mclk);
83 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
87 ret = clk_prepare_enable(spdif->hclk);
89 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
96 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
97 struct snd_pcm_hw_params *params,
98 struct snd_soc_dai *dai)
100 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
101 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
105 srate = params_rate(params);
110 mclk = 96000 * 128; /* 12288000 hz */
113 mclk = 44100 * 256; /* 11289600 hz */
116 mclk = 192000 * 128; /* 24576000 hz */
122 switch (params_format(params)) {
123 case SNDRV_PCM_FORMAT_S16_LE:
124 val |= SPDIF_CFGR_VDW_16;
126 case SNDRV_PCM_FORMAT_S20_3LE:
127 val |= SPDIF_CFGR_VDW_20;
129 case SNDRV_PCM_FORMAT_S24_LE:
130 val |= SPDIF_CFGR_VDW_24;
136 /* Set clock and calculate divider */
137 ret = clk_set_rate(spdif->mclk, mclk);
139 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
144 val |= SPDIF_CFGR_CLK_DIV(mclk/(srate * 256));
145 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
146 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
153 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
154 int cmd, struct snd_soc_dai *dai)
156 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
160 case SNDRV_PCM_TRIGGER_START:
161 case SNDRV_PCM_TRIGGER_RESUME:
162 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
163 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
164 SPDIF_DMACR_TDE_ENABLE |
165 SPDIF_DMACR_TDL_MASK,
166 SPDIF_DMACR_TDE_ENABLE |
167 SPDIF_DMACR_TDL(16));
172 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
173 SPDIF_XFER_TXS_START,
174 SPDIF_XFER_TXS_START);
176 case SNDRV_PCM_TRIGGER_SUSPEND:
177 case SNDRV_PCM_TRIGGER_STOP:
178 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
179 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
180 SPDIF_DMACR_TDE_ENABLE,
181 SPDIF_DMACR_TDE_DISABLE);
186 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
187 SPDIF_XFER_TXS_START,
188 SPDIF_XFER_TXS_STOP);
198 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
200 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
202 dai->playback_dma_data = &spdif->playback_dma_data;
207 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
208 .hw_params = rk_spdif_hw_params,
209 .trigger = rk_spdif_trigger,
212 static struct snd_soc_dai_driver rk_spdif_dai = {
213 .probe = rk_spdif_dai_probe,
215 .stream_name = "Playback",
218 .rates = (SNDRV_PCM_RATE_32000 |
219 SNDRV_PCM_RATE_44100 |
220 SNDRV_PCM_RATE_48000 |
221 SNDRV_PCM_RATE_96000 |
222 SNDRV_PCM_RATE_192000),
223 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
224 SNDRV_PCM_FMTBIT_S20_3LE |
225 SNDRV_PCM_FMTBIT_S24_LE),
227 .ops = &rk_spdif_dai_ops,
230 static const struct snd_soc_component_driver rk_spdif_component = {
231 .name = "rockchip-spdif",
234 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
248 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
262 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
273 static const struct regmap_config rk_spdif_regmap_config = {
277 .max_register = SPDIF_SMPDR,
278 .writeable_reg = rk_spdif_wr_reg,
279 .readable_reg = rk_spdif_rd_reg,
280 .volatile_reg = rk_spdif_volatile_reg,
281 .cache_type = REGCACHE_FLAT,
284 static int rk_spdif_probe(struct platform_device *pdev)
286 struct device_node *np = pdev->dev.of_node;
287 struct rk_spdif_dev *spdif;
288 const struct of_device_id *match;
289 struct resource *res;
293 match = of_match_node(rk_spdif_match, np);
294 if (match->data == (void *)RK_SPDIF_RK3288) {
297 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
300 "rockchip_spdif missing 'rockchip,grf' \n");
304 /* Select the 8 channel SPDIF solution on RK3288 as
305 * the 2 channel one does not appear to work
307 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
310 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
314 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
315 if (IS_ERR(spdif->hclk)) {
316 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
317 return PTR_ERR(spdif->hclk);
319 ret = clk_prepare_enable(spdif->hclk);
321 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
325 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
326 if (IS_ERR(spdif->mclk)) {
327 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
328 return PTR_ERR(spdif->mclk);
331 ret = clk_prepare_enable(spdif->mclk);
333 dev_err(spdif->dev, "clock enable failed %d\n", ret);
337 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
338 regs = devm_ioremap_resource(&pdev->dev, res);
340 return PTR_ERR(regs);
342 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
343 &rk_spdif_regmap_config);
344 if (IS_ERR(spdif->regmap)) {
346 "Failed to initialise managed register map\n");
347 return PTR_ERR(spdif->regmap);
350 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
351 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
352 spdif->playback_dma_data.maxburst = 4;
354 spdif->dev = &pdev->dev;
355 dev_set_drvdata(&pdev->dev, spdif);
357 pm_runtime_set_active(&pdev->dev);
358 pm_runtime_enable(&pdev->dev);
359 pm_request_idle(&pdev->dev);
361 ret = devm_snd_soc_register_component(&pdev->dev,
365 dev_err(&pdev->dev, "Could not register DAI\n");
369 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
371 dev_err(&pdev->dev, "Could not register PCM\n");
378 pm_runtime_disable(&pdev->dev);
383 static int rk_spdif_remove(struct platform_device *pdev)
385 struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
387 pm_runtime_disable(&pdev->dev);
388 if (!pm_runtime_status_suspended(&pdev->dev))
389 rk_spdif_runtime_suspend(&pdev->dev);
391 clk_disable_unprepare(spdif->mclk);
392 clk_disable_unprepare(spdif->hclk);
397 #ifdef CONFIG_PM_SLEEP
398 static int rockchip_spdif_suspend(struct device *dev)
400 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
402 regcache_mark_dirty(spdif->regmap);
407 static int rockchip_spdif_resume(struct device *dev)
409 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
412 ret = pm_runtime_get_sync(dev);
415 ret = regcache_sync(spdif->regmap);
422 static const struct dev_pm_ops rk_spdif_pm_ops = {
423 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
425 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spdif_suspend, rockchip_spdif_resume)
428 static struct platform_driver rk_spdif_driver = {
429 .probe = rk_spdif_probe,
430 .remove = rk_spdif_remove,
432 .name = "rockchip-spdif",
433 .of_match_table = of_match_ptr(rk_spdif_match),
434 .pm = &rk_spdif_pm_ops,
437 module_platform_driver(rk_spdif_driver);
439 MODULE_ALIAS("platform:rockchip-spdif");
440 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
441 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
442 MODULE_LICENSE("GPL v2");