1 /* sound/soc/samsung/ac97.c
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassisinghbrar@gmail.com>
8 * Credits: Graeme Gregory, Sean Choi
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/module.h>
20 #include <sound/soc.h>
22 #include "regs-ac97.h"
23 #include <linux/platform_data/asoc-s3c.h>
27 #define AC_CMD_ADDR(x) (x << 16)
28 #define AC_CMD_DATA(x) (x & 0xffff)
30 #define S3C_AC97_DAI_PCM 0
31 #define S3C_AC97_DAI_MIC 1
33 struct s3c_ac97_info {
37 struct completion done;
39 static struct s3c_ac97_info s3c_ac97;
41 static struct s3c_dma_params s3c_ac97_pcm_out = {
45 static struct s3c_dma_params s3c_ac97_pcm_in = {
49 static struct s3c_dma_params s3c_ac97_mic_in = {
53 static void s3c_ac97_activate(struct snd_ac97 *ac97)
57 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
58 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
59 return; /* Return if already active */
61 reinit_completion(&s3c_ac97.done);
63 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
64 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
65 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
68 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
69 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
72 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
73 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
74 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
76 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
77 pr_err("AC97: Unable to activate!");
80 static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
83 u32 ac_glbctrl, ac_codec_cmd;
86 mutex_lock(&s3c_ac97.lock);
88 s3c_ac97_activate(ac97);
90 reinit_completion(&s3c_ac97.done);
92 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
93 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
94 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
98 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
99 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
100 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
102 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
103 pr_err("AC97: Unable to read!");
105 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
106 addr = (stat >> 16) & 0x7f;
107 data = (stat & 0xffff);
110 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
113 mutex_unlock(&s3c_ac97.lock);
115 return (unsigned short)data;
118 static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
121 u32 ac_glbctrl, ac_codec_cmd;
123 mutex_lock(&s3c_ac97.lock);
125 s3c_ac97_activate(ac97);
127 reinit_completion(&s3c_ac97.done);
129 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
130 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
131 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
135 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
136 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
137 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
139 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
140 pr_err("AC97: Unable to write!");
142 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
143 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
144 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
146 mutex_unlock(&s3c_ac97.lock);
149 static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
151 pr_debug("AC97: Cold reset\n");
152 writel(S3C_AC97_GLBCTRL_COLDRESET,
153 s3c_ac97.regs + S3C_AC97_GLBCTRL);
156 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
160 static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
164 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
165 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
166 return; /* Return if already active */
168 pr_debug("AC97: Warm reset\n");
170 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
173 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
176 s3c_ac97_activate(ac97);
179 static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
181 u32 ac_glbctrl, ac_glbstat;
183 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
185 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
187 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
188 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
189 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
191 complete(&s3c_ac97.done);
194 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
195 ac_glbctrl |= (1<<30); /* Clear interrupt */
196 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
201 static struct snd_ac97_bus_ops s3c_ac97_ops = {
202 .read = s3c_ac97_read,
203 .write = s3c_ac97_write,
204 .warm_reset = s3c_ac97_warm_reset,
205 .reset = s3c_ac97_cold_reset,
208 static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
209 struct snd_soc_dai *dai)
213 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
214 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
215 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
217 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
220 case SNDRV_PCM_TRIGGER_START:
221 case SNDRV_PCM_TRIGGER_RESUME:
222 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
223 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
224 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
226 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
229 case SNDRV_PCM_TRIGGER_STOP:
230 case SNDRV_PCM_TRIGGER_SUSPEND:
231 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
235 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
240 static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
241 int cmd, struct snd_soc_dai *dai)
245 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
246 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
249 case SNDRV_PCM_TRIGGER_START:
250 case SNDRV_PCM_TRIGGER_RESUME:
251 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
252 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
255 case SNDRV_PCM_TRIGGER_STOP:
256 case SNDRV_PCM_TRIGGER_SUSPEND:
257 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
261 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
266 static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
267 .trigger = s3c_ac97_trigger,
270 static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
271 .trigger = s3c_ac97_mic_trigger,
274 static int s3c_ac97_dai_probe(struct snd_soc_dai *dai)
276 samsung_asoc_init_dma_data(dai, &s3c_ac97_pcm_out, &s3c_ac97_pcm_in);
281 static int s3c_ac97_mic_dai_probe(struct snd_soc_dai *dai)
283 samsung_asoc_init_dma_data(dai, NULL, &s3c_ac97_mic_in);
288 static struct snd_soc_dai_driver s3c_ac97_dai[] = {
289 [S3C_AC97_DAI_PCM] = {
290 .name = "samsung-ac97",
293 .stream_name = "AC97 Playback",
296 .rates = SNDRV_PCM_RATE_8000_48000,
297 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
299 .stream_name = "AC97 Capture",
302 .rates = SNDRV_PCM_RATE_8000_48000,
303 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
304 .probe = s3c_ac97_dai_probe,
305 .ops = &s3c_ac97_dai_ops,
307 [S3C_AC97_DAI_MIC] = {
308 .name = "samsung-ac97-mic",
311 .stream_name = "AC97 Mic Capture",
314 .rates = SNDRV_PCM_RATE_8000_48000,
315 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
316 .probe = s3c_ac97_mic_dai_probe,
317 .ops = &s3c_ac97_mic_dai_ops,
321 static const struct snd_soc_component_driver s3c_ac97_component = {
325 static int s3c_ac97_probe(struct platform_device *pdev)
327 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
328 struct s3c_audio_pdata *ac97_pdata;
331 ac97_pdata = pdev->dev.platform_data;
332 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
333 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
337 /* Check for availability of necessary resource */
338 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
340 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
344 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
346 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
350 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
352 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
356 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
358 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
362 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 s3c_ac97.regs = devm_ioremap_resource(&pdev->dev, mem_res);
364 if (IS_ERR(s3c_ac97.regs))
365 return PTR_ERR(s3c_ac97.regs);
367 s3c_ac97_pcm_out.channel = dmatx_res->start;
368 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
369 s3c_ac97_pcm_in.channel = dmarx_res->start;
370 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
371 s3c_ac97_mic_in.channel = dmamic_res->start;
372 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
374 init_completion(&s3c_ac97.done);
375 mutex_init(&s3c_ac97.lock);
377 s3c_ac97.ac97_clk = devm_clk_get(&pdev->dev, "ac97");
378 if (IS_ERR(s3c_ac97.ac97_clk)) {
379 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
383 clk_prepare_enable(s3c_ac97.ac97_clk);
385 if (ac97_pdata->cfg_gpio(pdev)) {
386 dev_err(&pdev->dev, "Unable to configure gpio\n");
391 ret = request_irq(irq_res->start, s3c_ac97_irq,
394 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
398 ret = snd_soc_set_ac97_ops(&s3c_ac97_ops);
400 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
404 ret = devm_snd_soc_register_component(&pdev->dev, &s3c_ac97_component,
405 s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
409 ret = samsung_asoc_dma_platform_register(&pdev->dev);
411 dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
417 free_irq(irq_res->start, NULL);
420 clk_disable_unprepare(s3c_ac97.ac97_clk);
422 snd_soc_set_ac97_ops(NULL);
426 static int s3c_ac97_remove(struct platform_device *pdev)
428 struct resource *irq_res;
430 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
432 free_irq(irq_res->start, NULL);
434 clk_disable_unprepare(s3c_ac97.ac97_clk);
435 snd_soc_set_ac97_ops(NULL);
440 static struct platform_driver s3c_ac97_driver = {
441 .probe = s3c_ac97_probe,
442 .remove = s3c_ac97_remove,
444 .name = "samsung-ac97",
448 module_platform_driver(s3c_ac97_driver);
450 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
451 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
452 MODULE_LICENSE("GPL");
453 MODULE_ALIAS("platform:samsung-ac97");