2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
83 #define BP (1 << 4) /* Fix the signal of Biphase output */
84 #define SE (1 << 0) /* Fix the master clock */
87 #define B_CLK 0x00000010
88 #define A_CLK 0x00000001
90 /* IO SHIFT / MACRO */
95 #define AB_IO(param, shift) (param << shift)
98 #define PBSR (1 << 12) /* Port B Software Reset */
99 #define PASR (1 << 8) /* Port A Software Reset */
100 #define IR (1 << 4) /* Interrupt Reset */
101 #define FSISR (1 << 0) /* Software Reset */
104 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
105 /* 1: Biphase and serial */
108 #define FIFO_SZ_MASK 0x7
110 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
112 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115 * FSI driver use below type name for variable
117 * xxx_len : data length
118 * xxx_width : data width
119 * xxx_offset : data offset
120 * xxx_num : number of data
128 struct snd_pcm_substream *substream;
144 struct fsi_master *master;
146 struct fsi_stream playback;
147 struct fsi_stream capture;
165 struct fsi_priv fsia;
166 struct fsi_priv fsib;
167 struct fsi_core *core;
168 struct sh_fsi_platform_info *info;
173 * basic read write function
176 static void __fsi_reg_write(u32 reg, u32 data)
178 /* valid data area is 24bit */
181 __raw_writel(data, reg);
184 static u32 __fsi_reg_read(u32 reg)
186 return __raw_readl(reg);
189 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
191 u32 val = __fsi_reg_read(reg);
196 __fsi_reg_write(reg, val);
199 #define fsi_reg_write(p, r, d)\
200 __fsi_reg_write((u32)(p->base + REG_##r), d)
202 #define fsi_reg_read(p, r)\
203 __fsi_reg_read((u32)(p->base + REG_##r))
205 #define fsi_reg_mask_set(p, r, m, d)\
206 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
208 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
209 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
210 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
215 spin_lock_irqsave(&master->lock, flags);
216 ret = __fsi_reg_read((u32)(master->base + reg));
217 spin_unlock_irqrestore(&master->lock, flags);
222 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
223 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
224 static void _fsi_master_mask_set(struct fsi_master *master,
225 u32 reg, u32 mask, u32 data)
229 spin_lock_irqsave(&master->lock, flags);
230 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
231 spin_unlock_irqrestore(&master->lock, flags);
238 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
243 static int fsi_is_port_a(struct fsi_priv *fsi)
245 return fsi->master->base == fsi->base;
248 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
250 struct snd_soc_pcm_runtime *rtd = substream->private_data;
255 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
257 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
260 return &master->fsia;
262 return &master->fsib;
265 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
267 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
270 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
272 int is_porta = fsi_is_port_a(fsi);
273 struct fsi_master *master = fsi_get_master(fsi);
275 return is_porta ? master->info->porta_flags :
276 master->info->portb_flags;
279 static inline int fsi_stream_is_play(int stream)
281 return stream == SNDRV_PCM_STREAM_PLAYBACK;
284 static inline int fsi_is_play(struct snd_pcm_substream *substream)
286 return fsi_stream_is_play(substream->stream);
289 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
292 return is_play ? &fsi->playback : &fsi->capture;
295 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
298 u32 flags = fsi_get_info_flags(fsi);
300 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
307 return (mode & flags) != mode;
310 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
312 int is_porta = fsi_is_port_a(fsi);
316 shift = is_play ? AO_SHIFT : AI_SHIFT;
318 shift = is_play ? BO_SHIFT : BI_SHIFT;
323 static void fsi_stream_push(struct fsi_priv *fsi,
325 struct snd_pcm_substream *substream,
329 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
331 io->substream = substream;
332 io->buff_len = buffer_len;
334 io->period_len = period_len;
336 io->oerr_num = -1; /* ignore 1st err */
337 io->uerr_num = -1; /* ignore 1st err */
340 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
342 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
343 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
346 if (io->oerr_num > 0)
347 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
349 if (io->uerr_num > 0)
350 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
352 io->substream = NULL;
361 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
364 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
368 fsi_reg_read(fsi, DOFF_ST) :
369 fsi_reg_read(fsi, DIFF_ST);
371 data_num = 0x1ff & (status >> 8);
372 data_num *= io->chan_num;
377 static int fsi_len2num(int len, int width)
382 #define fsi_num2offset(a, b) fsi_num2len(a, b)
383 static int fsi_num2len(int num, int width)
388 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
390 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
391 struct snd_pcm_substream *substream = io->substream;
392 struct snd_pcm_runtime *runtime = substream->runtime;
394 return frames_to_bytes(runtime, 1) / io->chan_num;
397 static void fsi_count_fifo_err(struct fsi_priv *fsi)
399 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
400 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
402 if (ostatus & ERR_OVER)
403 fsi->playback.oerr_num++;
405 if (ostatus & ERR_UNDER)
406 fsi->playback.uerr_num++;
408 if (istatus & ERR_OVER)
409 fsi->capture.oerr_num++;
411 if (istatus & ERR_UNDER)
412 fsi->capture.uerr_num++;
414 fsi_reg_write(fsi, DOFF_ST, 0);
415 fsi_reg_write(fsi, DIFF_ST, 0);
422 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
424 int is_play = fsi_stream_is_play(stream);
425 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
427 return io->substream->runtime->dma_area + io->buff_offset;
430 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
435 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
437 for (i = 0; i < num; i++)
438 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
441 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
446 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
449 for (i = 0; i < num; i++)
450 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
453 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
458 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
461 for (i = 0; i < num; i++)
462 fsi_reg_write(fsi, DODT, *(start + i));
465 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
470 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
472 for (i = 0; i < num; i++)
473 *(start + i) = fsi_reg_read(fsi, DIDT);
480 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
482 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
483 struct fsi_master *master = fsi_get_master(fsi);
485 fsi_core_mask_set(master, imsk, data, data);
486 fsi_core_mask_set(master, iemsk, data, data);
489 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
491 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
492 struct fsi_master *master = fsi_get_master(fsi);
494 fsi_core_mask_set(master, imsk, data, 0);
495 fsi_core_mask_set(master, iemsk, data, 0);
498 static u32 fsi_irq_get_status(struct fsi_master *master)
500 return fsi_core_read(master, int_st);
503 static void fsi_irq_clear_status(struct fsi_priv *fsi)
506 struct fsi_master *master = fsi_get_master(fsi);
508 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
509 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
511 /* clear interrupt factor */
512 fsi_core_mask_set(master, int_st, data, 0);
516 * SPDIF master clock function
518 * These functions are used later FSI2
520 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
522 struct fsi_master *master = fsi_get_master(fsi);
525 if (master->core->ver < 2) {
526 pr_err("fsi: register access err (%s)\n", __func__);
531 val = enable ? mask : 0;
534 fsi_core_mask_set(master, a_mclk, mask, val) :
535 fsi_core_mask_set(master, b_mclk, mask, val);
542 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
544 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
545 struct fsi_master *master = fsi_get_master(fsi);
548 fsi_master_mask_set(master, CLK_RST, val, val);
550 fsi_master_mask_set(master, CLK_RST, val, 0);
553 static void fsi_fifo_init(struct fsi_priv *fsi,
555 struct snd_soc_dai *dai)
557 struct fsi_master *master = fsi_get_master(fsi);
558 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
561 /* get on-chip RAM capacity */
562 shift = fsi_master_read(master, FIFO_SZ);
563 shift >>= fsi_get_port_shift(fsi, is_play);
564 shift &= FIFO_SZ_MASK;
565 io->fifo_max_num = 256 << shift;
566 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
569 * The maximum number of sample data varies depending
570 * on the number of channels selected for the format.
572 * FIFOs are used in 4-channel units in 3-channel mode
573 * and in 8-channel units in 5- to 7-channel mode
574 * meaning that more FIFOs than the required size of DPRAM
577 * ex) if 256 words of DP-RAM is connected
578 * 1 channel: 256 (256 x 1 = 256)
579 * 2 channels: 128 (128 x 2 = 256)
580 * 3 channels: 64 ( 64 x 3 = 192)
581 * 4 channels: 64 ( 64 x 4 = 256)
582 * 5 channels: 32 ( 32 x 5 = 160)
583 * 6 channels: 32 ( 32 x 6 = 192)
584 * 7 channels: 32 ( 32 x 7 = 224)
585 * 8 channels: 32 ( 32 x 8 = 256)
587 for (i = 1; i < io->chan_num; i <<= 1)
588 io->fifo_max_num >>= 1;
589 dev_dbg(dai->dev, "%d channel %d store\n",
590 io->chan_num, io->fifo_max_num);
593 * set interrupt generation factor
597 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
598 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
600 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
601 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
605 static void fsi_soft_all_reset(struct fsi_master *master)
608 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
612 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
613 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
617 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
619 struct snd_pcm_runtime *runtime;
620 struct snd_pcm_substream *substream = NULL;
621 int is_play = fsi_stream_is_play(stream);
622 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
623 int data_residue_num;
628 void (*fn)(struct fsi_priv *fsi, int size);
632 !io->substream->runtime)
636 substream = io->substream;
637 runtime = substream->runtime;
639 /* FSI FIFO has limit.
640 * So, this driver can not send periods data at a time
642 if (io->buff_offset >=
643 fsi_num2offset(io->period_num + 1, io->period_len)) {
646 io->period_num = (io->period_num + 1) % runtime->periods;
648 if (0 == io->period_num)
652 /* get 1 channel data width */
653 ch_width = fsi_get_frame_width(fsi, is_play);
655 /* get residue data number of alsa */
656 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
663 * data_num_max : number of FSI fifo free space
664 * data_num : number of ALSA residue data
666 data_num_max = io->fifo_max_num * io->chan_num;
667 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
669 data_num = data_residue_num;
673 fn = fsi_dma_soft_push16;
676 fn = fsi_dma_soft_push32;
685 * data_num_max : number of ALSA free space
686 * data_num : number of data in FSI fifo
688 data_num_max = data_residue_num;
689 data_num = fsi_get_fifo_data_num(fsi, is_play);
693 fn = fsi_dma_soft_pop16;
696 fn = fsi_dma_soft_pop32;
703 data_num = min(data_num, data_num_max);
707 /* update buff_offset */
708 io->buff_offset += fsi_num2offset(data_num, ch_width);
711 snd_pcm_period_elapsed(substream);
716 static int fsi_data_pop(struct fsi_priv *fsi)
718 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
721 static int fsi_data_push(struct fsi_priv *fsi)
723 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
726 static irqreturn_t fsi_interrupt(int irq, void *data)
728 struct fsi_master *master = data;
729 u32 int_st = fsi_irq_get_status(master);
731 /* clear irq status */
732 fsi_master_mask_set(master, SOFT_RST, IR, 0);
733 fsi_master_mask_set(master, SOFT_RST, IR, IR);
735 if (int_st & AB_IO(1, AO_SHIFT))
736 fsi_data_push(&master->fsia);
737 if (int_st & AB_IO(1, BO_SHIFT))
738 fsi_data_push(&master->fsib);
739 if (int_st & AB_IO(1, AI_SHIFT))
740 fsi_data_pop(&master->fsia);
741 if (int_st & AB_IO(1, BI_SHIFT))
742 fsi_data_pop(&master->fsib);
744 fsi_count_fifo_err(&master->fsia);
745 fsi_count_fifo_err(&master->fsib);
747 fsi_irq_clear_status(&master->fsia);
748 fsi_irq_clear_status(&master->fsib);
757 static int fsi_dai_startup(struct snd_pcm_substream *substream,
758 struct snd_soc_dai *dai)
760 struct fsi_priv *fsi = fsi_get_priv(substream);
761 struct fsi_master *master = fsi_get_master(fsi);
762 struct fsi_stream *io;
763 u32 flags = fsi_get_info_flags(fsi);
766 int is_play = fsi_is_play(substream);
769 io = fsi_get_stream(fsi, is_play);
771 pm_runtime_get_sync(dai->dev);
774 data = is_play ? (1 << 0) : (1 << 4);
775 is_master = fsi_is_master_mode(fsi, is_play);
777 fsi_reg_mask_set(fsi, CKG1, data, data);
779 fsi_reg_mask_set(fsi, CKG1, data, 0);
781 /* clock inversion (CKG2) */
783 if (SH_FSI_LRM_INV & flags)
785 if (SH_FSI_BRM_INV & flags)
787 if (SH_FSI_LRS_INV & flags)
789 if (SH_FSI_BRS_INV & flags)
792 fsi_reg_write(fsi, CKG2, data);
796 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
798 case SH_FSI_FMT_MONO:
802 case SH_FSI_FMT_MONO_DELAY:
815 io->chan_num = is_play ?
816 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
817 data = CR_TDM | (io->chan_num - 1);
819 case SH_FSI_FMT_TDM_DELAY:
820 io->chan_num = is_play ?
821 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
822 data = CR_TDM_D | (io->chan_num - 1);
824 case SH_FSI_FMT_SPDIF:
825 if (master->core->ver < 2) {
826 dev_err(dai->dev, "This FSI can not use SPDIF\n");
829 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
831 fsi_spdif_clk_ctrl(fsi, 1);
832 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
835 dev_err(dai->dev, "unknown format.\n");
839 fsi_reg_write(fsi, DO_FMT, data) :
840 fsi_reg_write(fsi, DI_FMT, data);
843 fsi_irq_disable(fsi, is_play);
844 fsi_irq_clear_status(fsi);
847 fsi_fifo_init(fsi, is_play, dai);
852 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
853 struct snd_soc_dai *dai)
855 struct fsi_priv *fsi = fsi_get_priv(substream);
856 int is_play = fsi_is_play(substream);
857 struct fsi_master *master = fsi_get_master(fsi);
858 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
860 fsi_irq_disable(fsi, is_play);
861 fsi_clk_ctrl(fsi, 0);
863 set_rate = master->info->set_rate;
864 if (set_rate && fsi->rate)
865 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
868 pm_runtime_put_sync(dai->dev);
871 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
872 struct snd_soc_dai *dai)
874 struct fsi_priv *fsi = fsi_get_priv(substream);
875 struct snd_pcm_runtime *runtime = substream->runtime;
876 int is_play = fsi_is_play(substream);
880 case SNDRV_PCM_TRIGGER_START:
881 fsi_stream_push(fsi, is_play, substream,
882 frames_to_bytes(runtime, runtime->buffer_size),
883 frames_to_bytes(runtime, runtime->period_size));
884 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
885 fsi_irq_enable(fsi, is_play);
887 case SNDRV_PCM_TRIGGER_STOP:
888 fsi_irq_disable(fsi, is_play);
889 fsi_stream_pop(fsi, is_play);
896 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
897 struct snd_pcm_hw_params *params,
898 struct snd_soc_dai *dai)
900 struct fsi_priv *fsi = fsi_get_priv(substream);
901 struct fsi_master *master = fsi_get_master(fsi);
902 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
903 int fsi_ver = master->core->ver;
904 long rate = params_rate(params);
907 set_rate = master->info->set_rate;
911 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
912 if (ret < 0) /* error */
919 switch (ret & SH_FSI_ACKMD_MASK) {
922 case SH_FSI_ACKMD_512:
925 case SH_FSI_ACKMD_256:
928 case SH_FSI_ACKMD_128:
931 case SH_FSI_ACKMD_64:
934 case SH_FSI_ACKMD_32:
936 dev_err(dai->dev, "unsupported ACKMD\n");
942 switch (ret & SH_FSI_BPFMD_MASK) {
945 case SH_FSI_BPFMD_32:
948 case SH_FSI_BPFMD_64:
951 case SH_FSI_BPFMD_128:
954 case SH_FSI_BPFMD_256:
957 case SH_FSI_BPFMD_512:
960 case SH_FSI_BPFMD_16:
962 dev_err(dai->dev, "unsupported ACKMD\n");
968 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
970 fsi_clk_ctrl(fsi, 1);
978 static struct snd_soc_dai_ops fsi_dai_ops = {
979 .startup = fsi_dai_startup,
980 .shutdown = fsi_dai_shutdown,
981 .trigger = fsi_dai_trigger,
982 .hw_params = fsi_dai_hw_params,
989 static struct snd_pcm_hardware fsi_pcm_hardware = {
990 .info = SNDRV_PCM_INFO_INTERLEAVED |
991 SNDRV_PCM_INFO_MMAP |
992 SNDRV_PCM_INFO_MMAP_VALID |
993 SNDRV_PCM_INFO_PAUSE,
1000 .buffer_bytes_max = 64 * 1024,
1001 .period_bytes_min = 32,
1002 .period_bytes_max = 8192,
1008 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1010 struct snd_pcm_runtime *runtime = substream->runtime;
1013 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1015 ret = snd_pcm_hw_constraint_integer(runtime,
1016 SNDRV_PCM_HW_PARAM_PERIODS);
1021 static int fsi_hw_params(struct snd_pcm_substream *substream,
1022 struct snd_pcm_hw_params *hw_params)
1024 return snd_pcm_lib_malloc_pages(substream,
1025 params_buffer_bytes(hw_params));
1028 static int fsi_hw_free(struct snd_pcm_substream *substream)
1030 return snd_pcm_lib_free_pages(substream);
1033 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1035 struct snd_pcm_runtime *runtime = substream->runtime;
1036 struct fsi_priv *fsi = fsi_get_priv(substream);
1037 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1040 location = (io->buff_offset - 1);
1044 return bytes_to_frames(runtime, location);
1047 static struct snd_pcm_ops fsi_pcm_ops = {
1048 .open = fsi_pcm_open,
1049 .ioctl = snd_pcm_lib_ioctl,
1050 .hw_params = fsi_hw_params,
1051 .hw_free = fsi_hw_free,
1052 .pointer = fsi_pointer,
1059 #define PREALLOC_BUFFER (32 * 1024)
1060 #define PREALLOC_BUFFER_MAX (32 * 1024)
1062 static void fsi_pcm_free(struct snd_pcm *pcm)
1064 snd_pcm_lib_preallocate_free_for_all(pcm);
1067 static int fsi_pcm_new(struct snd_card *card,
1068 struct snd_soc_dai *dai,
1069 struct snd_pcm *pcm)
1072 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1073 * in MMAP mode (i.e. aplay -M)
1075 return snd_pcm_lib_preallocate_pages_for_all(
1077 SNDRV_DMA_TYPE_CONTINUOUS,
1078 snd_dma_continuous_data(GFP_KERNEL),
1079 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1086 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1091 .formats = FSI_FMTS,
1097 .formats = FSI_FMTS,
1101 .ops = &fsi_dai_ops,
1107 .formats = FSI_FMTS,
1113 .formats = FSI_FMTS,
1117 .ops = &fsi_dai_ops,
1121 static struct snd_soc_platform_driver fsi_soc_platform = {
1122 .ops = &fsi_pcm_ops,
1123 .pcm_new = fsi_pcm_new,
1124 .pcm_free = fsi_pcm_free,
1131 static int fsi_probe(struct platform_device *pdev)
1133 struct fsi_master *master;
1134 const struct platform_device_id *id_entry;
1135 struct resource *res;
1139 id_entry = pdev->id_entry;
1141 dev_err(&pdev->dev, "unknown fsi device\n");
1145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 irq = platform_get_irq(pdev, 0);
1147 if (!res || (int)irq <= 0) {
1148 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1153 master = kzalloc(sizeof(*master), GFP_KERNEL);
1155 dev_err(&pdev->dev, "Could not allocate master\n");
1160 master->base = ioremap_nocache(res->start, resource_size(res));
1161 if (!master->base) {
1163 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1167 /* master setting */
1169 master->info = pdev->dev.platform_data;
1170 master->core = (struct fsi_core *)id_entry->driver_data;
1171 spin_lock_init(&master->lock);
1174 master->fsia.base = master->base;
1175 master->fsia.master = master;
1178 master->fsib.base = master->base + 0x40;
1179 master->fsib.master = master;
1181 pm_runtime_enable(&pdev->dev);
1182 pm_runtime_resume(&pdev->dev);
1183 dev_set_drvdata(&pdev->dev, master);
1185 fsi_soft_all_reset(master);
1187 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1188 id_entry->name, master);
1190 dev_err(&pdev->dev, "irq request err\n");
1194 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1196 dev_err(&pdev->dev, "cannot snd soc register\n");
1200 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1203 free_irq(irq, master);
1205 iounmap(master->base);
1206 pm_runtime_disable(&pdev->dev);
1214 static int fsi_remove(struct platform_device *pdev)
1216 struct fsi_master *master;
1218 master = dev_get_drvdata(&pdev->dev);
1220 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1221 snd_soc_unregister_platform(&pdev->dev);
1223 pm_runtime_disable(&pdev->dev);
1225 free_irq(master->irq, master);
1227 iounmap(master->base);
1233 static int fsi_runtime_nop(struct device *dev)
1235 /* Runtime PM callback shared between ->runtime_suspend()
1236 * and ->runtime_resume(). Simply returns success.
1238 * This driver re-initializes all registers after
1239 * pm_runtime_get_sync() anyway so there is no need
1240 * to save and restore registers here.
1245 static struct dev_pm_ops fsi_pm_ops = {
1246 .runtime_suspend = fsi_runtime_nop,
1247 .runtime_resume = fsi_runtime_nop,
1250 static struct fsi_core fsi1_core = {
1259 static struct fsi_core fsi2_core = {
1263 .int_st = CPU_INT_ST,
1266 .a_mclk = A_MST_CTLR,
1267 .b_mclk = B_MST_CTLR,
1270 static struct platform_device_id fsi_id_table[] = {
1271 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1272 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1275 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1277 static struct platform_driver fsi_driver = {
1279 .name = "fsi-pcm-audio",
1283 .remove = fsi_remove,
1284 .id_table = fsi_id_table,
1287 static int __init fsi_mobile_init(void)
1289 return platform_driver_register(&fsi_driver);
1292 static void __exit fsi_mobile_exit(void)
1294 platform_driver_unregister(&fsi_driver);
1297 module_init(fsi_mobile_init);
1298 module_exit(fsi_mobile_exit);
1300 MODULE_LICENSE("GPL");
1301 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1302 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");