2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
26 #include <sound/pcm_params.h>
27 #include <sound/sh_fsi.h>
28 #include <asm/atomic.h>
31 #define DOFF_CTL 0x0004
32 #define DOFF_ST 0x0008
34 #define DIFF_CTL 0x0010
35 #define DIFF_ST 0x0014
40 #define MUTE_ST 0x0028
41 #define REG_END MUTE_ST
47 #define CLK_RST 0x0210
48 #define SOFT_RST 0x0214
49 #define FIFO_SZ 0x0218
50 #define MREG_START INT_ST
51 #define MREG_END FIFO_SZ
55 #define CR_FMT(param) ((param) << 4)
57 # define CR_MONO_D 0x1
65 #define IRQ_HALF 0x00100000
66 #define FIFO_CLR 0x00000001
69 #define ERR_OVER 0x00000010
70 #define ERR_UNDER 0x00000001
71 #define ST_ERR (ERR_OVER | ERR_UNDER)
74 #define B_CLK 0x00000010
75 #define A_CLK 0x00000001
78 #define INT_B_IN (1 << 12)
79 #define INT_B_OUT (1 << 8)
80 #define INT_A_IN (1 << 4)
81 #define INT_A_OUT (1 << 0)
84 #define PBSR (1 << 12) /* Port B Software Reset */
85 #define PASR (1 << 8) /* Port A Software Reset */
86 #define IR (1 << 4) /* Interrupt Reset */
87 #define FSISR (1 << 0) /* Software Reset */
90 #define OUT_SZ_MASK 0x7
94 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
96 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
98 /************************************************************************
104 ************************************************************************/
107 struct snd_pcm_substream *substream;
108 struct fsi_master *master;
122 struct fsi_priv fsia;
123 struct fsi_priv fsib;
124 struct sh_fsi_platform_info *info;
128 /************************************************************************
131 basic read write function
134 ************************************************************************/
135 static void __fsi_reg_write(u32 reg, u32 data)
137 /* valid data area is 24bit */
140 __raw_writel(data, reg);
143 static u32 __fsi_reg_read(u32 reg)
145 return __raw_readl(reg);
148 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
150 u32 val = __fsi_reg_read(reg);
155 __fsi_reg_write(reg, val);
158 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
163 __fsi_reg_write((u32)(fsi->base + reg), data);
166 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
171 return __fsi_reg_read((u32)(fsi->base + reg));
174 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
179 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
182 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
186 if ((reg < MREG_START) ||
190 spin_lock_irqsave(&master->lock, flags);
191 __fsi_reg_write((u32)(master->base + reg), data);
192 spin_unlock_irqrestore(&master->lock, flags);
195 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
200 if ((reg < MREG_START) ||
204 spin_lock_irqsave(&master->lock, flags);
205 ret = __fsi_reg_read((u32)(master->base + reg));
206 spin_unlock_irqrestore(&master->lock, flags);
211 static void fsi_master_mask_set(struct fsi_master *master,
212 u32 reg, u32 mask, u32 data)
216 if ((reg < MREG_START) ||
220 spin_lock_irqsave(&master->lock, flags);
221 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
222 spin_unlock_irqrestore(&master->lock, flags);
225 /************************************************************************
231 ************************************************************************/
232 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
237 static int fsi_is_port_a(struct fsi_priv *fsi)
239 return fsi->master->base == fsi->base;
242 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
244 struct snd_soc_pcm_runtime *rtd = substream->private_data;
245 struct snd_soc_dai_link *machine = rtd->dai;
247 return machine->cpu_dai;
250 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
252 struct snd_soc_dai *dai = fsi_get_dai(substream);
254 return dai->private_data;
257 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
259 int is_porta = fsi_is_port_a(fsi);
260 struct fsi_master *master = fsi_get_master(fsi);
262 return is_porta ? master->info->porta_flags :
263 master->info->portb_flags;
266 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
269 u32 flags = fsi_get_info_flags(fsi);
271 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
278 return (mode & flags) != mode;
281 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
283 int is_porta = fsi_is_port_a(fsi);
287 data = is_play ? (1 << 0) : (1 << 4);
289 data = is_play ? (1 << 8) : (1 << 12);
294 static void fsi_stream_push(struct fsi_priv *fsi,
295 struct snd_pcm_substream *substream,
299 fsi->substream = substream;
300 fsi->buffer_len = buffer_len;
301 fsi->period_len = period_len;
302 fsi->byte_offset = 0;
306 static void fsi_stream_pop(struct fsi_priv *fsi)
308 fsi->substream = NULL;
311 fsi->byte_offset = 0;
315 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
318 u32 reg = is_play ? DOFF_ST : DIFF_ST;
321 status = fsi_reg_read(fsi, reg);
322 residue = 0x1ff & (status >> 8);
323 residue *= fsi->chan;
328 /************************************************************************
334 ************************************************************************/
335 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
337 u32 data = fsi_port_ab_io_bit(fsi, is_play);
338 struct fsi_master *master = fsi_get_master(fsi);
340 fsi_master_mask_set(master, IMSK, data, data);
341 fsi_master_mask_set(master, IEMSK, data, data);
344 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
346 u32 data = fsi_port_ab_io_bit(fsi, is_play);
347 struct fsi_master *master = fsi_get_master(fsi);
349 fsi_master_mask_set(master, IMSK, data, 0);
350 fsi_master_mask_set(master, IEMSK, data, 0);
353 static u32 fsi_irq_get_status(struct fsi_master *master)
355 return fsi_master_read(master, INT_ST);
358 static void fsi_irq_clear_all_status(struct fsi_master *master)
360 fsi_master_write(master, INT_ST, 0x0000000);
363 static void fsi_irq_clear_status(struct fsi_priv *fsi)
366 struct fsi_master *master = fsi_get_master(fsi);
368 data |= fsi_port_ab_io_bit(fsi, 0);
369 data |= fsi_port_ab_io_bit(fsi, 1);
371 /* clear interrupt factor */
372 fsi_master_mask_set(master, INT_ST, data, 0);
375 /************************************************************************
381 ************************************************************************/
382 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
384 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
385 struct fsi_master *master = fsi_get_master(fsi);
388 fsi_master_mask_set(master, CLK_RST, val, val);
390 fsi_master_mask_set(master, CLK_RST, val, 0);
393 static void fsi_fifo_init(struct fsi_priv *fsi,
395 struct snd_soc_dai *dai)
397 struct fsi_master *master = fsi_get_master(fsi);
400 /* get on-chip RAM capacity */
401 shift = fsi_master_read(master, FIFO_SZ);
402 shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
403 shift &= OUT_SZ_MASK;
404 fsi->fifo_max = 256 << shift;
405 dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max);
408 * The maximum number of sample data varies depending
409 * on the number of channels selected for the format.
411 * FIFOs are used in 4-channel units in 3-channel mode
412 * and in 8-channel units in 5- to 7-channel mode
413 * meaning that more FIFOs than the required size of DPRAM
416 * ex) if 256 words of DP-RAM is connected
417 * 1 channel: 256 (256 x 1 = 256)
418 * 2 channels: 128 (128 x 2 = 256)
419 * 3 channels: 64 ( 64 x 3 = 192)
420 * 4 channels: 64 ( 64 x 4 = 256)
421 * 5 channels: 32 ( 32 x 5 = 160)
422 * 6 channels: 32 ( 32 x 6 = 192)
423 * 7 channels: 32 ( 32 x 7 = 224)
424 * 8 channels: 32 ( 32 x 8 = 256)
426 for (i = 1; i < fsi->chan; i <<= 1)
428 dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max);
430 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
432 /* set interrupt generation factor */
433 fsi_reg_write(fsi, ctrl, IRQ_HALF);
436 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
439 static void fsi_soft_all_reset(struct fsi_master *master)
442 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
446 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
447 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
451 /* playback interrupt */
452 static int fsi_data_push(struct fsi_priv *fsi, int startup)
454 struct snd_pcm_runtime *runtime;
455 struct snd_pcm_substream *substream = NULL;
465 !fsi->substream->runtime)
469 substream = fsi->substream;
470 runtime = substream->runtime;
472 /* FSI FIFO has limit.
473 * So, this driver can not send periods data at a time
475 if (fsi->byte_offset >=
476 fsi->period_len * (fsi->periods + 1)) {
479 fsi->periods = (fsi->periods + 1) % runtime->periods;
481 if (0 == fsi->periods)
482 fsi->byte_offset = 0;
485 /* get 1 channel data width */
486 width = frames_to_bytes(runtime, 1) / fsi->chan;
488 /* get send size for alsa */
489 send = (fsi->buffer_len - fsi->byte_offset) / width;
491 /* get FIFO free size */
492 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
495 if (fifo_free < send)
498 start = runtime->dma_area;
499 start += fsi->byte_offset;
503 for (i = 0; i < send; i++)
504 fsi_reg_write(fsi, DODT,
505 ((u32)*((u16 *)start + i) << 8));
508 for (i = 0; i < send; i++)
509 fsi_reg_write(fsi, DODT, *((u32 *)start + i));
515 fsi->byte_offset += send * width;
517 status = fsi_reg_read(fsi, DOFF_ST);
519 struct snd_soc_dai *dai = fsi_get_dai(substream);
521 if (status & ERR_OVER)
522 dev_err(dai->dev, "over run\n");
523 if (status & ERR_UNDER)
524 dev_err(dai->dev, "under run\n");
526 fsi_reg_write(fsi, DOFF_ST, 0);
528 fsi_irq_enable(fsi, 1);
531 snd_pcm_period_elapsed(substream);
536 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
538 struct snd_pcm_runtime *runtime;
539 struct snd_pcm_substream *substream = NULL;
549 !fsi->substream->runtime)
553 substream = fsi->substream;
554 runtime = substream->runtime;
556 /* FSI FIFO has limit.
557 * So, this driver can not send periods data at a time
559 if (fsi->byte_offset >=
560 fsi->period_len * (fsi->periods + 1)) {
563 fsi->periods = (fsi->periods + 1) % runtime->periods;
565 if (0 == fsi->periods)
566 fsi->byte_offset = 0;
569 /* get 1 channel data width */
570 width = frames_to_bytes(runtime, 1) / fsi->chan;
572 /* get free space for alsa */
573 free = (fsi->buffer_len - fsi->byte_offset) / width;
576 fifo_fill = fsi_get_fifo_residue(fsi, 0);
578 if (free < fifo_fill)
581 start = runtime->dma_area;
582 start += fsi->byte_offset;
586 for (i = 0; i < fifo_fill; i++)
587 *((u16 *)start + i) =
588 (u16)(fsi_reg_read(fsi, DIDT) >> 8);
591 for (i = 0; i < fifo_fill; i++)
592 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
598 fsi->byte_offset += fifo_fill * width;
600 status = fsi_reg_read(fsi, DIFF_ST);
602 struct snd_soc_dai *dai = fsi_get_dai(substream);
604 if (status & ERR_OVER)
605 dev_err(dai->dev, "over run\n");
606 if (status & ERR_UNDER)
607 dev_err(dai->dev, "under run\n");
609 fsi_reg_write(fsi, DIFF_ST, 0);
611 fsi_irq_enable(fsi, 0);
614 snd_pcm_period_elapsed(substream);
619 static irqreturn_t fsi_interrupt(int irq, void *data)
621 struct fsi_master *master = data;
622 u32 int_st = fsi_irq_get_status(master);
624 /* clear irq status */
625 fsi_master_mask_set(master, SOFT_RST, IR, 0);
626 fsi_master_mask_set(master, SOFT_RST, IR, IR);
628 if (int_st & INT_A_OUT)
629 fsi_data_push(&master->fsia, 0);
630 if (int_st & INT_B_OUT)
631 fsi_data_push(&master->fsib, 0);
632 if (int_st & INT_A_IN)
633 fsi_data_pop(&master->fsia, 0);
634 if (int_st & INT_B_IN)
635 fsi_data_pop(&master->fsib, 0);
637 fsi_irq_clear_all_status(master);
642 /************************************************************************
648 ************************************************************************/
649 static int fsi_dai_startup(struct snd_pcm_substream *substream,
650 struct snd_soc_dai *dai)
652 struct fsi_priv *fsi = fsi_get_priv(substream);
654 u32 flags = fsi_get_info_flags(fsi);
658 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
662 pm_runtime_get_sync(dai->dev);
665 data = is_play ? (1 << 0) : (1 << 4);
666 is_master = fsi_is_master_mode(fsi, is_play);
668 fsi_reg_mask_set(fsi, CKG1, data, data);
670 fsi_reg_mask_set(fsi, CKG1, data, 0);
672 /* clock inversion (CKG2) */
674 switch (SH_FSI_INVERSION_MASK & flags) {
688 fsi_reg_write(fsi, CKG2, data);
692 reg = is_play ? DO_FMT : DI_FMT;
693 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
695 case SH_FSI_FMT_MONO:
697 data = CR_FMT(CR_MONO);
700 case SH_FSI_FMT_MONO_DELAY:
702 data = CR_FMT(CR_MONO_D);
707 data = CR_FMT(CR_PCM);
712 data = CR_FMT(CR_I2S);
717 data = CR_FMT(CR_TDM) | (fsi->chan - 1);
718 fsi->chan = is_play ?
719 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
721 case SH_FSI_FMT_TDM_DELAY:
723 data = CR_FMT(CR_TDM_D) | (fsi->chan - 1);
724 fsi->chan = is_play ?
725 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
728 dev_err(dai->dev, "unknown format.\n");
731 fsi_reg_write(fsi, reg, data);
734 * clear clk reset if master mode
737 fsi_clk_ctrl(fsi, 1);
740 fsi_irq_disable(fsi, is_play);
741 fsi_irq_clear_status(fsi);
744 fsi_fifo_init(fsi, is_play, dai);
749 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
750 struct snd_soc_dai *dai)
752 struct fsi_priv *fsi = fsi_get_priv(substream);
753 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
755 fsi_irq_disable(fsi, is_play);
756 fsi_clk_ctrl(fsi, 0);
758 pm_runtime_put_sync(dai->dev);
761 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
762 struct snd_soc_dai *dai)
764 struct fsi_priv *fsi = fsi_get_priv(substream);
765 struct snd_pcm_runtime *runtime = substream->runtime;
766 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
770 case SNDRV_PCM_TRIGGER_START:
771 fsi_stream_push(fsi, substream,
772 frames_to_bytes(runtime, runtime->buffer_size),
773 frames_to_bytes(runtime, runtime->period_size));
774 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
776 case SNDRV_PCM_TRIGGER_STOP:
777 fsi_irq_disable(fsi, is_play);
785 static struct snd_soc_dai_ops fsi_dai_ops = {
786 .startup = fsi_dai_startup,
787 .shutdown = fsi_dai_shutdown,
788 .trigger = fsi_dai_trigger,
791 /************************************************************************
797 ************************************************************************/
798 static struct snd_pcm_hardware fsi_pcm_hardware = {
799 .info = SNDRV_PCM_INFO_INTERLEAVED |
800 SNDRV_PCM_INFO_MMAP |
801 SNDRV_PCM_INFO_MMAP_VALID |
802 SNDRV_PCM_INFO_PAUSE,
809 .buffer_bytes_max = 64 * 1024,
810 .period_bytes_min = 32,
811 .period_bytes_max = 8192,
817 static int fsi_pcm_open(struct snd_pcm_substream *substream)
819 struct snd_pcm_runtime *runtime = substream->runtime;
822 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
824 ret = snd_pcm_hw_constraint_integer(runtime,
825 SNDRV_PCM_HW_PARAM_PERIODS);
830 static int fsi_hw_params(struct snd_pcm_substream *substream,
831 struct snd_pcm_hw_params *hw_params)
833 return snd_pcm_lib_malloc_pages(substream,
834 params_buffer_bytes(hw_params));
837 static int fsi_hw_free(struct snd_pcm_substream *substream)
839 return snd_pcm_lib_free_pages(substream);
842 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
844 struct snd_pcm_runtime *runtime = substream->runtime;
845 struct fsi_priv *fsi = fsi_get_priv(substream);
848 location = (fsi->byte_offset - 1);
852 return bytes_to_frames(runtime, location);
855 static struct snd_pcm_ops fsi_pcm_ops = {
856 .open = fsi_pcm_open,
857 .ioctl = snd_pcm_lib_ioctl,
858 .hw_params = fsi_hw_params,
859 .hw_free = fsi_hw_free,
860 .pointer = fsi_pointer,
863 /************************************************************************
869 ************************************************************************/
870 #define PREALLOC_BUFFER (32 * 1024)
871 #define PREALLOC_BUFFER_MAX (32 * 1024)
873 static void fsi_pcm_free(struct snd_pcm *pcm)
875 snd_pcm_lib_preallocate_free_for_all(pcm);
878 static int fsi_pcm_new(struct snd_card *card,
879 struct snd_soc_dai *dai,
883 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
884 * in MMAP mode (i.e. aplay -M)
886 return snd_pcm_lib_preallocate_pages_for_all(
888 SNDRV_DMA_TYPE_CONTINUOUS,
889 snd_dma_continuous_data(GFP_KERNEL),
890 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
893 /************************************************************************
899 ************************************************************************/
900 struct snd_soc_dai fsi_soc_dai[] = {
936 EXPORT_SYMBOL_GPL(fsi_soc_dai);
938 struct snd_soc_platform fsi_soc_platform = {
940 .pcm_ops = &fsi_pcm_ops,
941 .pcm_new = fsi_pcm_new,
942 .pcm_free = fsi_pcm_free,
944 EXPORT_SYMBOL_GPL(fsi_soc_platform);
946 /************************************************************************
952 ************************************************************************/
953 static int fsi_probe(struct platform_device *pdev)
955 struct fsi_master *master;
956 struct resource *res;
961 dev_err(&pdev->dev, "current fsi support id 0 only now\n");
965 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
966 irq = platform_get_irq(pdev, 0);
967 if (!res || (int)irq <= 0) {
968 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
973 master = kzalloc(sizeof(*master), GFP_KERNEL);
975 dev_err(&pdev->dev, "Could not allocate master\n");
980 master->base = ioremap_nocache(res->start, resource_size(res));
983 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
988 master->info = pdev->dev.platform_data;
989 master->fsia.base = master->base;
990 master->fsia.master = master;
991 master->fsib.base = master->base + 0x40;
992 master->fsib.master = master;
993 spin_lock_init(&master->lock);
995 pm_runtime_enable(&pdev->dev);
996 pm_runtime_resume(&pdev->dev);
998 fsi_soc_dai[0].dev = &pdev->dev;
999 fsi_soc_dai[0].private_data = &master->fsia;
1000 fsi_soc_dai[1].dev = &pdev->dev;
1001 fsi_soc_dai[1].private_data = &master->fsib;
1003 fsi_soft_all_reset(master);
1005 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master);
1007 dev_err(&pdev->dev, "irq request err\n");
1011 ret = snd_soc_register_platform(&fsi_soc_platform);
1013 dev_err(&pdev->dev, "cannot snd soc register\n");
1017 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1020 free_irq(irq, master);
1022 iounmap(master->base);
1023 pm_runtime_disable(&pdev->dev);
1031 static int fsi_remove(struct platform_device *pdev)
1033 struct fsi_master *master;
1035 master = fsi_get_master(fsi_soc_dai[0].private_data);
1037 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1038 snd_soc_unregister_platform(&fsi_soc_platform);
1040 pm_runtime_disable(&pdev->dev);
1042 free_irq(master->irq, master);
1044 iounmap(master->base);
1047 fsi_soc_dai[0].dev = NULL;
1048 fsi_soc_dai[0].private_data = NULL;
1049 fsi_soc_dai[1].dev = NULL;
1050 fsi_soc_dai[1].private_data = NULL;
1055 static int fsi_runtime_nop(struct device *dev)
1057 /* Runtime PM callback shared between ->runtime_suspend()
1058 * and ->runtime_resume(). Simply returns success.
1060 * This driver re-initializes all registers after
1061 * pm_runtime_get_sync() anyway so there is no need
1062 * to save and restore registers here.
1067 static struct dev_pm_ops fsi_pm_ops = {
1068 .runtime_suspend = fsi_runtime_nop,
1069 .runtime_resume = fsi_runtime_nop,
1072 static struct platform_driver fsi_driver = {
1078 .remove = fsi_remove,
1081 static int __init fsi_mobile_init(void)
1083 return platform_driver_register(&fsi_driver);
1086 static void __exit fsi_mobile_exit(void)
1088 platform_driver_unregister(&fsi_driver);
1090 module_init(fsi_mobile_init);
1091 module_exit(fsi_mobile_exit);
1093 MODULE_LICENSE("GPL");
1094 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1095 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");