2 * soc-cache.c -- ASoC register cache helpers
4 * Copyright 2009 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/i2c.h>
15 #include <linux/spi/spi.h>
16 #include <sound/soc.h>
18 static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
21 u16 *cache = codec->reg_cache;
23 if (reg >= codec->driver->reg_cache_size ||
24 snd_soc_codec_volatile_register(codec, reg)) {
25 if (codec->cache_only)
28 return codec->hw_read(codec, reg);
34 static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
37 u16 *cache = codec->reg_cache;
41 data[0] = (reg << 4) | ((value >> 8) & 0x000f);
42 data[1] = value & 0x00ff;
44 if (!snd_soc_codec_volatile_register(codec, reg) &&
45 reg < codec->driver->reg_cache_size)
48 if (codec->cache_only) {
49 codec->cache_sync = 1;
53 ret = codec->hw_write(codec->control_data, data, 2);
62 #if defined(CONFIG_SPI_MASTER)
63 static int snd_soc_4_12_spi_write(void *control_data, const char *data,
66 struct spi_device *spi = control_data;
67 struct spi_transfer t;
78 memset(&t, 0, (sizeof t));
83 spi_message_add_tail(&t, &m);
89 #define snd_soc_4_12_spi_write NULL
92 static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
95 u16 *cache = codec->reg_cache;
97 if (reg >= codec->driver->reg_cache_size ||
98 snd_soc_codec_volatile_register(codec, reg)) {
99 if (codec->cache_only)
102 return codec->hw_read(codec, reg);
108 static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
111 u16 *cache = codec->reg_cache;
115 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
116 data[1] = value & 0x00ff;
118 if (!snd_soc_codec_volatile_register(codec, reg) &&
119 reg < codec->driver->reg_cache_size)
122 if (codec->cache_only) {
123 codec->cache_sync = 1;
127 ret = codec->hw_write(codec->control_data, data, 2);
136 #if defined(CONFIG_SPI_MASTER)
137 static int snd_soc_7_9_spi_write(void *control_data, const char *data,
140 struct spi_device *spi = control_data;
141 struct spi_transfer t;
142 struct spi_message m;
151 spi_message_init(&m);
152 memset(&t, 0, (sizeof t));
157 spi_message_add_tail(&t, &m);
163 #define snd_soc_7_9_spi_write NULL
166 static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
169 u8 *cache = codec->reg_cache;
174 data[1] = value & 0xff;
176 if (!snd_soc_codec_volatile_register(codec, reg) &&
177 reg < codec->driver->reg_cache_size)
180 if (codec->cache_only) {
181 codec->cache_sync = 1;
185 if (codec->hw_write(codec->control_data, data, 2) == 2)
191 static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
194 u8 *cache = codec->reg_cache;
197 if (reg >= codec->driver->reg_cache_size ||
198 snd_soc_codec_volatile_register(codec, reg)) {
199 if (codec->cache_only)
202 return codec->hw_read(codec, reg);
208 #if defined(CONFIG_SPI_MASTER)
209 static int snd_soc_8_8_spi_write(void *control_data, const char *data,
212 struct spi_device *spi = control_data;
213 struct spi_transfer t;
214 struct spi_message m;
223 spi_message_init(&m);
224 memset(&t, 0, (sizeof t));
229 spi_message_add_tail(&t, &m);
235 #define snd_soc_8_8_spi_write NULL
238 static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
241 u16 *reg_cache = codec->reg_cache;
245 data[1] = (value >> 8) & 0xff;
246 data[2] = value & 0xff;
248 if (!snd_soc_codec_volatile_register(codec, reg) &&
249 reg < codec->driver->reg_cache_size)
250 reg_cache[reg] = value;
252 if (codec->cache_only) {
253 codec->cache_sync = 1;
257 if (codec->hw_write(codec->control_data, data, 3) == 3)
263 static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
266 u16 *cache = codec->reg_cache;
268 if (reg >= codec->driver->reg_cache_size ||
269 snd_soc_codec_volatile_register(codec, reg)) {
270 if (codec->cache_only)
273 return codec->hw_read(codec, reg);
279 #if defined(CONFIG_SPI_MASTER)
280 static int snd_soc_8_16_spi_write(void *control_data, const char *data,
283 struct spi_device *spi = control_data;
284 struct spi_transfer t;
285 struct spi_message m;
295 spi_message_init(&m);
296 memset(&t, 0, (sizeof t));
301 spi_message_add_tail(&t, &m);
307 #define snd_soc_8_16_spi_write NULL
310 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
311 static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
314 struct i2c_msg xfer[2];
318 struct i2c_client *client = codec->control_data;
321 xfer[0].addr = client->addr;
327 xfer[1].addr = client->addr;
328 xfer[1].flags = I2C_M_RD;
332 ret = i2c_transfer(client->adapter, xfer, 2);
334 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
341 #define snd_soc_8_8_read_i2c NULL
344 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
345 static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
348 struct i2c_msg xfer[2];
352 struct i2c_client *client = codec->control_data;
355 xfer[0].addr = client->addr;
361 xfer[1].addr = client->addr;
362 xfer[1].flags = I2C_M_RD;
364 xfer[1].buf = (u8 *)&data;
366 ret = i2c_transfer(client->adapter, xfer, 2);
368 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
372 return (data >> 8) | ((data & 0xff) << 8);
375 #define snd_soc_8_16_read_i2c NULL
378 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
379 static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
382 struct i2c_msg xfer[2];
386 struct i2c_client *client = codec->control_data;
389 xfer[0].addr = client->addr;
392 xfer[0].buf = (u8 *)®
395 xfer[1].addr = client->addr;
396 xfer[1].flags = I2C_M_RD;
400 ret = i2c_transfer(client->adapter, xfer, 2);
402 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
409 #define snd_soc_16_8_read_i2c NULL
412 static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
415 u8 *cache = codec->reg_cache;
418 if (reg >= codec->driver->reg_cache_size ||
419 snd_soc_codec_volatile_register(codec, reg)) {
420 if (codec->cache_only)
423 return codec->hw_read(codec, reg);
429 static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
432 u8 *cache = codec->reg_cache;
436 data[0] = (reg >> 8) & 0xff;
437 data[1] = reg & 0xff;
441 if (!snd_soc_codec_volatile_register(codec, reg) &&
442 reg < codec->driver->reg_cache_size)
445 if (codec->cache_only) {
446 codec->cache_sync = 1;
450 ret = codec->hw_write(codec->control_data, data, 3);
459 #if defined(CONFIG_SPI_MASTER)
460 static int snd_soc_16_8_spi_write(void *control_data, const char *data,
463 struct spi_device *spi = control_data;
464 struct spi_transfer t;
465 struct spi_message m;
475 spi_message_init(&m);
476 memset(&t, 0, (sizeof t));
481 spi_message_add_tail(&t, &m);
487 #define snd_soc_16_8_spi_write NULL
490 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
491 static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
494 struct i2c_msg xfer[2];
495 u16 reg = cpu_to_be16(r);
498 struct i2c_client *client = codec->control_data;
501 xfer[0].addr = client->addr;
504 xfer[0].buf = (u8 *)®
507 xfer[1].addr = client->addr;
508 xfer[1].flags = I2C_M_RD;
510 xfer[1].buf = (u8 *)&data;
512 ret = i2c_transfer(client->adapter, xfer, 2);
514 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
518 return be16_to_cpu(data);
521 #define snd_soc_16_16_read_i2c NULL
524 static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
527 u16 *cache = codec->reg_cache;
529 if (reg >= codec->driver->reg_cache_size ||
530 snd_soc_codec_volatile_register(codec, reg)) {
531 if (codec->cache_only)
534 return codec->hw_read(codec, reg);
540 static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
543 u16 *cache = codec->reg_cache;
547 data[0] = (reg >> 8) & 0xff;
548 data[1] = reg & 0xff;
549 data[2] = (value >> 8) & 0xff;
550 data[3] = value & 0xff;
552 if (!snd_soc_codec_volatile_register(codec, reg) &&
553 reg < codec->driver->reg_cache_size)
556 if (codec->cache_only) {
557 codec->cache_sync = 1;
561 ret = codec->hw_write(codec->control_data, data, 4);
570 #if defined(CONFIG_SPI_MASTER)
571 static int snd_soc_16_16_spi_write(void *control_data, const char *data,
574 struct spi_device *spi = control_data;
575 struct spi_transfer t;
576 struct spi_message m;
587 spi_message_init(&m);
588 memset(&t, 0, (sizeof t));
593 spi_message_add_tail(&t, &m);
599 #define snd_soc_16_16_spi_write NULL
605 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
606 int (*spi_write)(void *, const char *, int);
607 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
608 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
611 .addr_bits = 4, .data_bits = 12,
612 .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
613 .spi_write = snd_soc_4_12_spi_write,
616 .addr_bits = 7, .data_bits = 9,
617 .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
618 .spi_write = snd_soc_7_9_spi_write,
621 .addr_bits = 8, .data_bits = 8,
622 .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
623 .i2c_read = snd_soc_8_8_read_i2c,
624 .spi_write = snd_soc_8_8_spi_write,
627 .addr_bits = 8, .data_bits = 16,
628 .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
629 .i2c_read = snd_soc_8_16_read_i2c,
630 .spi_write = snd_soc_8_16_spi_write,
633 .addr_bits = 16, .data_bits = 8,
634 .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
635 .i2c_read = snd_soc_16_8_read_i2c,
636 .spi_write = snd_soc_16_8_spi_write,
639 .addr_bits = 16, .data_bits = 16,
640 .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
641 .i2c_read = snd_soc_16_16_read_i2c,
642 .spi_write = snd_soc_16_16_spi_write,
647 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
649 * @codec: CODEC to configure.
650 * @type: Type of cache.
651 * @addr_bits: Number of bits of register address data.
652 * @data_bits: Number of bits of data per register.
653 * @control: Control bus used.
655 * Register formats are frequently shared between many I2C and SPI
656 * devices. In order to promote code reuse the ASoC core provides
657 * some standard implementations of CODEC read and write operations
658 * which can be set up using this function.
660 * The caller is responsible for allocating and initialising the
663 * Note that at present this code cannot be used by CODECs with
664 * volatile registers.
666 int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
667 int addr_bits, int data_bits,
668 enum snd_soc_control_type control)
672 for (i = 0; i < ARRAY_SIZE(io_types); i++)
673 if (io_types[i].addr_bits == addr_bits &&
674 io_types[i].data_bits == data_bits)
676 if (i == ARRAY_SIZE(io_types)) {
678 "No I/O functions for %d bit address %d bit data\n",
679 addr_bits, data_bits);
683 codec->driver->write = io_types[i].write;
684 codec->driver->read = io_types[i].read;
691 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
692 codec->hw_write = (hw_write_t)i2c_master_send;
694 if (io_types[i].i2c_read)
695 codec->hw_read = io_types[i].i2c_read;
697 codec->control_data = container_of(codec->dev,
703 if (io_types[i].spi_write)
704 codec->hw_write = io_types[i].spi_write;
706 codec->control_data = container_of(codec->dev,
714 EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);