2 * soc-cache.c -- ASoC register cache helpers
4 * Copyright 2009 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/i2c.h>
15 #include <linux/spi/spi.h>
16 #include <sound/soc.h>
18 static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
21 u16 *cache = codec->reg_cache;
23 if (reg >= codec->driver->reg_cache_size ||
24 snd_soc_codec_volatile_register(codec, reg)) {
25 if (codec->cache_only)
28 return codec->hw_read(codec, reg);
34 static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
37 u16 *cache = codec->reg_cache;
41 data[0] = (reg << 4) | ((value >> 8) & 0x000f);
42 data[1] = value & 0x00ff;
44 if (!snd_soc_codec_volatile_register(codec, reg) &&
45 reg < codec->driver->reg_cache_size)
48 if (codec->cache_only) {
49 codec->cache_sync = 1;
53 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
55 ret = codec->hw_write(codec->control_data, data, 2);
64 #if defined(CONFIG_SPI_MASTER)
65 static int snd_soc_4_12_spi_write(void *control_data, const char *data,
68 struct spi_device *spi = control_data;
69 struct spi_transfer t;
80 memset(&t, 0, (sizeof t));
85 spi_message_add_tail(&t, &m);
91 #define snd_soc_4_12_spi_write NULL
94 static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
97 u16 *cache = codec->reg_cache;
99 if (reg >= codec->driver->reg_cache_size ||
100 snd_soc_codec_volatile_register(codec, reg)) {
101 if (codec->cache_only)
104 return codec->hw_read(codec, reg);
110 static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
113 u16 *cache = codec->reg_cache;
117 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
118 data[1] = value & 0x00ff;
120 if (!snd_soc_codec_volatile_register(codec, reg) &&
121 reg < codec->driver->reg_cache_size)
124 if (codec->cache_only) {
125 codec->cache_sync = 1;
129 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
131 ret = codec->hw_write(codec->control_data, data, 2);
140 #if defined(CONFIG_SPI_MASTER)
141 static int snd_soc_7_9_spi_write(void *control_data, const char *data,
144 struct spi_device *spi = control_data;
145 struct spi_transfer t;
146 struct spi_message m;
155 spi_message_init(&m);
156 memset(&t, 0, (sizeof t));
161 spi_message_add_tail(&t, &m);
167 #define snd_soc_7_9_spi_write NULL
170 static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
173 u8 *cache = codec->reg_cache;
178 data[1] = value & 0xff;
180 if (!snd_soc_codec_volatile_register(codec, reg) &&
181 reg < codec->driver->reg_cache_size)
184 if (codec->cache_only) {
185 codec->cache_sync = 1;
189 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
191 if (codec->hw_write(codec->control_data, data, 2) == 2)
197 static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
200 u8 *cache = codec->reg_cache;
203 if (reg >= codec->driver->reg_cache_size ||
204 snd_soc_codec_volatile_register(codec, reg)) {
205 if (codec->cache_only)
208 return codec->hw_read(codec, reg);
214 #if defined(CONFIG_SPI_MASTER)
215 static int snd_soc_8_8_spi_write(void *control_data, const char *data,
218 struct spi_device *spi = control_data;
219 struct spi_transfer t;
220 struct spi_message m;
229 spi_message_init(&m);
230 memset(&t, 0, (sizeof t));
235 spi_message_add_tail(&t, &m);
241 #define snd_soc_8_8_spi_write NULL
244 static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
247 u16 *reg_cache = codec->reg_cache;
251 data[1] = (value >> 8) & 0xff;
252 data[2] = value & 0xff;
254 if (!snd_soc_codec_volatile_register(codec, reg) &&
255 reg < codec->driver->reg_cache_size)
256 reg_cache[reg] = value;
258 if (codec->cache_only) {
259 codec->cache_sync = 1;
263 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
265 if (codec->hw_write(codec->control_data, data, 3) == 3)
271 static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
274 u16 *cache = codec->reg_cache;
276 if (reg >= codec->driver->reg_cache_size ||
277 snd_soc_codec_volatile_register(codec, reg)) {
278 if (codec->cache_only)
281 return codec->hw_read(codec, reg);
287 #if defined(CONFIG_SPI_MASTER)
288 static int snd_soc_8_16_spi_write(void *control_data, const char *data,
291 struct spi_device *spi = control_data;
292 struct spi_transfer t;
293 struct spi_message m;
303 spi_message_init(&m);
304 memset(&t, 0, (sizeof t));
309 spi_message_add_tail(&t, &m);
315 #define snd_soc_8_16_spi_write NULL
318 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
319 static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
322 struct i2c_msg xfer[2];
326 struct i2c_client *client = codec->control_data;
329 xfer[0].addr = client->addr;
335 xfer[1].addr = client->addr;
336 xfer[1].flags = I2C_M_RD;
340 ret = i2c_transfer(client->adapter, xfer, 2);
342 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
349 #define snd_soc_8_8_read_i2c NULL
352 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
353 static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
356 struct i2c_msg xfer[2];
360 struct i2c_client *client = codec->control_data;
363 xfer[0].addr = client->addr;
369 xfer[1].addr = client->addr;
370 xfer[1].flags = I2C_M_RD;
372 xfer[1].buf = (u8 *)&data;
374 ret = i2c_transfer(client->adapter, xfer, 2);
376 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
380 return (data >> 8) | ((data & 0xff) << 8);
383 #define snd_soc_8_16_read_i2c NULL
386 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
387 static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
390 struct i2c_msg xfer[2];
394 struct i2c_client *client = codec->control_data;
397 xfer[0].addr = client->addr;
400 xfer[0].buf = (u8 *)®
403 xfer[1].addr = client->addr;
404 xfer[1].flags = I2C_M_RD;
408 ret = i2c_transfer(client->adapter, xfer, 2);
410 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
417 #define snd_soc_16_8_read_i2c NULL
420 static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
423 u8 *cache = codec->reg_cache;
426 if (reg >= codec->driver->reg_cache_size ||
427 snd_soc_codec_volatile_register(codec, reg)) {
428 if (codec->cache_only)
431 return codec->hw_read(codec, reg);
437 static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
440 u8 *cache = codec->reg_cache;
444 data[0] = (reg >> 8) & 0xff;
445 data[1] = reg & 0xff;
449 if (!snd_soc_codec_volatile_register(codec, reg) &&
450 reg < codec->driver->reg_cache_size)
453 if (codec->cache_only) {
454 codec->cache_sync = 1;
458 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
460 ret = codec->hw_write(codec->control_data, data, 3);
469 #if defined(CONFIG_SPI_MASTER)
470 static int snd_soc_16_8_spi_write(void *control_data, const char *data,
473 struct spi_device *spi = control_data;
474 struct spi_transfer t;
475 struct spi_message m;
485 spi_message_init(&m);
486 memset(&t, 0, (sizeof t));
491 spi_message_add_tail(&t, &m);
497 #define snd_soc_16_8_spi_write NULL
500 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
501 static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
504 struct i2c_msg xfer[2];
505 u16 reg = cpu_to_be16(r);
508 struct i2c_client *client = codec->control_data;
511 xfer[0].addr = client->addr;
514 xfer[0].buf = (u8 *)®
517 xfer[1].addr = client->addr;
518 xfer[1].flags = I2C_M_RD;
520 xfer[1].buf = (u8 *)&data;
522 ret = i2c_transfer(client->adapter, xfer, 2);
524 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
528 return be16_to_cpu(data);
531 #define snd_soc_16_16_read_i2c NULL
534 static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
537 u16 *cache = codec->reg_cache;
539 if (reg >= codec->driver->reg_cache_size ||
540 snd_soc_codec_volatile_register(codec, reg)) {
541 if (codec->cache_only)
544 return codec->hw_read(codec, reg);
550 static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
553 u16 *cache = codec->reg_cache;
557 data[0] = (reg >> 8) & 0xff;
558 data[1] = reg & 0xff;
559 data[2] = (value >> 8) & 0xff;
560 data[3] = value & 0xff;
562 if (!snd_soc_codec_volatile_register(codec, reg) &&
563 reg < codec->driver->reg_cache_size)
566 if (codec->cache_only) {
567 codec->cache_sync = 1;
571 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
573 ret = codec->hw_write(codec->control_data, data, 4);
582 #if defined(CONFIG_SPI_MASTER)
583 static int snd_soc_16_16_spi_write(void *control_data, const char *data,
586 struct spi_device *spi = control_data;
587 struct spi_transfer t;
588 struct spi_message m;
599 spi_message_init(&m);
600 memset(&t, 0, (sizeof t));
605 spi_message_add_tail(&t, &m);
611 #define snd_soc_16_16_spi_write NULL
617 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
618 int (*spi_write)(void *, const char *, int);
619 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
620 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
623 .addr_bits = 4, .data_bits = 12,
624 .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
625 .spi_write = snd_soc_4_12_spi_write,
628 .addr_bits = 7, .data_bits = 9,
629 .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
630 .spi_write = snd_soc_7_9_spi_write,
633 .addr_bits = 8, .data_bits = 8,
634 .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
635 .i2c_read = snd_soc_8_8_read_i2c,
636 .spi_write = snd_soc_8_8_spi_write,
639 .addr_bits = 8, .data_bits = 16,
640 .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
641 .i2c_read = snd_soc_8_16_read_i2c,
642 .spi_write = snd_soc_8_16_spi_write,
645 .addr_bits = 16, .data_bits = 8,
646 .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
647 .i2c_read = snd_soc_16_8_read_i2c,
648 .spi_write = snd_soc_16_8_spi_write,
651 .addr_bits = 16, .data_bits = 16,
652 .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
653 .i2c_read = snd_soc_16_16_read_i2c,
654 .spi_write = snd_soc_16_16_spi_write,
659 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
661 * @codec: CODEC to configure.
662 * @type: Type of cache.
663 * @addr_bits: Number of bits of register address data.
664 * @data_bits: Number of bits of data per register.
665 * @control: Control bus used.
667 * Register formats are frequently shared between many I2C and SPI
668 * devices. In order to promote code reuse the ASoC core provides
669 * some standard implementations of CODEC read and write operations
670 * which can be set up using this function.
672 * The caller is responsible for allocating and initialising the
675 * Note that at present this code cannot be used by CODECs with
676 * volatile registers.
678 int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
679 int addr_bits, int data_bits,
680 enum snd_soc_control_type control)
684 for (i = 0; i < ARRAY_SIZE(io_types); i++)
685 if (io_types[i].addr_bits == addr_bits &&
686 io_types[i].data_bits == data_bits)
688 if (i == ARRAY_SIZE(io_types)) {
690 "No I/O functions for %d bit address %d bit data\n",
691 addr_bits, data_bits);
695 codec->driver->write = io_types[i].write;
696 codec->driver->read = io_types[i].read;
703 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
704 codec->hw_write = (hw_write_t)i2c_master_send;
706 if (io_types[i].i2c_read)
707 codec->hw_read = io_types[i].i2c_read;
709 codec->control_data = container_of(codec->dev,
715 if (io_types[i].spi_write)
716 codec->hw_write = io_types[i].spi_write;
718 codec->control_data = container_of(codec->dev,
726 EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);