2 * tegra_i2s.c - Tegra I2S driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010 - NVIDIA, Inc.
7 * Based on code copyright/by:
9 * Copyright (c) 2009-2010, NVIDIA Corporation.
10 * Scott Peterson <speterson@nvidia.com>
12 * Copyright (C) 2010 Google, Inc.
13 * Iliyan Malchev <malchev@google.com>
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * version 2 as published by the Free Software Foundation.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
31 #include <linux/clk.h>
32 #include <linux/module.h>
33 #include <linux/debugfs.h>
34 #include <linux/device.h>
35 #include <linux/platform_device.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
40 #include <mach/iomap.h>
41 #include <sound/core.h>
42 #include <sound/pcm.h>
43 #include <sound/pcm_params.h>
44 #include <sound/soc.h>
46 #include "tegra_i2s.h"
48 #define DRV_NAME "tegra-i2s"
50 static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
52 __raw_writel(val, i2s->regs + reg);
55 static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
57 return __raw_readl(i2s->regs + reg);
60 #ifdef CONFIG_DEBUG_FS
61 static int tegra_i2s_show(struct seq_file *s, void *unused)
63 #define REG(r) { r, #r }
69 REG(TEGRA_I2S_STATUS),
70 REG(TEGRA_I2S_TIMING),
71 REG(TEGRA_I2S_FIFO_SCR),
72 REG(TEGRA_I2S_PCM_CTRL),
73 REG(TEGRA_I2S_NW_CTRL),
74 REG(TEGRA_I2S_TDM_CTRL),
75 REG(TEGRA_I2S_TDM_TX_RX_CTRL),
79 struct tegra_i2s *i2s = s->private;
82 clk_enable(i2s->clk_i2s);
84 for (i = 0; i < ARRAY_SIZE(regs); i++) {
85 u32 val = tegra_i2s_read(i2s, regs[i].offset);
86 seq_printf(s, "%s = %08x\n", regs[i].name, val);
89 clk_disable(i2s->clk_i2s);
94 static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
96 return single_open(file, tegra_i2s_show, inode->i_private);
99 static const struct file_operations tegra_i2s_debug_fops = {
100 .open = tegra_i2s_debug_open,
103 .release = single_release,
106 static void tegra_i2s_debug_add(struct tegra_i2s *i2s)
108 i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
109 snd_soc_debugfs_root, i2s,
110 &tegra_i2s_debug_fops);
113 static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
116 debugfs_remove(i2s->debug);
119 static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s)
123 static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
128 static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
131 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
133 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
134 case SND_SOC_DAIFMT_NB_NF:
140 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
141 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
142 case SND_SOC_DAIFMT_CBS_CFS:
143 i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
145 case SND_SOC_DAIFMT_CBM_CFM:
151 i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
152 TEGRA_I2S_CTRL_LRCK_MASK);
153 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
154 case SND_SOC_DAIFMT_DSP_A:
155 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
156 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
158 case SND_SOC_DAIFMT_DSP_B:
159 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
160 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
162 case SND_SOC_DAIFMT_I2S:
163 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
164 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
166 case SND_SOC_DAIFMT_RIGHT_J:
167 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
168 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
170 case SND_SOC_DAIFMT_LEFT_J:
171 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
172 i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
181 static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
182 struct snd_pcm_hw_params *params,
183 struct snd_soc_dai *dai)
185 struct device *dev = substream->pcm->card->dev;
186 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
188 int ret, sample_size, srate, i2sclock, bitcnt;
190 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
191 switch (params_format(params)) {
192 case SNDRV_PCM_FORMAT_S16_LE:
193 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
196 case SNDRV_PCM_FORMAT_S24_LE:
197 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
200 case SNDRV_PCM_FORMAT_S32_LE:
201 i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
208 srate = params_rate(params);
210 /* Final "* 2" required by Tegra hardware */
211 i2sclock = srate * params_channels(params) * sample_size * 2;
213 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
215 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
219 bitcnt = (i2sclock / (2 * srate)) - 1;
220 if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
222 reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
224 if (i2sclock % (2 * srate))
225 reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
228 clk_enable(i2s->clk_i2s);
230 tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
232 tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
233 TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
234 TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
237 clk_disable(i2s->clk_i2s);
242 static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
244 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
245 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
248 static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
250 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
251 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
254 static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
256 i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
257 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
260 static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
262 i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
263 tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
266 static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
267 struct snd_soc_dai *dai)
269 struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
272 case SNDRV_PCM_TRIGGER_START:
273 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
274 case SNDRV_PCM_TRIGGER_RESUME:
276 clk_enable(i2s->clk_i2s);
278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
279 tegra_i2s_start_playback(i2s);
281 tegra_i2s_start_capture(i2s);
283 case SNDRV_PCM_TRIGGER_STOP:
284 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
285 case SNDRV_PCM_TRIGGER_SUSPEND:
286 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
287 tegra_i2s_stop_playback(i2s);
289 tegra_i2s_stop_capture(i2s);
292 clk_disable(i2s->clk_i2s);
301 static int tegra_i2s_probe(struct snd_soc_dai *dai)
303 struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
305 dai->capture_dma_data = &i2s->capture_dma_data;
306 dai->playback_dma_data = &i2s->playback_dma_data;
311 static const struct snd_soc_dai_ops tegra_i2s_dai_ops = {
312 .set_fmt = tegra_i2s_set_fmt,
313 .hw_params = tegra_i2s_hw_params,
314 .trigger = tegra_i2s_trigger,
317 static const struct snd_soc_dai_driver tegra_i2s_dai_template = {
318 .probe = tegra_i2s_probe,
322 .rates = SNDRV_PCM_RATE_8000_96000,
323 .formats = SNDRV_PCM_FMTBIT_S16_LE,
328 .rates = SNDRV_PCM_RATE_8000_96000,
329 .formats = SNDRV_PCM_FMTBIT_S16_LE,
331 .ops = &tegra_i2s_dai_ops,
332 .symmetric_rates = 1,
335 static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
337 struct tegra_i2s * i2s;
338 struct resource *mem, *memregion, *dmareq;
343 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra_i2s), GFP_KERNEL);
345 dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
349 dev_set_drvdata(&pdev->dev, i2s);
351 i2s->dai = tegra_i2s_dai_template;
352 i2s->dai.name = dev_name(&pdev->dev);
354 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
355 if (IS_ERR(i2s->clk_i2s)) {
356 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
357 ret = PTR_ERR(i2s->clk_i2s);
361 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 dev_err(&pdev->dev, "No memory resource\n");
368 dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
370 if (of_property_read_u32_array(pdev->dev.of_node,
371 "nvidia,dma-request-selector",
373 dev_err(&pdev->dev, "No DMA resource\n");
379 dma_ch = dmareq->start;
382 memregion = devm_request_mem_region(&pdev->dev, mem->start,
383 resource_size(mem), DRV_NAME);
385 dev_err(&pdev->dev, "Memory region already claimed\n");
390 i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
392 dev_err(&pdev->dev, "ioremap failed\n");
397 i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
398 i2s->capture_dma_data.wrap = 4;
399 i2s->capture_dma_data.width = 32;
400 i2s->capture_dma_data.req_sel = dma_ch;
402 i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
403 i2s->playback_dma_data.wrap = 4;
404 i2s->playback_dma_data.width = 32;
405 i2s->playback_dma_data.req_sel = dma_ch;
407 i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
409 ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
411 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
416 tegra_i2s_debug_add(i2s);
421 clk_put(i2s->clk_i2s);
426 static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
428 struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
430 snd_soc_unregister_dai(&pdev->dev);
432 tegra_i2s_debug_remove(i2s);
434 clk_put(i2s->clk_i2s);
439 static const struct of_device_id tegra_i2s_of_match[] __devinitconst = {
440 { .compatible = "nvidia,tegra20-i2s", },
444 static struct platform_driver tegra_i2s_driver = {
447 .owner = THIS_MODULE,
448 .of_match_table = tegra_i2s_of_match,
450 .probe = tegra_i2s_platform_probe,
451 .remove = __devexit_p(tegra_i2s_platform_remove),
453 module_platform_driver(tegra_i2s_driver);
455 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
456 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
457 MODULE_LICENSE("GPL");
458 MODULE_ALIAS("platform:" DRV_NAME);
459 MODULE_DEVICE_TABLE(of, tegra_i2s_of_match);