2 * Copyright (C) ST-Ericsson SA 2012
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
15 #ifndef UX500_MSP_I2S_H
16 #define UX500_MSP_I2S_H
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/asoc-ux500-msp.h>
21 #define MSP_INPUT_FREQ_APB 48000000
23 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
24 * 32 bits accesses (stereo).
26 enum msp_stereo_mode {
31 /* Direction (Transmit/Receive mode) */
37 /* Transmit and receive configuration register */
38 #define MSP_BIG_ENDIAN 0x00000000
39 #define MSP_LITTLE_ENDIAN 0x00001000
40 #define MSP_UNEXPECTED_FS_ABORT 0x00000000
41 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
42 #define MSP_NON_MODE_BIT_MASK 0x00009000
44 /* Global configuration register */
45 #define RX_ENABLE 0x00000001
46 #define RX_FIFO_ENABLE 0x00000002
47 #define RX_SYNC_SRG 0x00000010
48 #define RX_CLK_POL_RISING 0x00000020
49 #define RX_CLK_SEL_SRG 0x00000040
50 #define TX_ENABLE 0x00000100
51 #define TX_FIFO_ENABLE 0x00000200
52 #define TX_SYNC_SRG_PROG 0x00001800
53 #define TX_SYNC_SRG_AUTO 0x00001000
54 #define TX_CLK_POL_RISING 0x00002000
55 #define TX_CLK_SEL_SRG 0x00004000
56 #define TX_EXTRA_DELAY_ENABLE 0x00008000
57 #define SRG_ENABLE 0x00010000
58 #define FRAME_GEN_ENABLE 0x00100000
59 #define SRG_CLK_SEL_APB 0x00000000
60 #define RX_FIFO_SYNC_HI 0x00000000
61 #define TX_FIFO_SYNC_HI 0x00000000
62 #define SPI_CLK_MODE_NORMAL 0x00000000
64 #define MSP_FRAME_SIZE_AUTO -1
72 #define MSP_DMACR 0x18
91 #define MSP_IODLY 0x70
96 #define MSP_TSTDR 0x8c
98 #define MSP_PID0 0xfe0
99 #define MSP_PID1 0xfe4
100 #define MSP_PID2 0xfe8
101 #define MSP_PID3 0xfec
103 #define MSP_CID0 0xff0
104 #define MSP_CID1 0xff4
105 #define MSP_CID2 0xff8
106 #define MSP_CID3 0xffc
108 /* Protocol dependant parameters list */
109 #define RX_ENABLE_MASK BIT(0)
110 #define RX_FIFO_ENABLE_MASK BIT(1)
111 #define RX_FSYNC_MASK BIT(2)
112 #define DIRECT_COMPANDING_MASK BIT(3)
113 #define RX_SYNC_SEL_MASK BIT(4)
114 #define RX_CLK_POL_MASK BIT(5)
115 #define RX_CLK_SEL_MASK BIT(6)
116 #define LOOPBACK_MASK BIT(7)
117 #define TX_ENABLE_MASK BIT(8)
118 #define TX_FIFO_ENABLE_MASK BIT(9)
119 #define TX_FSYNC_MASK BIT(10)
120 #define TX_MSP_TDR_TSR BIT(11)
121 #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11))
122 #define TX_CLK_POL_MASK BIT(13)
123 #define TX_CLK_SEL_MASK BIT(14)
124 #define TX_EXTRA_DELAY_MASK BIT(15)
125 #define SRG_ENABLE_MASK BIT(16)
126 #define SRG_CLK_POL_MASK BIT(17)
127 #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18))
128 #define FRAME_GEN_EN_MASK BIT(20)
129 #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21))
130 #define SPI_BURST_MODE_MASK BIT(23)
133 #define RFFEN_SHIFT 1
134 #define RFSPOL_SHIFT 2
136 #define RFSSEL_SHIFT 4
137 #define RCKPOL_SHIFT 5
138 #define RCKSEL_SHIFT 6
141 #define TFFEN_SHIFT 9
142 #define TFSPOL_SHIFT 10
143 #define TFSSEL_SHIFT 11
144 #define TCKPOL_SHIFT 13
145 #define TCKSEL_SHIFT 14
146 #define TXDDL_SHIFT 15
147 #define SGEN_SHIFT 16
148 #define SCKPOL_SHIFT 17
149 #define SCKSEL_SHIFT 18
150 #define FGEN_SHIFT 20
151 #define SPICKM_SHIFT 21
152 #define TBSWAP_SHIFT 28
154 #define RCKPOL_MASK BIT(0)
155 #define TCKPOL_MASK BIT(0)
156 #define SPICKM_MASK (BIT(1) | BIT(0))
157 #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT)
158 #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT)
160 #define P1ELEN_SHIFT 0
161 #define P1FLEN_SHIFT 3
162 #define DTYP_SHIFT 10
163 #define ENDN_SHIFT 12
164 #define DDLY_SHIFT 13
165 #define FSIG_SHIFT 15
166 #define P2ELEN_SHIFT 16
167 #define P2FLEN_SHIFT 19
168 #define P2SM_SHIFT 26
169 #define P2EN_SHIFT 27
170 #define FSYNC_SHIFT 15
172 #define P1ELEN_MASK 0x00000007
173 #define P2ELEN_MASK 0x00070000
174 #define P1FLEN_MASK 0x00000378
175 #define P2FLEN_MASK 0x03780000
176 #define DDLY_MASK 0x00003000
177 #define DTYP_MASK 0x00000600
178 #define P2SM_MASK 0x04000000
179 #define P2EN_MASK 0x08000000
180 #define ENDN_MASK 0x00001000
181 #define TFSPOL_MASK 0x00000400
182 #define TBSWAP_MASK 0x30000000
183 #define COMPANDING_MODE_MASK 0x00000c00
184 #define FSYNC_MASK 0x00008000
186 #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK)
187 #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK)
188 #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK)
189 #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK)
190 #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK)
191 #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK)
192 #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK)
193 #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK)
194 #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK)
195 #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK)
196 #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK)
197 #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \
198 COMPANDING_MODE_MASK)
199 #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK)
202 #define RX_BUSY BIT(0)
203 #define RX_FIFO_EMPTY BIT(1)
204 #define RX_FIFO_FULL BIT(2)
205 #define TX_BUSY BIT(3)
206 #define TX_FIFO_EMPTY BIT(4)
207 #define TX_FIFO_FULL BIT(5)
209 #define RBUSY_SHIFT 0
212 #define TBUSY_SHIFT 3
216 /* Multichannel control register */
217 #define RMCEN_SHIFT 0
218 #define RMCSF_SHIFT 1
219 #define RCMPM_SHIFT 3
220 #define TMCEN_SHIFT 5
221 #define TNCSF_SHIFT 6
223 /* Sample rate generator register */
224 #define SCKDIV_SHIFT 0
225 #define FRWID_SHIFT 10
226 #define FRPER_SHIFT 16
228 #define SCK_DIV_MASK 0x0000003FF
229 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00)
230 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000)
232 /* DMA controller register */
233 #define RX_DMA_ENABLE BIT(0)
234 #define TX_DMA_ENABLE BIT(1)
236 #define RDMAE_SHIFT 0
237 #define TDMAE_SHIFT 1
239 /* Interrupt Register */
240 #define RX_SERVICE_INT BIT(0)
241 #define RX_OVERRUN_ERROR_INT BIT(1)
242 #define RX_FSYNC_ERR_INT BIT(2)
243 #define RX_FSYNC_INT BIT(3)
244 #define TX_SERVICE_INT BIT(4)
245 #define TX_UNDERRUN_ERR_INT BIT(5)
246 #define TX_FSYNC_ERR_INT BIT(6)
247 #define TX_FSYNC_INT BIT(7)
248 #define ALL_INT 0x000000ff
250 /* MSP test control register */
251 #define MSP_ITCR_ITEN BIT(0)
252 #define MSP_ITCR_TESTFIFO BIT(1)
260 /* Single or dual phase mode */
261 enum msp_phase_mode {
267 enum msp_frame_length {
272 MSP_FRAME_LEN_12 = 11,
273 MSP_FRAME_LEN_16 = 15,
274 MSP_FRAME_LEN_20 = 19,
275 MSP_FRAME_LEN_32 = 31,
276 MSP_FRAME_LEN_48 = 47,
277 MSP_FRAME_LEN_64 = 63
281 enum msp_elem_length {
292 enum msp_data_xfer_width {
293 MSP_DATA_TRANSFER_WIDTH_BYTE,
294 MSP_DATA_TRANSFER_WIDTH_HALFWORD,
295 MSP_DATA_TRANSFER_WIDTH_WORD
298 enum msp_frame_sync {
299 MSP_FSYNC_UNIGNORE = 0,
300 MSP_FSYNC_IGNORE = 1,
303 enum msp_phase2_start_mode {
304 MSP_PHASE2_START_MODE_IMEDIATE,
305 MSP_PHASE2_START_MODE_FSYNC
309 MSP_BTF_MS_BIT_FIRST = 0,
310 MSP_BTF_LS_BIT_FIRST = 1
314 MSP_FSYNC_POL_ACT_HI = 0,
315 MSP_FSYNC_POL_ACT_LO = 1
318 /* Data delay (in bit clock cycles) */
326 /* Configurations of clocks (transmit, receive or sample rate generator) */
328 MSP_FALLING_EDGE = 0,
334 MSP_SWAP_BYTE_PER_WORD = 1,
335 MSP_SWAP_BYTE_PER_HALF_WORD = 2,
336 MSP_SWAP_HALF_WORD_PER_WORD = 3
339 enum msp_compress_mode {
340 MSP_COMPRESS_MODE_LINEAR = 0,
341 MSP_COMPRESS_MODE_MU_LAW = 2,
342 MSP_COMPRESS_MODE_A_LAW = 3
345 enum msp_expand_mode {
346 MSP_EXPAND_MODE_LINEAR = 0,
347 MSP_EXPAND_MODE_LINEAR_SIGNED = 1,
348 MSP_EXPAND_MODE_MU_LAW = 2,
349 MSP_EXPAND_MODE_A_LAW = 3
352 #define MSP_FRAME_PERIOD_IN_MONO_MODE 256
353 #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32
354 #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16
359 MSP_PCM_COMPAND_PROTOCOL,
364 * No of registers to backup during
367 #define MAX_MSP_BACKUP_REGS 36
369 enum i2s_direction_t {
375 MSP_DATA_BITS_DEFAULT = -1,
376 MSP_DATA_BITS_8 = 0x00,
388 MSP_STATE_CONFIGURED = 1,
389 MSP_STATE_RUNNING = 2,
392 enum msp_rx_comparison_enable_mode {
393 MSP_COMPARISON_DISABLED = 0,
394 MSP_COMPARISON_NONEQUAL_ENABLED = 2,
395 MSP_COMPARISON_EQUAL_ENABLED = 3
398 struct msp_multichannel_config {
399 bool rx_multichannel_enable;
400 bool tx_multichannel_enable;
401 enum msp_rx_comparison_enable_mode rx_comparison_enable_mode;
403 u32 comparison_value;
405 u32 rx_channel_0_enable;
406 u32 rx_channel_1_enable;
407 u32 rx_channel_2_enable;
408 u32 rx_channel_3_enable;
409 u32 tx_channel_0_enable;
410 u32 tx_channel_1_enable;
411 u32 tx_channel_2_enable;
412 u32 tx_channel_3_enable;
415 struct msp_protdesc {
418 u32 rx_phase2_start_mode;
419 u32 tx_phase2_start_mode;
436 u32 rx_half_word_swap;
437 u32 tx_half_word_swap;
438 u32 compression_mode;
440 u32 frame_sync_ignore;
443 u32 clocks_per_frame;
446 struct ux500_msp_config {
447 unsigned int f_inputclk;
448 unsigned int rx_clk_sel;
449 unsigned int tx_clk_sel;
450 unsigned int srg_clk_sel;
451 unsigned int rx_fsync_pol;
452 unsigned int tx_fsync_pol;
453 unsigned int rx_fsync_sel;
454 unsigned int tx_fsync_sel;
455 unsigned int rx_fifo_config;
456 unsigned int tx_fifo_config;
457 unsigned int loopback_enable;
458 unsigned int tx_data_enable;
459 unsigned int default_protdesc;
460 struct msp_protdesc protdesc;
461 int multichannel_configured;
462 struct msp_multichannel_config multichannel_config;
463 unsigned int direction;
464 unsigned int protocol;
465 unsigned int frame_freq;
466 enum msp_data_size data_size;
467 unsigned int def_elem_len;
468 unsigned int iodelay;
473 void __iomem *registers;
475 struct stedma40_chan_cfg *dma_cfg_rx;
476 struct stedma40_chan_cfg *dma_cfg_tx;
477 enum msp_state msp_state;
479 unsigned int dir_busy;
481 unsigned int f_bitclk;
484 struct ux500_msp_dma_params {
485 unsigned int data_size;
486 struct stedma40_chan_cfg *dma_cfg;
489 struct msp_i2s_platform_data;
490 int ux500_msp_i2s_init_msp(struct platform_device *pdev,
491 struct ux500_msp **msp_p,
492 struct msp_i2s_platform_data *platform_data);
493 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
494 struct ux500_msp *msp);
495 int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config);
496 int ux500_msp_i2s_close(struct ux500_msp *msp,
498 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd,