2 * MikroTik RouterBOARD 4xx series support
4 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/platform_device.h>
13 #include <linux/irq.h>
14 #include <linux/mdio-gpio.h>
15 #include <linux/mmc/host.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/flash.h>
18 #include <linux/spi/mmc_spi.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
22 #include <asm/mach-ath79/ar71xx_regs.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/pci.h>
25 #include <asm/mach-ath79/rb4xx_cpld.h>
29 #include "dev-gpio-buttons.h"
30 #include "dev-leds-gpio.h"
32 #include "machtypes.h"
35 #define RB4XX_GPIO_USER_LED 4
36 #define RB4XX_GPIO_RESET_SWITCH 7
38 #define RB4XX_GPIO_CPLD_BASE 32
39 #define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
40 #define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
41 #define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
42 #define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
43 #define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
45 #define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
46 #define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
48 static struct gpio_led rb4xx_leds_gpio[] __initdata = {
50 .name = "rb4xx:yellow:user",
51 .gpio = RB4XX_GPIO_USER_LED,
54 .name = "rb4xx:green:led1",
55 .gpio = RB4XX_GPIO_CPLD_LED1,
58 .name = "rb4xx:green:led2",
59 .gpio = RB4XX_GPIO_CPLD_LED2,
62 .name = "rb4xx:green:led3",
63 .gpio = RB4XX_GPIO_CPLD_LED3,
66 .name = "rb4xx:green:led4",
67 .gpio = RB4XX_GPIO_CPLD_LED4,
70 .name = "rb4xx:green:led5",
71 .gpio = RB4XX_GPIO_CPLD_LED5,
76 static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
78 .desc = "reset_switch",
81 .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
82 .gpio = RB4XX_GPIO_RESET_SWITCH,
87 static struct platform_device rb4xx_nand_device = {
92 static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
96 .irq = ATH79_PCI_IRQ(2),
100 .irq = ATH79_PCI_IRQ(0),
104 .irq = ATH79_PCI_IRQ(1),
108 .irq = ATH79_PCI_IRQ(1),
112 .irq = ATH79_PCI_IRQ(2),
116 static struct mtd_partition rb4xx_partitions[] = {
118 .name = "routerboot",
121 .mask_flags = MTD_WRITEABLE,
123 .name = "hard_config",
126 .mask_flags = MTD_WRITEABLE,
131 .mask_flags = MTD_WRITEABLE,
133 .name = "soft_config",
139 static struct flash_platform_data rb4xx_flash_data = {
141 .parts = rb4xx_partitions,
142 .nr_parts = ARRAY_SIZE(rb4xx_partitions),
145 static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
146 .gpio_base = RB4XX_GPIO_CPLD_BASE,
149 static struct mmc_spi_platform_data rb4xx_mmc_data = {
150 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
153 static struct spi_board_info rb4xx_spi_info[] = {
157 .max_speed_hz = 25000000,
158 .modalias = "m25p80",
159 .platform_data = &rb4xx_flash_data,
163 .max_speed_hz = 25000000,
164 .modalias = "spi-rb4xx-cpld",
165 .platform_data = &rb4xx_cpld_data,
169 static struct spi_board_info rb4xx_microsd_info[] = {
173 .max_speed_hz = 25000000,
174 .modalias = "mmc_spi",
175 .platform_data = &rb4xx_mmc_data,
180 static struct resource rb4xx_spi_resources[] = {
182 .start = AR71XX_SPI_BASE,
183 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
184 .flags = IORESOURCE_MEM,
188 static struct platform_device rb4xx_spi_device = {
191 .resource = rb4xx_spi_resources,
192 .num_resources = ARRAY_SIZE(rb4xx_spi_resources),
195 static void __init rb4xx_generic_setup(void)
197 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
198 AR71XX_GPIO_FUNC_SPI_CS2_EN);
200 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
203 ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
204 ARRAY_SIZE(rb4xx_gpio_keys),
207 spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
208 platform_device_register(&rb4xx_spi_device);
209 platform_device_register(&rb4xx_nand_device);
212 static void __init rb411_setup(void)
214 rb4xx_generic_setup();
215 spi_register_board_info(rb4xx_microsd_info,
216 ARRAY_SIZE(rb4xx_microsd_info));
218 ath79_register_mdio(0, 0xfffffffc);
220 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
221 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
222 ath79_eth0_data.phy_mask = 0x00000003;
224 ath79_register_eth(0);
226 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
227 ath79_register_pci();
230 MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
233 static void __init rb411u_setup(void)
236 ath79_register_usb();
239 MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
242 #define RB433_LAN_PHYMASK BIT(0)
243 #define RB433_WAN_PHYMASK BIT(4)
244 #define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
246 static void __init rb433_setup(void)
248 rb4xx_generic_setup();
249 spi_register_board_info(rb4xx_microsd_info,
250 ARRAY_SIZE(rb4xx_microsd_info));
252 ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
254 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
255 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
256 ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
258 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
259 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
260 ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
262 ath79_register_eth(1);
263 ath79_register_eth(0);
265 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
266 ath79_register_pci();
269 MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
272 static void __init rb433u_setup(void)
275 ath79_register_usb();
278 MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
281 #define RB450_LAN_PHYMASK BIT(0)
282 #define RB450_WAN_PHYMASK BIT(4)
283 #define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
285 static void __init rb450_generic_setup(int gige)
287 rb4xx_generic_setup();
288 ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
290 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
291 ath79_eth0_data.phy_if_mode = (gige) ?
292 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
293 ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
295 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
296 ath79_eth1_data.phy_if_mode = (gige) ?
297 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
298 ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
300 ath79_register_eth(1);
301 ath79_register_eth(0);
304 static void __init rb450_setup(void)
306 rb450_generic_setup(0);
309 MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
312 static void __init rb450g_setup(void)
314 rb450_generic_setup(1);
315 spi_register_board_info(rb4xx_microsd_info,
316 ARRAY_SIZE(rb4xx_microsd_info));
319 MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
322 static void __init rb493_setup(void)
324 rb4xx_generic_setup();
326 ath79_register_mdio(0, 0x3fffff00);
328 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
329 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
330 ath79_eth0_data.speed = SPEED_100;
331 ath79_eth0_data.duplex = DUPLEX_FULL;
333 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
334 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
335 ath79_eth1_data.phy_mask = 0x00000001;
337 ath79_register_eth(0);
338 ath79_register_eth(1);
340 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
341 ath79_register_pci();
344 MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
347 #define RB493G_GPIO_MDIO_MDC 7
348 #define RB493G_GPIO_MDIO_DATA 8
350 #define RB493G_MDIO_PHYMASK BIT(0)
352 static struct mdio_gpio_platform_data rb493g_mdio_data = {
353 .mdc = RB493G_GPIO_MDIO_MDC,
354 .mdio = RB493G_GPIO_MDIO_DATA,
356 .phy_mask = ~RB493G_MDIO_PHYMASK,
359 static struct platform_device rb493g_mdio_device = {
363 .platform_data = &rb493g_mdio_data,
367 static void __init rb493g_setup(void)
369 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
370 AR71XX_GPIO_FUNC_SPI_CS2_EN);
372 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
375 spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
376 platform_device_register(&rb4xx_spi_device);
377 platform_device_register(&rb4xx_nand_device);
379 ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
381 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
382 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
383 ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
384 ath79_eth0_data.speed = SPEED_1000;
385 ath79_eth0_data.duplex = DUPLEX_FULL;
387 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
388 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
389 ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
390 ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
391 ath79_eth1_data.speed = SPEED_1000;
392 ath79_eth1_data.duplex = DUPLEX_FULL;
394 platform_device_register(&rb493g_mdio_device);
396 ath79_register_eth(1);
397 ath79_register_eth(0);
399 ath79_register_usb();
401 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
402 ath79_register_pci();
405 MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",