2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/cache.h>
17 #define AG71XX_DEFAULT_MSG_ENABLE \
27 static int ag71xx_msg_level = -1;
29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
34 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
36 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
37 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
38 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
40 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
42 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
47 static void ag71xx_dump_regs(struct ag71xx *ag)
49 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
52 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
53 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
54 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
55 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
56 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
58 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
60 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
61 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
65 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
66 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
75 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
76 ag->dev->name, label, intr,
77 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
78 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
79 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
80 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
81 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
82 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
90 dma_free_coherent(NULL, ring->size * ring->desc_size,
91 ring->descs_cpu, ring->descs_dma);
94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
99 ring->desc_size = sizeof(struct ag71xx_desc);
100 if (ring->desc_size % cache_line_size()) {
101 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
102 ring, ring->desc_size,
103 roundup(ring->desc_size, cache_line_size()));
104 ring->desc_size = roundup(ring->desc_size, cache_line_size());
107 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
108 &ring->descs_dma, GFP_ATOMIC);
109 if (!ring->descs_cpu) {
116 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
122 for (i = 0; i < size; i++) {
123 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring, i, ring->buf[i].desc);
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 struct ag71xx_ring *ring = &ag->tx_ring;
137 struct net_device *dev = ag->dev;
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
147 if (ring->buf[i].skb)
148 dev_kfree_skb_any(ring->buf[i].skb);
150 ring->buf[i].skb = NULL;
155 /* flush descriptors */
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
162 struct ag71xx_ring *ring = &ag->tx_ring;
165 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
169 ring->buf[i].desc->ctrl = DESC_EMPTY;
170 ring->buf[i].skb = NULL;
173 /* flush descriptors */
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
182 struct ag71xx_ring *ring = &ag->rx_ring;
188 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189 if (ring->buf[i].skb)
190 kfree_skb(ring->buf[i].skb);
194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
196 struct ag71xx_ring *ring = &ag->rx_ring;
201 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
202 ring->buf[i].desc->next = (u32) (ring->descs_dma +
203 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
205 DBG("ag71xx: RX desc at %p, next is %08x\n",
207 ring->buf[i].desc->next);
210 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
213 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
219 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
223 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
225 ring->buf[i].skb = skb;
226 ring->buf[i].desc->data = virt_to_phys(skb->data);
227 ring->buf[i].desc->ctrl = DESC_EMPTY;
230 /* flush descriptors */
239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
241 struct ag71xx_ring *ring = &ag->rx_ring;
245 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
248 i = ring->dirty % AG71XX_RX_RING_SIZE;
250 if (ring->buf[i].skb == NULL) {
253 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
257 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
260 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
263 ring->buf[i].skb = skb;
264 ring->buf[i].desc->data = virt_to_phys(skb->data);
267 ring->buf[i].desc->ctrl = DESC_EMPTY;
271 /* flush descriptors */
274 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
279 static int ag71xx_rings_init(struct ag71xx *ag)
283 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
287 ag71xx_ring_tx_init(ag);
289 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
293 ret = ag71xx_ring_rx_init(ag);
297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
299 ag71xx_ring_rx_clean(ag);
300 ag71xx_ring_free(&ag->rx_ring);
302 ag71xx_ring_tx_clean(ag);
303 ag71xx_ring_free(&ag->tx_ring);
306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
310 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
311 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
313 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
315 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
316 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
319 static void ag71xx_dma_reset(struct ag71xx *ag)
323 ag71xx_dump_dma_regs(ag);
326 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
327 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
329 /* clear descriptor addresses */
330 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
331 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
333 /* clear pending RX/TX interrupts */
334 for (i = 0; i < 256; i++) {
335 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
336 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
339 /* clear pending errors */
340 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
341 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
343 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
344 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
347 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
348 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
351 ag71xx_dump_dma_regs(ag);
354 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
355 MAC_CFG1_SRX | MAC_CFG1_STX)
357 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
359 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
360 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
361 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
362 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
363 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
366 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
367 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
368 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
369 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
370 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
371 FIFO_CFG5_17 | FIFO_CFG5_SF)
373 static void ag71xx_hw_init(struct ag71xx *ag)
375 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
377 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
380 ar71xx_device_stop(pdata->reset_bit);
382 ar71xx_device_start(pdata->reset_bit);
385 /* setup MAC configuration registers */
386 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
387 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
388 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
390 /* setup max frame length */
391 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
393 /* setup MII interface type */
394 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
396 /* setup FIFO configuration registers */
397 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
398 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
399 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
400 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
401 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
403 ag71xx_dma_reset(ag);
406 static void ag71xx_hw_start(struct ag71xx *ag)
408 /* start RX engine */
409 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
411 /* enable interrupts */
412 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
415 static void ag71xx_hw_stop(struct ag71xx *ag)
417 /* disable all interrupts */
418 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_dma_reset(ag);
423 static int ag71xx_open(struct net_device *dev)
425 struct ag71xx *ag = netdev_priv(dev);
428 ret = ag71xx_rings_init(ag);
432 napi_enable(&ag->napi);
434 netif_carrier_off(dev);
435 ag71xx_phy_start(ag);
437 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
438 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
440 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
444 netif_start_queue(dev);
449 ag71xx_rings_cleanup(ag);
453 static int ag71xx_stop(struct net_device *dev)
455 struct ag71xx *ag = netdev_priv(dev);
458 spin_lock_irqsave(&ag->lock, flags);
460 netif_stop_queue(dev);
464 netif_carrier_off(dev);
467 napi_disable(&ag->napi);
468 del_timer_sync(&ag->oom_timer);
470 spin_unlock_irqrestore(&ag->lock, flags);
472 ag71xx_rings_cleanup(ag);
477 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
479 struct ag71xx *ag = netdev_priv(dev);
480 struct ag71xx_ring *ring = &ag->tx_ring;
481 struct ag71xx_desc *desc;
484 i = ring->curr % AG71XX_TX_RING_SIZE;
485 desc = ring->buf[i].desc;
487 if (!ag71xx_desc_empty(desc))
490 ag71xx_add_ar8216_header(ag, skb);
493 DBG("%s: packet len is too small\n", ag->dev->name);
497 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
499 ring->buf[i].skb = skb;
501 /* setup descriptor fields */
502 desc->data = virt_to_phys(skb->data);
503 desc->ctrl = (skb->len & DESC_PKTLEN_M);
505 /* flush descriptor */
509 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
510 DBG("%s: tx queue full\n", ag->dev->name);
511 netif_stop_queue(dev);
514 DBG("%s: packet injected into TX queue\n", ag->dev->name);
516 /* enable TX engine */
517 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
519 dev->trans_start = jiffies;
524 dev->stats.tx_dropped++;
530 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
532 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
533 struct ag71xx *ag = netdev_priv(dev);
538 if (ag->phy_dev == NULL)
541 spin_lock_irq(&ag->lock);
542 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
543 spin_unlock_irq(&ag->lock);
548 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
554 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
561 if (ag->phy_dev == NULL)
564 return phy_mii_ioctl(ag->phy_dev, data, cmd);
573 static void ag71xx_oom_timer_handler(unsigned long data)
575 struct net_device *dev = (struct net_device *) data;
576 struct ag71xx *ag = netdev_priv(dev);
578 netif_rx_schedule(dev, &ag->napi);
581 static void ag71xx_tx_timeout(struct net_device *dev)
583 struct ag71xx *ag = netdev_priv(dev);
585 if (netif_msg_tx_err(ag))
586 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
588 schedule_work(&ag->restart_work);
591 static void ag71xx_restart_work_func(struct work_struct *work)
593 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
595 ag71xx_stop(ag->dev);
596 ag71xx_open(ag->dev);
599 static void ag71xx_tx_packets(struct ag71xx *ag)
601 struct ag71xx_ring *ring = &ag->tx_ring;
604 DBG("%s: processing TX ring\n", ag->dev->name);
607 while (ring->dirty != ring->curr) {
608 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
609 struct ag71xx_desc *desc = ring->buf[i].desc;
610 struct sk_buff *skb = ring->buf[i].skb;
612 if (!ag71xx_desc_empty(desc))
615 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
617 ag->dev->stats.tx_bytes += skb->len;
618 ag->dev->stats.tx_packets++;
620 dev_kfree_skb_any(skb);
621 ring->buf[i].skb = NULL;
627 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
629 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
630 netif_wake_queue(ag->dev);
634 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
636 struct net_device *dev = ag->dev;
637 struct ag71xx_ring *ring = &ag->rx_ring;
640 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
641 dev->name, limit, ring->curr, ring->dirty);
643 while (done < limit) {
644 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
645 struct ag71xx_desc *desc = ring->buf[i].desc;
649 if (ag71xx_desc_empty(desc))
652 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
657 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
659 skb = ring->buf[i].skb;
660 pktlen = ag71xx_desc_pktlen(desc);
661 pktlen -= ETH_FCS_LEN;
663 skb_put(skb, pktlen);
666 skb->ip_summed = CHECKSUM_NONE;
668 dev->last_rx = jiffies;
669 dev->stats.rx_packets++;
670 dev->stats.rx_bytes += pktlen;
672 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
673 dev->stats.rx_dropped++;
676 skb->protocol = eth_type_trans(skb, dev);
677 netif_receive_skb(skb);
680 ring->buf[i].skb = NULL;
686 ag71xx_ring_rx_refill(ag);
688 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
689 dev->name, ring->curr, ring->dirty, done);
694 static int ag71xx_poll(struct napi_struct *napi, int limit)
696 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
697 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
698 struct net_device *dev = ag->dev;
699 struct ag71xx_ring *rx_ring;
705 ag71xx_tx_packets(ag);
707 DBG("%s: processing RX ring\n", dev->name);
708 done = ag71xx_rx_packets(ag, limit);
710 rx_ring = &ag->rx_ring;
711 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
714 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
715 if (unlikely(status & RX_STATUS_OF)) {
716 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
717 dev->stats.rx_fifo_errors++;
720 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
724 if (status & RX_STATUS_PR)
727 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
728 if (status & TX_STATUS_PS)
731 DBG("%s: disable polling mode, done=%d, limit=%d\n",
732 dev->name, done, limit);
734 netif_rx_complete(dev, napi);
736 /* enable interrupts */
737 spin_lock_irqsave(&ag->lock, flags);
738 ag71xx_int_enable(ag, AG71XX_INT_POLL);
739 spin_unlock_irqrestore(&ag->lock, flags);
744 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
745 dev->name, done, limit);
749 if (netif_msg_rx_err(ag))
750 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
752 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
753 netif_rx_complete(dev, napi);
757 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
759 struct net_device *dev = dev_id;
760 struct ag71xx *ag = netdev_priv(dev);
763 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
764 ag71xx_dump_intr(ag, "raw", status);
766 if (unlikely(!status))
769 if (unlikely(status & AG71XX_INT_ERR)) {
770 if (status & AG71XX_INT_TX_BE) {
771 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
772 dev_err(&dev->dev, "TX BUS error\n");
774 if (status & AG71XX_INT_RX_BE) {
775 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
776 dev_err(&dev->dev, "RX BUS error\n");
780 if (likely(status & AG71XX_INT_POLL)) {
781 ag71xx_int_disable(ag, AG71XX_INT_POLL);
782 DBG("%s: enable polling mode\n", dev->name);
783 netif_rx_schedule(dev, &ag->napi);
789 static void ag71xx_set_multicast_list(struct net_device *dev)
794 static int __init ag71xx_probe(struct platform_device *pdev)
796 struct net_device *dev;
797 struct resource *res;
799 struct ag71xx_platform_data *pdata;
802 pdata = pdev->dev.platform_data;
804 dev_err(&pdev->dev, "no platform data specified\n");
809 dev = alloc_etherdev(sizeof(*ag));
811 dev_err(&pdev->dev, "alloc_etherdev failed\n");
816 SET_NETDEV_DEV(dev, &pdev->dev);
818 ag = netdev_priv(dev);
821 ag->mii_bus = ag71xx_mdio_bus->mii_bus;
822 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
823 AG71XX_DEFAULT_MSG_ENABLE);
824 spin_lock_init(&ag->lock);
826 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
828 dev_err(&pdev->dev, "no mac_base resource found\n");
833 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
835 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
840 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
842 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
847 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
849 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
854 dev->irq = platform_get_irq(pdev, 0);
855 err = request_irq(dev->irq, ag71xx_interrupt,
856 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
859 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
860 goto err_unmap_mii_ctrl;
863 dev->base_addr = (unsigned long)ag->mac_base;
864 dev->open = ag71xx_open;
865 dev->stop = ag71xx_stop;
866 dev->hard_start_xmit = ag71xx_hard_start_xmit;
867 dev->set_multicast_list = ag71xx_set_multicast_list;
868 dev->do_ioctl = ag71xx_do_ioctl;
869 dev->ethtool_ops = &ag71xx_ethtool_ops;
871 dev->tx_timeout = ag71xx_tx_timeout;
872 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
874 init_timer(&ag->oom_timer);
875 ag->oom_timer.data = (unsigned long) dev;
876 ag->oom_timer.function = ag71xx_oom_timer_handler;
878 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
880 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
882 err = register_netdev(dev);
884 dev_err(&pdev->dev, "unable to register net device\n");
888 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
889 dev->name, dev->base_addr, dev->irq);
891 ag71xx_dump_regs(ag);
895 ag71xx_dump_regs(ag);
897 /* Reset the mdio bus explicitly */
899 mutex_lock(&ag->mii_bus->mdio_lock);
900 ag->mii_bus->reset(ag->mii_bus);
901 mutex_unlock(&ag->mii_bus->mdio_lock);
904 err = ag71xx_phy_connect(ag);
906 goto err_unregister_netdev;
908 platform_set_drvdata(pdev, dev);
912 err_unregister_netdev:
913 unregister_netdev(dev);
915 free_irq(dev->irq, dev);
917 iounmap(ag->mii_ctrl);
919 iounmap(ag->mac_base);
923 platform_set_drvdata(pdev, NULL);
927 static int __exit ag71xx_remove(struct platform_device *pdev)
929 struct net_device *dev = platform_get_drvdata(pdev);
932 struct ag71xx *ag = netdev_priv(dev);
934 ag71xx_phy_disconnect(ag);
935 unregister_netdev(dev);
936 free_irq(dev->irq, dev);
937 iounmap(ag->mii_ctrl);
938 iounmap(ag->mac_base);
940 platform_set_drvdata(pdev, NULL);
946 static struct platform_driver ag71xx_driver = {
947 .probe = ag71xx_probe,
948 .remove = __exit_p(ag71xx_remove),
950 .name = AG71XX_DRV_NAME,
954 static int __init ag71xx_module_init(void)
958 ret = ag71xx_mdio_driver_init();
962 ret = platform_driver_register(&ag71xx_driver);
969 ag71xx_mdio_driver_exit();
974 static void __exit ag71xx_module_exit(void)
976 platform_driver_unregister(&ag71xx_driver);
977 ag71xx_mdio_driver_exit();
980 module_init(ag71xx_module_init);
981 module_exit(ag71xx_module_exit);
983 MODULE_VERSION(AG71XX_DRV_VERSION);
984 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
985 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
986 MODULE_LICENSE("GPL v2");
987 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);