target/linux/bcm53xx/patches-3.18/131-ARM-BCM5301X-Implement-SMP-support.patch

   1 From 707ab07695ea8953a5bb56512e7bb38ca79c5c38 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Thu, 19 Feb 2015 23:27:59 +0100
   4 Subject: [PATCH V2] ARM: BCM5301X: Implement SMP support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  10 ---
  11 V2: Change code after receiving Florian's comments:
  12     1) Use "mmio-sram"
  13     2) Remove commented out ASM call
  14     3) Fix coding style in ASM
  15     4) Simplify finding OF node
  16 ---
  17  Documentation/devicetree/bindings/arm/bcm4708.txt |  24 ++++
  18  Documentation/devicetree/bindings/arm/cpus.txt    |   1 +
  19  arch/arm/boot/dts/bcm4708.dtsi                    |  13 ++
  20  arch/arm/mach-bcm/Makefile                        |   3 +
  21  arch/arm/mach-bcm/bcm5301x_headsmp.S              |  45 ++++++
  22  arch/arm/mach-bcm/bcm5301x_smp.c                  | 158 ++++++++++++++++++++++
  23  6 files changed, 244 insertions(+)
  24  create mode 100644 arch/arm/mach-bcm/bcm5301x_headsmp.S
  25  create mode 100644 arch/arm/mach-bcm/bcm5301x_smp.c
  26
  27 diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm4708.txt
  28 index 6b0f49f..3dd0e9d 100644
  29 --- a/Documentation/devicetree/bindings/arm/bcm4708.txt
  30 +++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
  31 @@ -6,3 +6,27 @@ Boards with the BCM4708 SoC shall have the following properties:
  32  Required root node property:
  33
  34  compatible = "brcm,bcm4708";
  35 +
  36 +Optional sub-node properties:
  37 +
  38 +compatible = "mmio-sram" for SRAM access with IO memory region
  39 +               This is needed for SMP-capable SoCs which use part of
  40 +               SRAM for storing location of code to be executed by the
  41 +               extra cores.
  42 +               SMP support requires another sub-node with compatible
  43 +               property "brcm,bcm4708-sysram".
  44 +
  45 +Example:
  46 +
  47 +       sysram@ffff0000 {
  48 +               compatible = "mmio-sram";
  49 +               reg = <0xffff0000 0x10000>;
  50 +               #address-cells = <1>;
  51 +               #size-cells = <1>;
  52 +               ranges = <0 0xffff0000 0x10000>;
  53 +
  54 +               smp-sysram@0 {
  55 +                       compatible = "brcm,bcm4708-sysram";
  56 +                       reg = <0x0 0x1000>;
  57 +               };
  58 +       };
  59 diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
  60 index 6aa331d..3507ae3 100644
  61 --- a/Documentation/devicetree/bindings/arm/cpus.txt
  62 +++ b/Documentation/devicetree/bindings/arm/cpus.txt
  63 @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below.
  64                           can be one of:
  65                             "allwinner,sun6i-a31"
  66                             "arm,psci"
  67 +                           "brcm,bcm4708-smp"
  68                             "brcm,brahma-b15"
  69                             "marvell,armada-375-smp"
  70                             "marvell,armada-380-smp"
  71 diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
  72 index 31141e8..c0af5cc 100644
  73 --- a/arch/arm/boot/dts/bcm4708.dtsi
  74 +++ b/arch/arm/boot/dts/bcm4708.dtsi
  75 @@ -15,6 +15,7 @@
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79 +               enable-method = "brcm,bcm4708-smp";
  80
  81                 cpu@0 {
  82                         device_type = "cpu";
  83 @@ -31,4 +32,16 @@
  84                 };
  85         };
  86
  87 +       sysram@ffff0000 {
  88 +               compatible = "mmio-sram";
  89 +               reg = <0xffff0000 0x10000>;
  90 +               #address-cells = <1>;
  91 +               #size-cells = <1>;
  92 +               ranges = <0 0xffff0000 0x10000>;
  93 +
  94 +               smp-sysram@0 {
  95 +                       compatible = "brcm,bcm4708-sysram";
  96 +                       reg = <0x0 0x1000>;
  97 +               };
  98 +       };
  99  };
 100 diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
 101 index 4c38674..ca12727 100644
 102 --- a/arch/arm/mach-bcm/Makefile
 103 +++ b/arch/arm/mach-bcm/Makefile
 104 @@ -33,6 +33,9 @@ obj-$(CONFIG_ARCH_BCM2835)    += board_bcm2835.o
 105
 106  # BCM5301X
 107  obj-$(CONFIG_ARCH_BCM_5301X)   += bcm_5301x.o
 108 +ifeq ($(CONFIG_SMP),y)
 109 +obj-$(CONFIG_ARCH_BCM_5301X)   += bcm5301x_smp.o bcm5301x_headsmp.o
 110 +endif
 111
 112  # BCM63XXx
 113  obj-$(CONFIG_ARCH_BCM_63XX)    := bcm63xx.o
 114 diff --git a/arch/arm/mach-bcm/bcm5301x_headsmp.S b/arch/arm/mach-bcm/bcm5301x_headsmp.S
 115 new file mode 100644
 116 index 0000000..9ca8d20
 117 --- /dev/null
 118 +++ b/arch/arm/mach-bcm/bcm5301x_headsmp.S
 119 @@ -0,0 +1,45 @@
 120 +/*
 121 + * Broadcom BCM470X / BCM5301X ARM platform code.
 122 + *
 123 + * Copyright (c) 2003 ARM Limited
 124 + * All Rights Reserved
 125 + *
 126 + * Licensed under the GNU/GPL. See COPYING for details.
 127 + */
 128 +#include <linux/linkage.h>
 129 +
 130 +/*
 131 + * BCM5301X specific entry point for secondary CPUs.
 132 + */
 133 +ENTRY(bcm5301x_secondary_startup)
 134 +       mrc     p15, 0, r0, c0, c0, 5
 135 +       and     r0, r0, #15
 136 +       adr     r4, 1f
 137 +       ldmia   r4, {r5, r6}
 138 +       sub     r4, r4, r5
 139 +       add     r6, r6, r4
 140 +pen:   ldr     r7, [r6]
 141 +       cmp     r7, r0
 142 +       bne     pen
 143 +
 144 +       /*
 145 +        * In case L1 cache has unpredictable contents at power-up
 146 +        * clean its contents without flushing.
 147 +        */
 148 +       bl      v7_invalidate_l1
 149 +
 150 +       mov     r0, #0
 151 +       mcr     p15, 0, r0, c7, c5, 0   /* Invalidate icache */
 152 +       dsb
 153 +       isb
 154 +
 155 +       /*
 156 +        * we've been released from the holding pen: secondary_stack
 157 +        * should now contain the SVC stack for this core
 158 +        */
 159 +       b       secondary_startup
 160 +ENDPROC(bcm5301x_secondary_startup)
 161 +
 162 +       .align 2
 163 +1:     .long   .
 164 +       .long   pen_release
 165 diff --git a/arch/arm/mach-bcm/bcm5301x_smp.c b/arch/arm/mach-bcm/bcm5301x_smp.c
 166 new file mode 100644
 167 index 0000000..45d7089
 168 --- /dev/null
 169 +++ b/arch/arm/mach-bcm/bcm5301x_smp.c
 170 @@ -0,0 +1,158 @@
 171 +/*
 172 + * Broadcom BCM470X / BCM5301X ARM platform code.
 173 + *
 174 + * Copyright (C) 2002 ARM Ltd.
 175 + * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
 176 + *
 177 + * Licensed under the GNU/GPL. See COPYING for details.
 178 + */
 179 +
 180 +#include <asm/cacheflush.h>
 181 +#include <asm/delay.h>
 182 +#include <asm/smp_plat.h>
 183 +#include <asm/smp_scu.h>
 184 +
 185 +#include <linux/clockchips.h>
 186 +#include <linux/of.h>
 187 +#include <linux/of_address.h>
 188 +
 189 +#define SOC_ROM_LUT_OFF                0x400
 190 +
 191 +extern void bcm5301x_secondary_startup(void);
 192 +
 193 +static void __cpuinit write_pen_release(int val)
 194 +{
 195 +       pen_release = val;
 196 +       smp_wmb();
 197 +       sync_cache_w(&pen_release);
 198 +}
 199 +
 200 +static DEFINE_SPINLOCK(boot_lock);
 201 +
 202 +static void __init bcm5301x_smp_secondary_set_entry(void (*entry_point)(void))
 203 +{
 204 +       void __iomem *sysram_base_addr = NULL;
 205 +       struct device_node *node;
 206 +
 207 +       node = of_find_compatible_node(NULL, NULL, "brcm,bcm4708-sysram");
 208 +       if (!of_device_is_available(node))
 209 +               return;
 210 +
 211 +       sysram_base_addr = of_iomap(node, 0);
 212 +       if (!sysram_base_addr) {
 213 +               pr_warn("Failed to map sysram\n");
 214 +               return;
 215 +       }
 216 +
 217 +       writel(virt_to_phys(entry_point), sysram_base_addr + SOC_ROM_LUT_OFF);
 218 +
 219 +       dsb_sev();      /* Exit WFI */
 220 +       mb();           /* make sure write buffer is drained */
 221 +
 222 +       iounmap(sysram_base_addr);
 223 +}
 224 +
 225 +static void __init bcm5301x_smp_prepare_cpus(unsigned int max_cpus)
 226 +{
 227 +       void __iomem *scu_base;
 228 +
 229 +       if (!scu_a9_has_base()) {
 230 +               pr_warn("Unknown SCU base\n");
 231 +               return;
 232 +       }
 233 +
 234 +       scu_base = ioremap((phys_addr_t)scu_a9_get_base(), SZ_256);
 235 +       if (!scu_base) {
 236 +               pr_err("Failed to remap SCU\n");
 237 +               return;
 238 +       }
 239 +
 240 +       /* Initialise the SCU */
 241 +       scu_enable(scu_base);
 242 +
 243 +       /* Let CPUs know where to start */
 244 +       bcm5301x_smp_secondary_set_entry(bcm5301x_secondary_startup);
 245 +
 246 +       iounmap(scu_base);
 247 +}
 248 +
 249 +static void __cpuinit bcm5301x_smp_secondary_init(unsigned int cpu)
 250 +{
 251 +       trace_hardirqs_off();
 252 +
 253 +       /*
 254 +        * let the primary processor know we're out of the
 255 +        * pen, then head off into the C entry point
 256 +        */
 257 +       write_pen_release(-1);
 258 +
 259 +       /*
 260 +        * Synchronise with the boot thread.
 261 +        */
 262 +       spin_lock(&boot_lock);
 263 +       spin_unlock(&boot_lock);
 264 +}
 265 +
 266 +static int __cpuinit bcm5301x_smp_boot_secondary(unsigned int cpu,
 267 +                                                struct task_struct *idle)
 268 +{
 269 +       unsigned long timeout;
 270 +
 271 +       /*
 272 +        * set synchronisation state between this boot processor
 273 +        * and the secondary one
 274 +        */
 275 +       spin_lock(&boot_lock);
 276 +
 277 +       /*
 278 +        * The secondary processor is waiting to be released from
 279 +        * the holding pen - release it, then wait for it to flag
 280 +        * that it has been released by resetting pen_release.
 281 +        *
 282 +        * Note that "pen_release" is the hardware CPU ID, whereas
 283 +        * "cpu" is Linux's internal ID.
 284 +        */
 285 +       write_pen_release(cpu_logical_map(cpu));
 286 +
 287 +        /* Send the secondary CPU SEV */
 288 +       dsb_sev();
 289 +
 290 +       udelay(100);
 291 +
 292 +       /*
 293 +        * Send the secondary CPU a soft interrupt, thereby causing
 294 +        * the boot monitor to read the system wide flags register,
 295 +        * and branch to the address found there.
 296 +        */
 297 +       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 298 +
 299 +       /*
 300 +        * Timeout set on purpose in jiffies so that on slow processors
 301 +        * that must also have low HZ it will wait longer.
 302 +        */
 303 +       timeout = jiffies + (HZ * 10);
 304 +       while (time_before(jiffies, timeout)) {
 305 +               smp_rmb();
 306 +               if (pen_release == -1)
 307 +                       break;
 308 +
 309 +               udelay(10);
 310 +       }
 311 +
 312 +       /*
 313 +        * now the secondary core is starting up let it run its
 314 +        * calibrations, then wait for it to finish
 315 +        */
 316 +       spin_unlock(&boot_lock);
 317 +
 318 +       return pen_release != -1 ? -ENOSYS : 0;
 319 +}
 320 +
 321 +static struct smp_operations bcm5301x_smp_ops __initdata = {
 322 +       .smp_prepare_cpus       = bcm5301x_smp_prepare_cpus,
 323 +       .smp_secondary_init     = bcm5301x_smp_secondary_init,
 324 +       .smp_boot_secondary     = bcm5301x_smp_boot_secondary,
 325 +};
 326 +
 327 +CPU_METHOD_OF_DECLARE(bcm5301x_smp, "brcm,bcm4708-smp",
 328 +                     &bcm5301x_smp_ops);
 329 --
 330 1.8.4.5
 331