target/linux/bcm53xx/patches-4.4/083-0001-spi-bcm-qspi-Add-Broadcom-MSPI-driver.patch

   1 From fa236a7ef24048bafaeed13f68df35a819794758 Mon Sep 17 00:00:00 2001
   2 From: Kamal Dasu <kdasu.kdev@gmail.com>
   3 Date: Wed, 24 Aug 2016 18:04:23 -0400
   4 Subject: [PATCH] spi: bcm-qspi: Add Broadcom MSPI driver
   5
   6 Master SPI driver for Broadcom settop, iProc SoCs. The driver
   7 is used for devices that use SPI protocol on BRCMSTB, NSP, NS2
   8 SoCs. SoC platform driver call exported porbe(), remove()
   9 and suspend/resume pm_ops implemented in this common driver.
  10
  11 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
  12 Signed-off-by: Yendapally Reddy Dhananjaya Reddy
  13 Signed-off-by: Mark Brown <broonie@kernel.org>
  14 ---
  15  drivers/spi/Kconfig        |  10 +
  16  drivers/spi/Makefile       |   1 +
  17  drivers/spi/spi-bcm-qspi.c | 712 +++++++++++++++++++++++++++++++++++++++++++++
  18  drivers/spi/spi-bcm-qspi.h |  63 ++++
  19  4 files changed, 786 insertions(+)
  20  create mode 100644 drivers/spi/spi-bcm-qspi.c
  21  create mode 100644 drivers/spi/spi-bcm-qspi.h
  22
  23 --- a/drivers/spi/Kconfig
  24 +++ b/drivers/spi/Kconfig
  25 @@ -147,6 +147,16 @@ config SPI_BCM63XX_HSSPI
  26           This enables support for the High Speed SPI controller present on
  27           newer Broadcom BCM63XX SoCs.
  28
  29 +config SPI_BCM_QSPI
  30 +       tristate "Broadcom BSPI and MSPI controller support"
  31 +       depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || COMPILE_TEST
  32 +       default ARCH_BCM_IPROC
  33 +       help
  34 +         Enables support for the Broadcom SPI flash and MSPI controller.
  35 +         Select this option for any one of BRCMSTB, iProc NSP and NS2 SoCs
  36 +         based platforms. This driver works for both SPI master for spi-nor
  37 +         flash device as well as MSPI device.
  38 +
  39  config SPI_BITBANG
  40         tristate "Utilities for Bitbanging SPI masters"
  41         help
  42 --- a/drivers/spi/Makefile
  43 +++ b/drivers/spi/Makefile
  44 @@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM2835AUX)          += spi-bcm
  45  obj-$(CONFIG_SPI_BCM53XX)              += spi-bcm53xx.o
  46  obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o
  47  obj-$(CONFIG_SPI_BCM63XX_HSSPI)                += spi-bcm63xx-hsspi.o
  48 +obj-$(CONFIG_SPI_BCM_QSPI)             += spi-bcm-qspi.o
  49  obj-$(CONFIG_SPI_BFIN5XX)              += spi-bfin5xx.o
  50  obj-$(CONFIG_SPI_ADI_V3)                += spi-adi-v3.o
  51  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
  52 --- /dev/null
  53 +++ b/drivers/spi/spi-bcm-qspi.c
  54 @@ -0,0 +1,712 @@
  55 +/*
  56 + * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers
  57 + *
  58 + * Copyright 2016 Broadcom
  59 + *
  60 + * This program is free software; you can redistribute it and/or modify
  61 + * it under the terms of the GNU General Public License, version 2, as
  62 + * published by the Free Software Foundation (the "GPL").
  63 + *
  64 + * This program is distributed in the hope that it will be useful, but
  65 + * WITHOUT ANY WARRANTY; without even the implied warranty of
  66 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  67 + * General Public License version 2 (GPLv2) for more details.
  68 + *
  69 + * You should have received a copy of the GNU General Public License
  70 + * version 2 (GPLv2) along with this source code.
  71 + */
  72 +
  73 +#include <linux/clk.h>
  74 +#include <linux/delay.h>
  75 +#include <linux/device.h>
  76 +#include <linux/init.h>
  77 +#include <linux/interrupt.h>
  78 +#include <linux/io.h>
  79 +#include <linux/ioport.h>
  80 +#include <linux/kernel.h>
  81 +#include <linux/module.h>
  82 +#include <linux/mtd/cfi.h>
  83 +#include <linux/mtd/spi-nor.h>
  84 +#include <linux/of.h>
  85 +#include <linux/of_irq.h>
  86 +#include <linux/platform_device.h>
  87 +#include <linux/slab.h>
  88 +#include <linux/spi/spi.h>
  89 +#include <linux/sysfs.h>
  90 +#include <linux/types.h>
  91 +#include "spi-bcm-qspi.h"
  92 +
  93 +#define DRIVER_NAME "bcm_qspi"
  94 +
  95 +/* MSPI register offsets */
  96 +#define MSPI_SPCR0_LSB                         0x000
  97 +#define MSPI_SPCR0_MSB                         0x004
  98 +#define MSPI_SPCR1_LSB                         0x008
  99 +#define MSPI_SPCR1_MSB                         0x00c
 100 +#define MSPI_NEWQP                             0x010
 101 +#define MSPI_ENDQP                             0x014
 102 +#define MSPI_SPCR2                             0x018
 103 +#define MSPI_MSPI_STATUS                       0x020
 104 +#define MSPI_CPTQP                             0x024
 105 +#define MSPI_SPCR3                             0x028
 106 +#define MSPI_TXRAM                             0x040
 107 +#define MSPI_RXRAM                             0x0c0
 108 +#define MSPI_CDRAM                             0x140
 109 +#define MSPI_WRITE_LOCK                        0x180
 110 +
 111 +#define MSPI_MASTER_BIT                        BIT(7)
 112 +
 113 +#define MSPI_NUM_CDRAM                         16
 114 +#define MSPI_CDRAM_CONT_BIT                    BIT(7)
 115 +#define MSPI_CDRAM_BITSE_BIT                   BIT(6)
 116 +#define MSPI_CDRAM_PCS                         0xf
 117 +
 118 +#define MSPI_SPCR2_SPE                         BIT(6)
 119 +#define MSPI_SPCR2_CONT_AFTER_CMD              BIT(7)
 120 +
 121 +#define MSPI_MSPI_STATUS_SPIF                  BIT(0)
 122 +
 123 +#define INTR_BASE_BIT_SHIFT                    0x02
 124 +#define INTR_COUNT                             0x07
 125 +
 126 +#define NUM_CHIPSELECT                         4
 127 +#define QSPI_SPBR_MIN                          8U
 128 +#define QSPI_SPBR_MAX                          255U
 129 +
 130 +#define OPCODE_DIOR                            0xBB
 131 +#define OPCODE_QIOR                            0xEB
 132 +#define OPCODE_DIOR_4B                         0xBC
 133 +#define OPCODE_QIOR_4B                         0xEC
 134 +
 135 +#define MAX_CMD_SIZE                           6
 136 +
 137 +#define ADDR_4MB_MASK                          GENMASK(22, 0)
 138 +
 139 +/* stop at end of transfer, no other reason */
 140 +#define TRANS_STATUS_BREAK_NONE                0
 141 +/* stop at end of spi_message */
 142 +#define TRANS_STATUS_BREAK_EOM                 1
 143 +/* stop at end of spi_transfer if delay */
 144 +#define TRANS_STATUS_BREAK_DELAY               2
 145 +/* stop at end of spi_transfer if cs_change */
 146 +#define TRANS_STATUS_BREAK_CS_CHANGE           4
 147 +/* stop if we run out of bytes */
 148 +#define TRANS_STATUS_BREAK_NO_BYTES            8
 149 +
 150 +/* events that make us stop filling TX slots */
 151 +#define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM |                \
 152 +                              TRANS_STATUS_BREAK_DELAY |               \
 153 +                              TRANS_STATUS_BREAK_CS_CHANGE)
 154 +
 155 +/* events that make us deassert CS */
 156 +#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM |          \
 157 +                                    TRANS_STATUS_BREAK_CS_CHANGE)
 158 +
 159 +struct bcm_qspi_parms {
 160 +       u32 speed_hz;
 161 +       u8 mode;
 162 +       u8 bits_per_word;
 163 +};
 164 +
 165 +enum base_type {
 166 +       MSPI,
 167 +       CHIP_SELECT,
 168 +       BASEMAX,
 169 +};
 170 +
 171 +struct bcm_qspi_irq {
 172 +       const char *irq_name;
 173 +       const irq_handler_t irq_handler;
 174 +       u32 mask;
 175 +};
 176 +
 177 +struct bcm_qspi_dev_id {
 178 +       const struct bcm_qspi_irq *irqp;
 179 +       void *dev;
 180 +};
 181 +
 182 +struct qspi_trans {
 183 +       struct spi_transfer *trans;
 184 +       int byte;
 185 +};
 186 +
 187 +struct bcm_qspi {
 188 +       struct platform_device *pdev;
 189 +       struct spi_master *master;
 190 +       struct clk *clk;
 191 +       u32 base_clk;
 192 +       u32 max_speed_hz;
 193 +       void __iomem *base[BASEMAX];
 194 +       struct bcm_qspi_parms last_parms;
 195 +       struct qspi_trans  trans_pos;
 196 +       int curr_cs;
 197 +       u32 s3_strap_override_ctrl;
 198 +       bool big_endian;
 199 +       int num_irqs;
 200 +       struct bcm_qspi_dev_id *dev_ids;
 201 +       struct completion mspi_done;
 202 +};
 203 +
 204 +/* Read qspi controller register*/
 205 +static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
 206 +                               unsigned int offset)
 207 +{
 208 +       return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
 209 +}
 210 +
 211 +/* Write qspi controller register*/
 212 +static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
 213 +                                 unsigned int offset, unsigned int data)
 214 +{
 215 +       bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
 216 +}
 217 +
 218 +static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
 219 +{
 220 +       u32 data = 0;
 221 +
 222 +       if (qspi->curr_cs == cs)
 223 +               return;
 224 +       if (qspi->base[CHIP_SELECT]) {
 225 +               data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
 226 +               data = (data & ~0xff) | (1 << cs);
 227 +               bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
 228 +               usleep_range(10, 20);
 229 +       }
 230 +       qspi->curr_cs = cs;
 231 +}
 232 +
 233 +/* MSPI helpers */
 234 +static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 235 +                                 const struct bcm_qspi_parms *xp)
 236 +{
 237 +       u32 spcr, spbr = 0;
 238 +
 239 +       if (xp->speed_hz)
 240 +               spbr = qspi->base_clk / (2 * xp->speed_hz);
 241 +
 242 +       spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
 243 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 244 +
 245 +       spcr = MSPI_MASTER_BIT;
 246 +       /* for 16 bit the data should be zero */
 247 +       if (xp->bits_per_word != 16)
 248 +               spcr |= xp->bits_per_word << 2;
 249 +       spcr |= xp->mode & 3;
 250 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 251 +
 252 +       qspi->last_parms = *xp;
 253 +}
 254 +
 255 +static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
 256 +                                 struct spi_device *spi,
 257 +                                 struct spi_transfer *trans)
 258 +{
 259 +       struct bcm_qspi_parms xp;
 260 +
 261 +       xp.speed_hz = trans->speed_hz;
 262 +       xp.bits_per_word = trans->bits_per_word;
 263 +       xp.mode = spi->mode;
 264 +
 265 +       bcm_qspi_hw_set_parms(qspi, &xp);
 266 +}
 267 +
 268 +static int bcm_qspi_setup(struct spi_device *spi)
 269 +{
 270 +       struct bcm_qspi_parms *xp;
 271 +
 272 +       if (spi->bits_per_word > 16)
 273 +               return -EINVAL;
 274 +
 275 +       xp = spi_get_ctldata(spi);
 276 +       if (!xp) {
 277 +               xp = kzalloc(sizeof(*xp), GFP_KERNEL);
 278 +               if (!xp)
 279 +                       return -ENOMEM;
 280 +               spi_set_ctldata(spi, xp);
 281 +       }
 282 +       xp->speed_hz = spi->max_speed_hz;
 283 +       xp->mode = spi->mode;
 284 +
 285 +       if (spi->bits_per_word)
 286 +               xp->bits_per_word = spi->bits_per_word;
 287 +       else
 288 +               xp->bits_per_word = 8;
 289 +
 290 +       return 0;
 291 +}
 292 +
 293 +static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
 294 +                                       struct qspi_trans *qt, int flags)
 295 +{
 296 +       int ret = TRANS_STATUS_BREAK_NONE;
 297 +
 298 +       /* count the last transferred bytes */
 299 +       if (qt->trans->bits_per_word <= 8)
 300 +               qt->byte++;
 301 +       else
 302 +               qt->byte += 2;
 303 +
 304 +       if (qt->byte >= qt->trans->len) {
 305 +               /* we're at the end of the spi_transfer */
 306 +
 307 +               /* in TX mode, need to pause for a delay or CS change */
 308 +               if (qt->trans->delay_usecs &&
 309 +                   (flags & TRANS_STATUS_BREAK_DELAY))
 310 +                       ret |= TRANS_STATUS_BREAK_DELAY;
 311 +               if (qt->trans->cs_change &&
 312 +                   (flags & TRANS_STATUS_BREAK_CS_CHANGE))
 313 +                       ret |= TRANS_STATUS_BREAK_CS_CHANGE;
 314 +               if (ret)
 315 +                       goto done;
 316 +
 317 +               dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
 318 +               if (spi_transfer_is_last(qspi->master, qt->trans))
 319 +                       ret = TRANS_STATUS_BREAK_EOM;
 320 +               else
 321 +                       ret = TRANS_STATUS_BREAK_NO_BYTES;
 322 +
 323 +               qt->trans = NULL;
 324 +       }
 325 +
 326 +done:
 327 +       dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
 328 +               qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
 329 +       return ret;
 330 +}
 331 +
 332 +static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
 333 +{
 334 +       u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
 335 +
 336 +       /* mask out reserved bits */
 337 +       return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
 338 +}
 339 +
 340 +static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
 341 +{
 342 +       u32 reg_offset = MSPI_RXRAM;
 343 +       u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 344 +       u32 msb_offset = reg_offset + (slot << 3);
 345 +
 346 +       return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
 347 +               ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
 348 +}
 349 +
 350 +static void read_from_hw(struct bcm_qspi *qspi, int slots)
 351 +{
 352 +       struct qspi_trans tp;
 353 +       int slot;
 354 +
 355 +       if (slots > MSPI_NUM_CDRAM) {
 356 +               /* should never happen */
 357 +               dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
 358 +               return;
 359 +       }
 360 +
 361 +       tp = qspi->trans_pos;
 362 +
 363 +       for (slot = 0; slot < slots; slot++) {
 364 +               if (tp.trans->bits_per_word <= 8) {
 365 +                       u8 *buf = tp.trans->rx_buf;
 366 +
 367 +                       if (buf)
 368 +                               buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
 369 +                       dev_dbg(&qspi->pdev->dev, "RD %02x\n",
 370 +                               buf ? buf[tp.byte] : 0xff);
 371 +               } else {
 372 +                       u16 *buf = tp.trans->rx_buf;
 373 +
 374 +                       if (buf)
 375 +                               buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
 376 +                                                                     slot);
 377 +                       dev_dbg(&qspi->pdev->dev, "RD %04x\n",
 378 +                               buf ? buf[tp.byte] : 0xffff);
 379 +               }
 380 +
 381 +               update_qspi_trans_byte_count(qspi, &tp,
 382 +                                            TRANS_STATUS_BREAK_NONE);
 383 +       }
 384 +
 385 +       qspi->trans_pos = tp;
 386 +}
 387 +
 388 +static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
 389 +                                      u8 val)
 390 +{
 391 +       u32 reg_offset = MSPI_TXRAM + (slot << 3);
 392 +
 393 +       /* mask out reserved bits */
 394 +       bcm_qspi_write(qspi, MSPI, reg_offset, val);
 395 +}
 396 +
 397 +static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
 398 +                                       u16 val)
 399 +{
 400 +       u32 reg_offset = MSPI_TXRAM;
 401 +       u32 msb_offset = reg_offset + (slot << 3);
 402 +       u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 403 +
 404 +       bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
 405 +       bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
 406 +}
 407 +
 408 +static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
 409 +{
 410 +       return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
 411 +}
 412 +
 413 +static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
 414 +{
 415 +       bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
 416 +}
 417 +
 418 +/* Return number of slots written */
 419 +static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 420 +{
 421 +       struct qspi_trans tp;
 422 +       int slot = 0, tstatus = 0;
 423 +       u32 mspi_cdram = 0;
 424 +
 425 +       tp = qspi->trans_pos;
 426 +       bcm_qspi_update_parms(qspi, spi, tp.trans);
 427 +
 428 +       /* Run until end of transfer or reached the max data */
 429 +       while (!tstatus && slot < MSPI_NUM_CDRAM) {
 430 +               if (tp.trans->bits_per_word <= 8) {
 431 +                       const u8 *buf = tp.trans->tx_buf;
 432 +                       u8 val = buf ? buf[tp.byte] : 0xff;
 433 +
 434 +                       write_txram_slot_u8(qspi, slot, val);
 435 +                       dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
 436 +               } else {
 437 +                       const u16 *buf = tp.trans->tx_buf;
 438 +                       u16 val = buf ? buf[tp.byte / 2] : 0xffff;
 439 +
 440 +                       write_txram_slot_u16(qspi, slot, val);
 441 +                       dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
 442 +               }
 443 +               mspi_cdram = MSPI_CDRAM_CONT_BIT;
 444 +               mspi_cdram |= (~(1 << spi->chip_select) &
 445 +                              MSPI_CDRAM_PCS);
 446 +               mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
 447 +                               MSPI_CDRAM_BITSE_BIT);
 448 +
 449 +               write_cdram_slot(qspi, slot, mspi_cdram);
 450 +
 451 +               tstatus = update_qspi_trans_byte_count(qspi, &tp,
 452 +                                                      TRANS_STATUS_BREAK_TX);
 453 +               slot++;
 454 +       }
 455 +
 456 +       if (!slot) {
 457 +               dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
 458 +               goto done;
 459 +       }
 460 +
 461 +       dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
 462 +       bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
 463 +       bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
 464 +
 465 +       if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
 466 +               mspi_cdram = read_cdram_slot(qspi, slot - 1) &
 467 +                       ~MSPI_CDRAM_CONT_BIT;
 468 +               write_cdram_slot(qspi, slot - 1, mspi_cdram);
 469 +       }
 470 +
 471 +       /* Must flush previous writes before starting MSPI operation */
 472 +       mb();
 473 +       /* Set cont | spe | spifie */
 474 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
 475 +
 476 +done:
 477 +       return slot;
 478 +}
 479 +
 480 +static int bcm_qspi_transfer_one(struct spi_master *master,
 481 +                                struct spi_device *spi,
 482 +                                struct spi_transfer *trans)
 483 +{
 484 +       struct bcm_qspi *qspi = spi_master_get_devdata(master);
 485 +       int slots;
 486 +       unsigned long timeo = msecs_to_jiffies(100);
 487 +
 488 +       bcm_qspi_chip_select(qspi, spi->chip_select);
 489 +       qspi->trans_pos.trans = trans;
 490 +       qspi->trans_pos.byte = 0;
 491 +
 492 +       while (qspi->trans_pos.byte < trans->len) {
 493 +               reinit_completion(&qspi->mspi_done);
 494 +
 495 +               slots = write_to_hw(qspi, spi);
 496 +               if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
 497 +                       dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
 498 +                       return -ETIMEDOUT;
 499 +               }
 500 +
 501 +               read_from_hw(qspi, slots);
 502 +       }
 503 +
 504 +       return 0;
 505 +}
 506 +
 507 +static void bcm_qspi_cleanup(struct spi_device *spi)
 508 +{
 509 +       struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
 510 +
 511 +       kfree(xp);
 512 +}
 513 +
 514 +static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
 515 +{
 516 +       struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
 517 +       struct bcm_qspi *qspi = qspi_dev_id->dev;
 518 +       u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
 519 +
 520 +       if (status & MSPI_MSPI_STATUS_SPIF) {
 521 +               /* clear interrupt */
 522 +               status &= ~MSPI_MSPI_STATUS_SPIF;
 523 +               bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
 524 +               complete(&qspi->mspi_done);
 525 +               return IRQ_HANDLED;
 526 +       } else {
 527 +               return IRQ_NONE;
 528 +       }
 529 +}
 530 +
 531 +static const struct bcm_qspi_irq qspi_irq_tab[] = {
 532 +       {
 533 +               .irq_name = "mspi_done",
 534 +               .irq_handler = bcm_qspi_mspi_l2_isr,
 535 +               .mask = INTR_MSPI_DONE_MASK,
 536 +       },
 537 +       {
 538 +               .irq_name = "mspi_halted",
 539 +               .irq_handler = bcm_qspi_mspi_l2_isr,
 540 +               .mask = INTR_MSPI_HALTED_MASK,
 541 +       },
 542 +};
 543 +
 544 +static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
 545 +{
 546 +       struct bcm_qspi_parms parms;
 547 +
 548 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
 549 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
 550 +       bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
 551 +       bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
 552 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
 553 +
 554 +       parms.mode = SPI_MODE_3;
 555 +       parms.bits_per_word = 8;
 556 +       parms.speed_hz = qspi->max_speed_hz;
 557 +       bcm_qspi_hw_set_parms(qspi, &parms);
 558 +}
 559 +
 560 +static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
 561 +{
 562 +       bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
 563 +}
 564 +
 565 +static const struct of_device_id bcm_qspi_of_match[] = {
 566 +       { .compatible = "brcm,spi-bcm-qspi" },
 567 +       {},
 568 +};
 569 +MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
 570 +
 571 +int bcm_qspi_probe(struct platform_device *pdev,
 572 +                  struct bcm_qspi_soc_intc *soc)
 573 +{
 574 +       struct device *dev = &pdev->dev;
 575 +       struct bcm_qspi *qspi;
 576 +       struct spi_master *master;
 577 +       struct resource *res;
 578 +       int irq, ret = 0, num_ints = 0;
 579 +       u32 val;
 580 +       const char *name = NULL;
 581 +       int num_irqs = ARRAY_SIZE(qspi_irq_tab);
 582 +
 583 +       /* We only support device-tree instantiation */
 584 +       if (!dev->of_node)
 585 +               return -ENODEV;
 586 +
 587 +       if (!of_match_node(bcm_qspi_of_match, dev->of_node))
 588 +               return -ENODEV;
 589 +
 590 +       master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
 591 +       if (!master) {
 592 +               dev_err(dev, "error allocating spi_master\n");
 593 +               return -ENOMEM;
 594 +       }
 595 +
 596 +       qspi = spi_master_get_devdata(master);
 597 +       qspi->pdev = pdev;
 598 +       qspi->trans_pos.trans = NULL;
 599 +       qspi->trans_pos.byte = 0;
 600 +       qspi->master = master;
 601 +
 602 +       master->bus_num = -1;
 603 +       master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
 604 +       master->setup = bcm_qspi_setup;
 605 +       master->transfer_one = bcm_qspi_transfer_one;
 606 +       master->cleanup = bcm_qspi_cleanup;
 607 +       master->dev.of_node = dev->of_node;
 608 +       master->num_chipselect = NUM_CHIPSELECT;
 609 +
 610 +       qspi->big_endian = of_device_is_big_endian(dev->of_node);
 611 +
 612 +       if (!of_property_read_u32(dev->of_node, "num-cs", &val))
 613 +               master->num_chipselect = val;
 614 +
 615 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
 616 +       if (!res)
 617 +               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 618 +                                                  "mspi");
 619 +
 620 +       if (res) {
 621 +               qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
 622 +               if (IS_ERR(qspi->base[MSPI])) {
 623 +                       ret = PTR_ERR(qspi->base[MSPI]);
 624 +                       goto qspi_probe_err;
 625 +               }
 626 +       } else {
 627 +               goto qspi_probe_err;
 628 +       }
 629 +
 630 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
 631 +       if (res) {
 632 +               qspi->base[CHIP_SELECT]  = devm_ioremap_resource(dev, res);
 633 +               if (IS_ERR(qspi->base[CHIP_SELECT])) {
 634 +                       ret = PTR_ERR(qspi->base[CHIP_SELECT]);
 635 +                       goto qspi_probe_err;
 636 +               }
 637 +       }
 638 +
 639 +       qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
 640 +                               GFP_KERNEL);
 641 +       if (IS_ERR(qspi->dev_ids)) {
 642 +               ret = PTR_ERR(qspi->dev_ids);
 643 +               goto qspi_probe_err;
 644 +       }
 645 +
 646 +       for (val = 0; val < num_irqs; val++) {
 647 +               irq = -1;
 648 +               name = qspi_irq_tab[val].irq_name;
 649 +               irq = platform_get_irq_byname(pdev, name);
 650 +
 651 +               if (irq  >= 0) {
 652 +                       ret = devm_request_irq(&pdev->dev, irq,
 653 +                                              qspi_irq_tab[val].irq_handler, 0,
 654 +                                              name,
 655 +                                              &qspi->dev_ids[val]);
 656 +                       if (ret < 0) {
 657 +                               dev_err(&pdev->dev, "IRQ %s not found\n", name);
 658 +                               goto qspi_probe_err;
 659 +                       }
 660 +
 661 +                       qspi->dev_ids[val].dev = qspi;
 662 +                       qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
 663 +                       num_ints++;
 664 +                       dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
 665 +                               qspi_irq_tab[val].irq_name,
 666 +                               irq);
 667 +               }
 668 +       }
 669 +
 670 +       if (!num_ints) {
 671 +               dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
 672 +               goto qspi_probe_err;
 673 +       }
 674 +
 675 +       qspi->clk = devm_clk_get(&pdev->dev, NULL);
 676 +       if (IS_ERR(qspi->clk)) {
 677 +               dev_warn(dev, "unable to get clock\n");
 678 +               goto qspi_probe_err;
 679 +       }
 680 +
 681 +       ret = clk_prepare_enable(qspi->clk);
 682 +       if (ret) {
 683 +               dev_err(dev, "failed to prepare clock\n");
 684 +               goto qspi_probe_err;
 685 +       }
 686 +
 687 +       qspi->base_clk = clk_get_rate(qspi->clk);
 688 +       qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
 689 +
 690 +       bcm_qspi_hw_init(qspi);
 691 +       init_completion(&qspi->mspi_done);
 692 +       qspi->curr_cs = -1;
 693 +
 694 +       platform_set_drvdata(pdev, qspi);
 695 +       ret = devm_spi_register_master(&pdev->dev, master);
 696 +       if (ret < 0) {
 697 +               dev_err(dev, "can't register master\n");
 698 +               goto qspi_reg_err;
 699 +       }
 700 +
 701 +       return 0;
 702 +
 703 +qspi_reg_err:
 704 +       bcm_qspi_hw_uninit(qspi);
 705 +       clk_disable_unprepare(qspi->clk);
 706 +qspi_probe_err:
 707 +       spi_master_put(master);
 708 +       kfree(qspi->dev_ids);
 709 +       return ret;
 710 +}
 711 +/* probe function to be called by SoC specific platform driver probe */
 712 +EXPORT_SYMBOL_GPL(bcm_qspi_probe);
 713 +
 714 +int bcm_qspi_remove(struct platform_device *pdev)
 715 +{
 716 +       struct bcm_qspi *qspi = platform_get_drvdata(pdev);
 717 +
 718 +       platform_set_drvdata(pdev, NULL);
 719 +       bcm_qspi_hw_uninit(qspi);
 720 +       clk_disable_unprepare(qspi->clk);
 721 +       kfree(qspi->dev_ids);
 722 +       spi_unregister_master(qspi->master);
 723 +
 724 +       return 0;
 725 +}
 726 +/* function to be called by SoC specific platform driver remove() */
 727 +EXPORT_SYMBOL_GPL(bcm_qspi_remove);
 728 +
 729 +#ifdef CONFIG_PM_SLEEP
 730 +static int bcm_qspi_suspend(struct device *dev)
 731 +{
 732 +       struct bcm_qspi *qspi = dev_get_drvdata(dev);
 733 +
 734 +       spi_master_suspend(qspi->master);
 735 +       clk_disable(qspi->clk);
 736 +       bcm_qspi_hw_uninit(qspi);
 737 +
 738 +       return 0;
 739 +};
 740 +
 741 +static int bcm_qspi_resume(struct device *dev)
 742 +{
 743 +       struct bcm_qspi *qspi = dev_get_drvdata(dev);
 744 +       int ret = 0;
 745 +
 746 +       bcm_qspi_hw_init(qspi);
 747 +       bcm_qspi_chip_select(qspi, qspi->curr_cs);
 748 +       ret = clk_enable(qspi->clk);
 749 +       if (!ret)
 750 +               spi_master_resume(qspi->master);
 751 +
 752 +       return ret;
 753 +}
 754 +#endif /* CONFIG_PM_SLEEP */
 755 +
 756 +const struct dev_pm_ops bcm_qspi_pm_ops = {
 757 +       .suspend = bcm_qspi_suspend,
 758 +       .resume  = bcm_qspi_resume,
 759 +};
 760 +/* pm_ops to be called by SoC specific platform driver */
 761 +EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
 762 +
 763 +MODULE_AUTHOR("Kamal Dasu");
 764 +MODULE_DESCRIPTION("Broadcom QSPI driver");
 765 +MODULE_LICENSE("GPL v2");
 766 +MODULE_ALIAS("platform:" DRIVER_NAME);
 767 --- /dev/null
 768 +++ b/drivers/spi/spi-bcm-qspi.h
 769 @@ -0,0 +1,63 @@
 770 +/*
 771 + * Copyright 2016 Broadcom
 772 + *
 773 + * This program is free software; you can redistribute it and/or modify
 774 + * it under the terms of the GNU General Public License, version 2, as
 775 + * published by the Free Software Foundation (the "GPL").
 776 + *
 777 + * This program is distributed in the hope that it will be useful, but
 778 + * WITHOUT ANY WARRANTY; without even the implied warranty of
 779 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 780 + * General Public License version 2 (GPLv2) for more details.
 781 + *
 782 + * You should have received a copy of the GNU General Public License
 783 + * version 2 (GPLv2) along with this source code.
 784 + */
 785 +
 786 +#ifndef __SPI_BCM_QSPI_H__
 787 +#define __SPI_BCM_QSPI_H__
 788 +
 789 +#include <linux/types.h>
 790 +#include <linux/io.h>
 791 +
 792 +/* MSPI Interrupt masks */
 793 +#define INTR_MSPI_HALTED_MASK                  BIT(6)
 794 +#define INTR_MSPI_DONE_MASK                    BIT(5)
 795 +
 796 +#define MSPI_INTERRUPTS_ALL                   \
 797 +       (INTR_MSPI_DONE_MASK |                 \
 798 +        INTR_MSPI_HALTED_MASK)
 799 +
 800 +struct platform_device;
 801 +struct dev_pm_ops;
 802 +
 803 +struct bcm_qspi_soc_intc;
 804 +
 805 +/* Read controller register*/
 806 +static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
 807 +{
 808 +       if (be)
 809 +               return ioread32be(addr);
 810 +       else
 811 +               return readl_relaxed(addr);
 812 +}
 813 +
 814 +/* Write controller register*/
 815 +static inline void bcm_qspi_writel(bool be,
 816 +                                  unsigned int data, void __iomem *addr)
 817 +{
 818 +       if (be)
 819 +               iowrite32be(data, addr);
 820 +       else
 821 +               writel_relaxed(data, addr);
 822 +}
 823 +
 824 +/* The common driver functions to be called by the SoC platform driver */
 825 +int bcm_qspi_probe(struct platform_device *pdev,
 826 +                  struct bcm_qspi_soc_intc *soc_intc);
 827 +int bcm_qspi_remove(struct platform_device *pdev);
 828 +
 829 +/* pm_ops used by the SoC platform driver called on PM suspend/resume */
 830 +extern const struct dev_pm_ops bcm_qspi_pm_ops;
 831 +
 832 +#endif /* __SPI_BCM_QSPI_H__ */