target/linux/brcm2708/patches-4.4/0485-Overlay-for-Microchip-MCP23S08-17-SPI-gpio-expanders.patch

   1 From 7312a1a17fcfd2ae587be671f895b23c8973e9ad Mon Sep 17 00:00:00 2001
   2 From: wavelet2 <a3d35232@btinternet.com>
   3 Date: Fri, 19 Aug 2016 09:32:53 +0100
   4 Subject: [PATCH] Overlay for Microchip MCP23S08/17 SPI gpio expanders  (#1566)
   5
   6 Added Overlay for Microchip MCP23S08/17 SPI gpio expanders
   7 ---
   8  arch/arm/boot/dts/overlays/Makefile             |   1 +
   9  arch/arm/boot/dts/overlays/README               |  24 +
  10  arch/arm/boot/dts/overlays/mcp23s17-overlay.dts | 732 ++++++++++++++++++++++++
  11  3 files changed, 757 insertions(+)
  12  create mode 100644 arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
  13
  14 --- a/arch/arm/boot/dts/overlays/Makefile
  15 +++ b/arch/arm/boot/dts/overlays/Makefile
  16 @@ -49,6 +49,7 @@ dtbo-$(RPI_DT_OVERLAYS) += justboom-dac.
  17  dtbo-$(RPI_DT_OVERLAYS) += justboom-digi.dtbo
  18  dtbo-$(RPI_DT_OVERLAYS) += lirc-rpi.dtbo
  19  dtbo-$(RPI_DT_OVERLAYS) += mcp23017.dtbo
  20 +dtbo-$(RPI_DT_OVERLAYS) += mcp23s17.dtbo
  21  dtbo-$(RPI_DT_OVERLAYS) += mcp2515-can0.dtbo
  22  dtbo-$(RPI_DT_OVERLAYS) += mcp2515-can1.dtbo
  23  dtbo-$(RPI_DT_OVERLAYS) += mmc.dtbo
  24 --- a/arch/arm/boot/dts/overlays/README
  25 +++ b/arch/arm/boot/dts/overlays/README
  26 @@ -628,6 +628,30 @@ Params: gpiopin                 Gpio pin
  27          addr                    I2C address of the MCP23017 (default: 0x20)
  28
  29
  30 +Name:   mcp23s17
  31 +Info:   Configures the MCP23S08/17 SPI GPIO expanders.
  32 +        If devices are present on SPI1 or SPI2, those interfaces must be enabled
  33 +        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
  34 +        If interrupts are enabled for a device on a given CS# on a SPI bus, that
  35 +        device must be the only one present on that SPI bus/CS#.
  36 +Load:   dtoverlay=mcp23s17,<param>=<val>
  37 +Params: s08-spi<n>-<m>-present  4-bit integer, bitmap indicating MCP23S08
  38 +                                devices present on SPI<n>, CS#<m>
  39 +
  40 +        s17-spi<n>-<m>-present  8-bit integer, bitmap indicating MCP23S17
  41 +                                devices present on SPI<n>, CS#<m>
  42 +
  43 +        s08-spi<n>-<m>-int-gpio integer, enables interrupts on a single
  44 +                                MCP23S08 device on SPI<n>, CS#<m>, specifies
  45 +                                the GPIO pin to which INT output of MCP23S08
  46 +                                is connected.
  47 +
  48 +        s17-spi<n>-<m>-int-gpio integer, enables mirrored interrupts on a
  49 +                                single MCP23S17 device on SPI<n>, CS#<m>,
  50 +                                specifies the GPIO pin to which either INTA
  51 +                                or INTB output of MCP23S17 is connected.
  52 +
  53 +
  54  Name:   mcp2515-can0
  55  Info:   Configures the MCP2515 CAN controller on spi0.0
  56  Load:   dtoverlay=mcp2515-can0,<param>=<val>
  57 --- /dev/null
  58 +++ b/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
  59 @@ -0,0 +1,732 @@
  60 +// Overlay for MCP23S08/17 GPIO Extenders from Microchip Semiconductor
  61 +
  62 +// dtparams:
  63 +//     s08-spi<n>-<m>-present  - 4-bit integer, bitmap indicating MCP23S08 devices present on SPI<n>, CS#<m>.
  64 +//     s17-spi<n>-<m>-present  - 8-bit integer, bitmap indicating MCP23S17 devices present on SPI<n>, CS#<m>.
  65 +//     s08-spi<n>-<m>-int-gpio - integer, enables interrupts on a single MCP23S08 device on SPI<n>, CS#<m>, specifies the GPIO pin to which INT output is connected.
  66 +//     s17-spi<n>-<m>-int-gpio - integer, enables mirrored interrupts on a single MCP23S17 device on SPI<n>, CS#<m>, specifies the GPIO pin to which either INTA or INTB output is connected.
  67 +//
  68 +// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
  69 +// If interrupts are enabled for a device on a given CS# on a SPI bus, that device must be the only one present on that SPI bus/CS#.
  70 +//
  71 +// Example 1: A single MCP23S17 device on SPI0, CS#0 with its SPI addr set to 0 and INTA output connected to GPIO25:
  72 +// dtoverlay=mcp23s17:s17-spi0-0-present=1,s17-spi0-0-int-gpio=25
  73 +//
  74 +// Example 2: Two MCP23S08 devices on SPI1, CS#0 with their addrs set to 2 and 3. Three MCP23S17 devices on SPI1, CS#1 with their addrs set to 0, 1 and 7:
  75 +// dtoverlay=spi1-2cs
  76 +// dtoverlay=mcp23s17:s08-spi1-0-present=12,s17-spi1-1-present=131
  77 +
  78 +/dts-v1/;
  79 +/plugin/;
  80 +
  81 +/ {
  82 +       compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
  83 +
  84 +       // disable spi-dev on spi0.0
  85 +       fragment@0 {
  86 +               target = <&spidev0>;
  87 +               __dormant__ {
  88 +                       status = "disabled";
  89 +               };
  90 +       };
  91 +
  92 +       // disable spi-dev on spi0.1
  93 +       fragment@1 {
  94 +               target = <&spidev1>;
  95 +               __dormant__ {
  96 +                       status = "disabled";
  97 +               };
  98 +       };
  99 +
 100 +       // disable spi-dev on spi1.0
 101 +       fragment@2 {
 102 +               target-path = "spi1/spidev@0";
 103 +               __dormant__ {
 104 +                       status = "disabled";
 105 +               };
 106 +       };
 107 +
 108 +       // disable spi-dev on spi1.1
 109 +       fragment@3 {
 110 +               target-path = "spi1/spidev@1";
 111 +               __dormant__ {
 112 +                       status = "disabled";
 113 +               };
 114 +       };
 115 +
 116 +       // disable spi-dev on spi1.2
 117 +       fragment@4 {
 118 +               target-path = "spi1/spidev@2";
 119 +               __dormant__ {
 120 +                       status = "disabled";
 121 +               };
 122 +       };
 123 +
 124 +       // disable spi-dev on spi2.0
 125 +       fragment@5 {
 126 +               target-path = "spi2/spidev@0";
 127 +               __dormant__ {
 128 +                       status = "disabled";
 129 +               };
 130 +       };
 131 +
 132 +       // disable spi-dev on spi2.1
 133 +       fragment@6 {
 134 +               target-path = "spi2/spidev@1";
 135 +               __dormant__ {
 136 +                       status = "disabled";
 137 +               };
 138 +       };
 139 +
 140 +       // disable spi-dev on spi2.2
 141 +       fragment@7 {
 142 +               target-path = "spi2/spidev@2";
 143 +               __dormant__ {
 144 +                       status = "disabled";
 145 +               };
 146 +       };
 147 +
 148 +       // enable one or more mcp23s08s on spi0.0
 149 +       fragment@8 {
 150 +               target = <&spi0>;
 151 +               __dormant__ {
 152 +                       status = "okay";
 153 +                        #address-cells = <1>;
 154 +                        #size-cells = <0>;
 155 +                       mcp23s08_00: mcp23s08@0 {
 156 +                               compatible = "microchip,mcp23s08";
 157 +                               gpio-controller;
 158 +                               #gpio-cells = <2>;
 159 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-0-present parameter */
 160 +                               reg = <0>;
 161 +                               spi-max-frequency = <500000>;
 162 +                               status = "okay";
 163 +                               #interrupt-cells=<2>;
 164 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-0-int-gpio parameter */
 165 +                       };
 166 +               };
 167 +       };
 168 +
 169 +       // enable one or more mcp23s08s on spi0.1
 170 +       fragment@9 {
 171 +               target = <&spi0>;
 172 +               __dormant__ {
 173 +                       status = "okay";
 174 +                        #address-cells = <1>;
 175 +                        #size-cells = <0>;
 176 +                       mcp23s08_01: mcp23s08@1 {
 177 +                               compatible = "microchip,mcp23s08";
 178 +                               gpio-controller;
 179 +                               #gpio-cells = <2>;
 180 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-1-present parameter */
 181 +                               reg = <1>;
 182 +                               spi-max-frequency = <500000>;
 183 +                               status = "okay";
 184 +                               #interrupt-cells=<2>;
 185 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-1-int-gpio parameter */
 186 +                       };
 187 +               };
 188 +       };
 189 +
 190 +       // enable one or more mcp23s08s on spi1.0
 191 +       fragment@10 {
 192 +               target = <&spi1>;
 193 +               __dormant__ {
 194 +                       status = "okay";
 195 +                        #address-cells = <1>;
 196 +                        #size-cells = <0>;
 197 +                       mcp23s08_10: mcp23s08@0 {
 198 +                               compatible = "microchip,mcp23s08";
 199 +                               gpio-controller;
 200 +                               #gpio-cells = <2>;
 201 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-0-present parameter */
 202 +                               reg = <0>;
 203 +                               spi-max-frequency = <500000>;
 204 +                               status = "okay";
 205 +                               #interrupt-cells=<2>;
 206 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-0-int-gpio parameter */
 207 +                       };
 208 +               };
 209 +       };
 210 +
 211 +       // enable one or more mcp23s08s on spi1.1
 212 +       fragment@11 {
 213 +               target = <&spi1>;
 214 +               __dormant__ {
 215 +                       status = "okay";
 216 +                        #address-cells = <1>;
 217 +                        #size-cells = <0>;
 218 +                       mcp23s08_11: mcp23s08@1 {
 219 +                               compatible = "microchip,mcp23s08";
 220 +                               gpio-controller;
 221 +                               #gpio-cells = <2>;
 222 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-1-present parameter */
 223 +                               reg = <1>;
 224 +                               spi-max-frequency = <500000>;
 225 +                               status = "okay";
 226 +                               #interrupt-cells=<2>;
 227 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-1-int-gpio parameter */
 228 +                       };
 229 +               };
 230 +       };
 231 +
 232 +       // enable one or more mcp23s08s on spi1.2
 233 +       fragment@12 {
 234 +               target = <&spi1>;
 235 +               __dormant__ {
 236 +                       status = "okay";
 237 +                        #address-cells = <1>;
 238 +                        #size-cells = <0>;
 239 +                       mcp23s08_12: mcp23s08@2 {
 240 +                               compatible = "microchip,mcp23s08";
 241 +                               gpio-controller;
 242 +                               #gpio-cells = <2>;
 243 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-2-present parameter */
 244 +                               reg = <2>;
 245 +                               spi-max-frequency = <500000>;
 246 +                               status = "okay";
 247 +                               #interrupt-cells=<2>;
 248 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-2-int-gpio parameter */
 249 +                       };
 250 +               };
 251 +       };
 252 +
 253 +       // enable one or more mcp23s08s on spi2.0
 254 +       fragment@13 {
 255 +               target = <&spi2>;
 256 +               __dormant__ {
 257 +                       status = "okay";
 258 +                        #address-cells = <1>;
 259 +                        #size-cells = <0>;
 260 +                       mcp23s08_20: mcp23s08@0 {
 261 +                               compatible = "microchip,mcp23s08";
 262 +                               gpio-controller;
 263 +                               #gpio-cells = <2>;
 264 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-0-present parameter */
 265 +                               reg = <0>;
 266 +                               spi-max-frequency = <500000>;
 267 +                               status = "okay";
 268 +                               #interrupt-cells=<2>;
 269 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-0-int-gpio parameter */
 270 +                       };
 271 +               };
 272 +       };
 273 +
 274 +       // enable one or more mcp23s08s on spi2.1
 275 +       fragment@14 {
 276 +               target = <&spi2>;
 277 +               __dormant__ {
 278 +                       status = "okay";
 279 +                        #address-cells = <1>;
 280 +                        #size-cells = <0>;
 281 +                       mcp23s08_21: mcp23s08@1 {
 282 +                               compatible = "microchip,mcp23s08";
 283 +                               gpio-controller;
 284 +                               #gpio-cells = <2>;
 285 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-1-present parameter */
 286 +                               reg = <1>;
 287 +                               spi-max-frequency = <500000>;
 288 +                               status = "okay";
 289 +                               #interrupt-cells=<2>;
 290 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-1-int-gpio parameter */
 291 +                       };
 292 +               };
 293 +       };
 294 +
 295 +       // enable one or more mcp23s08s on spi2.2
 296 +       fragment@15 {
 297 +               target = <&spi2>;
 298 +               __dormant__ {
 299 +                       status = "okay";
 300 +                        #address-cells = <1>;
 301 +                        #size-cells = <0>;
 302 +                       mcp23s08_22: mcp23s08@2 {
 303 +                               compatible = "microchip,mcp23s08";
 304 +                               gpio-controller;
 305 +                               #gpio-cells = <2>;
 306 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-2-present parameter */
 307 +                               reg = <2>;
 308 +                               spi-max-frequency = <500000>;
 309 +                               status = "okay";
 310 +                               #interrupt-cells=<2>;
 311 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-2-int-gpio parameter */
 312 +                       };
 313 +               };
 314 +       };
 315 +
 316 +       // enable one or more mcp23s17s on spi0.0
 317 +       fragment@16 {
 318 +               target = <&spi0>;
 319 +               __dormant__ {
 320 +                       status = "okay";
 321 +                        #address-cells = <1>;
 322 +                        #size-cells = <0>;
 323 +                       mcp23s17_00: mcp23s17@0 {
 324 +                               compatible = "microchip,mcp23s17";
 325 +                               gpio-controller;
 326 +                               #gpio-cells = <2>;
 327 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-0-present parameter */
 328 +                               reg = <0>;
 329 +                               spi-max-frequency = <500000>;
 330 +                               status = "okay";
 331 +                               #interrupt-cells=<2>;
 332 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-0-int-gpio parameter */
 333 +                       };
 334 +               };
 335 +       };
 336 +
 337 +       // enable one or more mcp23s17s on spi0.1
 338 +       fragment@17 {
 339 +               target = <&spi0>;
 340 +               __dormant__ {
 341 +                       status = "okay";
 342 +                        #address-cells = <1>;
 343 +                        #size-cells = <0>;
 344 +                       mcp23s17_01: mcp23s17@1 {
 345 +                               compatible = "microchip,mcp23s17";
 346 +                               gpio-controller;
 347 +                               #gpio-cells = <2>;
 348 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-1-present parameter */
 349 +                               reg = <1>;
 350 +                               spi-max-frequency = <500000>;
 351 +                               status = "okay";
 352 +                               #interrupt-cells=<2>;
 353 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-1-int-gpio parameter */
 354 +                       };
 355 +               };
 356 +       };
 357 +
 358 +       // enable one or more mcp23s17s on spi1.0
 359 +       fragment@18 {
 360 +               target = <&spi1>;
 361 +               __dormant__ {
 362 +                       status = "okay";
 363 +                        #address-cells = <1>;
 364 +                        #size-cells = <0>;
 365 +                       mcp23s17_10: mcp23s17@0 {
 366 +                               compatible = "microchip,mcp23s17";
 367 +                               gpio-controller;
 368 +                               #gpio-cells = <2>;
 369 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-0-present parameter */
 370 +                               reg = <0>;
 371 +                               spi-max-frequency = <500000>;
 372 +                               status = "okay";
 373 +                               #interrupt-cells=<2>;
 374 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-0-int-gpio parameter */
 375 +                       };
 376 +               };
 377 +       };
 378 +
 379 +       // enable one or more mcp23s17s on spi1.1
 380 +       fragment@19 {
 381 +               target = <&spi1>;
 382 +               __dormant__ {
 383 +                       status = "okay";
 384 +                        #address-cells = <1>;
 385 +                        #size-cells = <0>;
 386 +                       mcp23s17_11: mcp23s17@1 {
 387 +                               compatible = "microchip,mcp23s17";
 388 +                               gpio-controller;
 389 +                               #gpio-cells = <2>;
 390 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-1-present parameter */
 391 +                               reg = <1>;
 392 +                               spi-max-frequency = <500000>;
 393 +                               status = "okay";
 394 +                               #interrupt-cells=<2>;
 395 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-1-int-gpio parameter */
 396 +                       };
 397 +               };
 398 +       };
 399 +
 400 +       // enable one or more mcp23s17s on spi1.2
 401 +       fragment@20 {
 402 +               target = <&spi1>;
 403 +               __dormant__ {
 404 +                       status = "okay";
 405 +                        #address-cells = <1>;
 406 +                        #size-cells = <0>;
 407 +                       mcp23s17_12: mcp23s17@2 {
 408 +                               compatible = "microchip,mcp23s17";
 409 +                               gpio-controller;
 410 +                               #gpio-cells = <2>;
 411 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-2-present parameter */
 412 +                               reg = <2>;
 413 +                               spi-max-frequency = <500000>;
 414 +                               status = "okay";
 415 +                               #interrupt-cells=<2>;
 416 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-2-int-gpio parameter */
 417 +                       };
 418 +               };
 419 +       };
 420 +
 421 +       // enable one or more mcp23s17s on spi2.0
 422 +       fragment@21 {
 423 +               target = <&spi2>;
 424 +               __dormant__ {
 425 +                       status = "okay";
 426 +                        #address-cells = <1>;
 427 +                        #size-cells = <0>;
 428 +                       mcp23s17_20: mcp23s17@0 {
 429 +                               compatible = "microchip,mcp23s17";
 430 +                               gpio-controller;
 431 +                               #gpio-cells = <2>;
 432 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-0-present parameter */
 433 +                               reg = <0>;
 434 +                               spi-max-frequency = <500000>;
 435 +                               status = "okay";
 436 +                               #interrupt-cells=<2>;
 437 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-0-int-gpio parameter */
 438 +                       };
 439 +               };
 440 +       };
 441 +
 442 +       // enable one or more mcp23s17s on spi2.1
 443 +       fragment@22 {
 444 +               target = <&spi2>;
 445 +               __dormant__ {
 446 +                       status = "okay";
 447 +                        #address-cells = <1>;
 448 +                        #size-cells = <0>;
 449 +                       mcp23s17_21: mcp23s17@1 {
 450 +                               compatible = "microchip,mcp23s17";
 451 +                               gpio-controller;
 452 +                               #gpio-cells = <2>;
 453 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-1-present parameter */
 454 +                               reg = <1>;
 455 +                               spi-max-frequency = <500000>;
 456 +                               status = "okay";
 457 +                               #interrupt-cells=<2>;
 458 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-1-int-gpio parameter */
 459 +                       };
 460 +               };
 461 +       };
 462 +
 463 +       // enable one or more mcp23s17s on spi2.2
 464 +       fragment@23 {
 465 +               target = <&spi2>;
 466 +               __dormant__ {
 467 +                       status = "okay";
 468 +                        #address-cells = <1>;
 469 +                        #size-cells = <0>;
 470 +                       mcp23s17_22: mcp23s17@2 {
 471 +                               compatible = "microchip,mcp23s17";
 472 +                               gpio-controller;
 473 +                               #gpio-cells = <2>;
 474 +                               microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-2-present parameter */
 475 +                               reg = <2>;
 476 +                               spi-max-frequency = <500000>;
 477 +                               status = "okay";
 478 +                               #interrupt-cells=<2>;
 479 +                               interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-2-int-gpio parameter */
 480 +                       };
 481 +               };
 482 +       };
 483 +
 484 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.0 as a input with no pull-up/down
 485 +       fragment@24 {
 486 +               target = <&gpio>;
 487 +               __dormant__ {
 488 +                       spi0_0_int_pins: spi0_0_int_pins {
 489 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-0-int-gpio parameter */
 490 +                               brcm,function = <0>;
 491 +                               brcm,pull = <0>;
 492 +                       };
 493 +               };
 494 +       };
 495 +
 496 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.1 as a input with no pull-up/down
 497 +       fragment@25 {
 498 +               target = <&gpio>;
 499 +               __dormant__ {
 500 +                       spi0_1_int_pins: spi0_1_int_pins {
 501 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-1-int-gpio parameter */
 502 +                               brcm,function = <0>;
 503 +                               brcm,pull = <0>;
 504 +                       };
 505 +               };
 506 +       };
 507 +
 508 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.0 as a input with no pull-up/down
 509 +       fragment@26 {
 510 +               target = <&gpio>;
 511 +               __dormant__ {
 512 +                       spi1_0_int_pins: spi1_0_int_pins {
 513 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-0-int-gpio parameter */
 514 +                               brcm,function = <0>;
 515 +                               brcm,pull = <0>;
 516 +                       };
 517 +               };
 518 +       };
 519 +
 520 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.1 as a input with no pull-up/down
 521 +       fragment@27 {
 522 +               target = <&gpio>;
 523 +               __dormant__ {
 524 +                       spi1_1_int_pins: spi1_1_int_pins {
 525 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-1-int-gpio parameter */
 526 +                               brcm,function = <0>;
 527 +                               brcm,pull = <0>;
 528 +                       };
 529 +               };
 530 +       };
 531 +
 532 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.2 as a input with no pull-up/down
 533 +       fragment@28 {
 534 +               target = <&gpio>;
 535 +               __dormant__ {
 536 +                       spi1_2_int_pins: spi1_2_int_pins {
 537 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-2-int-gpio parameter */
 538 +                               brcm,function = <0>;
 539 +                               brcm,pull = <0>;
 540 +                       };
 541 +               };
 542 +       };
 543 +
 544 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.0 as a input with no pull-up/down
 545 +       fragment@29 {
 546 +               target = <&gpio>;
 547 +               __dormant__ {
 548 +                       spi2_0_int_pins: spi2_0_int_pins {
 549 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-0-int-gpio parameter */
 550 +                               brcm,function = <0>;
 551 +                               brcm,pull = <0>;
 552 +                       };
 553 +               };
 554 +       };
 555 +
 556 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.1 as a input with no pull-up/down
 557 +       fragment@30 {
 558 +               target = <&gpio>;
 559 +               __dormant__ {
 560 +                       spi2_1_int_pins: spi2_1_int_pins {
 561 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-1-int-gpio parameter */
 562 +                               brcm,function = <0>;
 563 +                               brcm,pull = <0>;
 564 +                       };
 565 +               };
 566 +       };
 567 +
 568 +       // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.2 as a input with no pull-up/down
 569 +       fragment@31 {
 570 +               target = <&gpio>;
 571 +               __dormant__ {
 572 +                       spi2_2_int_pins: spi2_2_int_pins {
 573 +                               brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-2-int-gpio parameter */
 574 +                               brcm,function = <0>;
 575 +                               brcm,pull = <0>;
 576 +                       };
 577 +               };
 578 +       };
 579 +
 580 +       // Enable interrupts for a mcp23s08 on spi0.0.
 581 +       // Use default active low interrupt signalling.
 582 +       fragment@32 {
 583 +               target = <&mcp23s08_00>;
 584 +               __dormant__ {
 585 +                       interrupt-parent = <&gpio>;
 586 +                       interrupt-controller;
 587 +               };
 588 +       };
 589 +
 590 +       // Enable interrupts for a mcp23s08 on spi0.1.
 591 +       // Use default active low interrupt signalling.
 592 +       fragment@33 {
 593 +               target = <&mcp23s08_01>;
 594 +               __dormant__ {
 595 +                       interrupt-parent = <&gpio>;
 596 +                       interrupt-controller;
 597 +               };
 598 +       };
 599 +
 600 +       // Enable interrupts for a mcp23s08 on spi1.0.
 601 +       // Use default active low interrupt signalling.
 602 +       fragment@34 {
 603 +               target = <&mcp23s08_10>;
 604 +               __dormant__ {
 605 +                       interrupt-parent = <&gpio>;
 606 +                       interrupt-controller;
 607 +               };
 608 +       };
 609 +
 610 +       // Enable interrupts for a mcp23s08 on spi1.1.
 611 +       // Use default active low interrupt signalling.
 612 +       fragment@35 {
 613 +               target = <&mcp23s08_11>;
 614 +               __dormant__ {
 615 +                       interrupt-parent = <&gpio>;
 616 +                       interrupt-controller;
 617 +               };
 618 +       };
 619 +
 620 +       // Enable interrupts for a mcp23s08 on spi1.2.
 621 +       // Use default active low interrupt signalling.
 622 +       fragment@36 {
 623 +               target = <&mcp23s08_12>;
 624 +               __dormant__ {
 625 +                       interrupt-parent = <&gpio>;
 626 +                       interrupt-controller;
 627 +               };
 628 +       };
 629 +
 630 +       // Enable interrupts for a mcp23s08 on spi2.0.
 631 +       // Use default active low interrupt signalling.
 632 +       fragment@37 {
 633 +               target = <&mcp23s08_20>;
 634 +               __dormant__ {
 635 +                       interrupt-parent = <&gpio>;
 636 +                       interrupt-controller;
 637 +               };
 638 +       };
 639 +
 640 +       // Enable interrupts for a mcp23s08 on spi2.1.
 641 +       // Use default active low interrupt signalling.
 642 +       fragment@38 {
 643 +               target = <&mcp23s08_21>;
 644 +               __dormant__ {
 645 +                       interrupt-parent = <&gpio>;
 646 +                       interrupt-controller;
 647 +               };
 648 +       };
 649 +
 650 +       // Enable interrupts for a mcp23s08 on spi2.2.
 651 +       // Use default active low interrupt signalling.
 652 +       fragment@39 {
 653 +               target = <&mcp23s08_22>;
 654 +               __dormant__ {
 655 +                       interrupt-parent = <&gpio>;
 656 +                       interrupt-controller;
 657 +               };
 658 +       };
 659 +
 660 +       // Enable interrupts for a mcp23s17 on spi0.0.
 661 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 662 +       // Use default active low interrupt signalling.
 663 +       fragment@40 {
 664 +               target = <&mcp23s17_00>;
 665 +               __dormant__ {
 666 +                       interrupt-parent = <&gpio>;
 667 +                       interrupt-controller;
 668 +                       microchip,irq-mirror;
 669 +               };
 670 +       };
 671 +
 672 +       // Enable interrupts for a mcp23s17 on spi0.1.
 673 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 674 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 675 +       fragment@41 {
 676 +               target = <&mcp23s17_01>;
 677 +               __dormant__ {
 678 +                       interrupt-parent = <&gpio>;
 679 +                       interrupt-controller;
 680 +                       microchip,irq-mirror;
 681 +               };
 682 +       };
 683 +
 684 +       // Enable interrupts for a mcp23s17 on spi1.0.
 685 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 686 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 687 +       fragment@42 {
 688 +               target = <&mcp23s17_10>;
 689 +               __dormant__ {
 690 +                       interrupt-parent = <&gpio>;
 691 +                       interrupt-controller;
 692 +                       microchip,irq-mirror;
 693 +               };
 694 +       };
 695 +
 696 +       // Enable interrupts for a mcp23s17 on spi1.1.
 697 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 698 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 699 +       fragment@43 {
 700 +               target = <&mcp23s17_11>;
 701 +               __dormant__ {
 702 +                       interrupt-parent = <&gpio>;
 703 +                       interrupt-controller;
 704 +                       microchip,irq-mirror;
 705 +               };
 706 +       };
 707 +
 708 +       // Enable interrupts for a mcp23s17 on spi1.2.
 709 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 710 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 711 +       fragment@44 {
 712 +               target = <&mcp23s17_12>;
 713 +               __dormant__ {
 714 +                       interrupt-parent = <&gpio>;
 715 +                       interrupt-controller;
 716 +                       microchip,irq-mirror;
 717 +               };
 718 +       };
 719 +
 720 +       // Enable interrupts for a mcp23s17 on spi2.0.
 721 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 722 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 723 +       fragment@45 {
 724 +               target = <&mcp23s17_20>;
 725 +               __dormant__ {
 726 +                       interrupt-parent = <&gpio>;
 727 +                       interrupt-controller;
 728 +                       microchip,irq-mirror;
 729 +               };
 730 +       };
 731 +
 732 +       // Enable interrupts for a mcp23s17 on spi2.1.
 733 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 734 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 735 +       fragment@46 {
 736 +               target = <&mcp23s17_21>;
 737 +               __dormant__ {
 738 +                       interrupt-parent = <&gpio>;
 739 +                       interrupt-controller;
 740 +                       microchip,irq-mirror;
 741 +               };
 742 +       };
 743 +
 744 +       // Enable interrupts for a mcp23s17 on spi2.2.
 745 +       // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
 746 +       // Configure INTA/B outputs of mcp23s08/17 as active low.
 747 +       fragment@47 {
 748 +               target = <&mcp23s17_22>;
 749 +               __dormant__ {
 750 +                       interrupt-parent = <&gpio>;
 751 +                       interrupt-controller;
 752 +                       microchip,irq-mirror;
 753 +               };
 754 +       };
 755 +
 756 +       __overrides__ {
 757 +               s08-spi0-0-present = <0>,"+0+8",  <&mcp23s08_00>,"microchip,spi-present-mask:0";
 758 +               s08-spi0-1-present = <0>,"+1+9",  <&mcp23s08_01>,"microchip,spi-present-mask:0";
 759 +               s08-spi1-0-present = <0>,"+2+10", <&mcp23s08_10>,"microchip,spi-present-mask:0";
 760 +               s08-spi1-1-present = <0>,"+3+11", <&mcp23s08_11>,"microchip,spi-present-mask:0";
 761 +               s08-spi1-2-present = <0>,"+4+12", <&mcp23s08_12>,"microchip,spi-present-mask:0";
 762 +               s08-spi2-0-present = <0>,"+5+13", <&mcp23s08_20>,"microchip,spi-present-mask:0";
 763 +               s08-spi2-1-present = <0>,"+6+14", <&mcp23s08_21>,"microchip,spi-present-mask:0";
 764 +               s08-spi2-2-present = <0>,"+7+15", <&mcp23s08_22>,"microchip,spi-present-mask:0";
 765 +               s17-spi0-0-present = <0>,"+0+16", <&mcp23s17_00>,"microchip,spi-present-mask:0";
 766 +               s17-spi0-1-present = <0>,"+1+17", <&mcp23s17_01>,"microchip,spi-present-mask:0";
 767 +               s17-spi1-0-present = <0>,"+2+18", <&mcp23s17_10>,"microchip,spi-present-mask:0";
 768 +               s17-spi1-1-present = <0>,"+3+19", <&mcp23s17_11>,"microchip,spi-present-mask:0";
 769 +               s17-spi1-2-present = <0>,"+4+20", <&mcp23s17_12>,"microchip,spi-present-mask:0";
 770 +               s17-spi2-0-present = <0>,"+5+21", <&mcp23s17_20>,"microchip,spi-present-mask:0";
 771 +               s17-spi2-1-present = <0>,"+6+22", <&mcp23s17_21>,"microchip,spi-present-mask:0";
 772 +               s17-spi2-2-present = <0>,"+7+23", <&mcp23s17_22>,"microchip,spi-present-mask:0";
 773 +               s08-spi0-0-int-gpio = <0>,"+24+32", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s08_00>,"interrupts:0";
 774 +               s08-spi0-1-int-gpio = <0>,"+25+33", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s08_01>,"interrupts:0";
 775 +               s08-spi1-0-int-gpio = <0>,"+26+34", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s08_10>,"interrupts:0";
 776 +               s08-spi1-1-int-gpio = <0>,"+27+35", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s08_11>,"interrupts:0";
 777 +               s08-spi1-2-int-gpio = <0>,"+28+36", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s08_12>,"interrupts:0";
 778 +               s08-spi2-0-int-gpio = <0>,"+29+37", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s08_20>,"interrupts:0";
 779 +               s08-spi2-1-int-gpio = <0>,"+30+38", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s08_21>,"interrupts:0";
 780 +               s08-spi2-2-int-gpio = <0>,"+31+39", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s08_22>,"interrupts:0";
 781 +               s17-spi0-0-int-gpio = <0>,"+24+40", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s17_00>,"interrupts:0";
 782 +               s17-spi0-1-int-gpio = <0>,"+25+41", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s17_01>,"interrupts:0";
 783 +               s17-spi1-0-int-gpio = <0>,"+26+42", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s17_10>,"interrupts:0";
 784 +               s17-spi1-1-int-gpio = <0>,"+27+43", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s17_11>,"interrupts:0";
 785 +               s17-spi1-2-int-gpio = <0>,"+28+44", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s17_12>,"interrupts:0";
 786 +               s17-spi2-0-int-gpio = <0>,"+29+45", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s17_20>,"interrupts:0";
 787 +               s17-spi2-1-int-gpio = <0>,"+30+46", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s17_21>,"interrupts:0";
 788 +               s17-spi2-2-int-gpio = <0>,"+31+47", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s17_22>,"interrupts:0";
 789 +       };
 790 +};
 791 +