target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/rtl8366rb.h>
  19
  20 #include "rtl8366_smi.h"
  21
  22 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  23 #define RTL8366RB_DRIVER_VER    "0.2.2"
  24
  25 #define RTL8366RB_PHY_NO_MAX    4
  26 #define RTL8366RB_PHY_PAGE_MAX  7
  27 #define RTL8366RB_PHY_ADDR_MAX  31
  28
  29 /* Switch Global Configuration register */
  30 #define RTL8366RB_SGCR                          0x0000
  31 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  32 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  33 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  34 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  35 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  38 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  39 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366RB_PECR                          0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366RB_SSCR0                         0x0002
  46 #define RTL8366RB_SSCR1                         0x0003
  47 #define RTL8366RB_SSCR2                         0x0004
  48 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  49
  50 #define RTL8366RB_RESET_CTRL_REG                0x0100
  51 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  52 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  53
  54 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  55 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  56 #define RTL8366RB_CHIP_ID_REG                   0x0509
  57 #define RTL8366RB_CHIP_ID_8366                  0x5937
  58
  59 /* PHY registers control */
  60 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  61 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  62
  63 #define RTL8366RB_PHY_CTRL_READ                 1
  64 #define RTL8366RB_PHY_CTRL_WRITE                0
  65
  66 #define RTL8366RB_PHY_REG_MASK                  0x1f
  67 #define RTL8366RB_PHY_PAGE_OFFSET               5
  68 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  69 #define RTL8366RB_PHY_NO_OFFSET                 9
  70 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  71
  72 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  73
  74 /* LED control registers */
  75 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  76 #define RTL8366RB_LED_BLINKRATE_BIT             0
  77 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  78
  79 #define RTL8366RB_LED_CTRL_REG                  0x0431
  80 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  81 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  82
  83 #define RTL8366RB_MIB_COUNT                     33
  84 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  85 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  86 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  87 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  88 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  89 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  90 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  91 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  92 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  93
  94 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  95 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  96                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
  97 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
  98 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
  99
 100
 101 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 102 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 103
 104
 105 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 106 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 107 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 108
 109 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 110
 111
 112 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 113 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 114 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 115 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 116 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 117 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 118 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 119
 120
 121 #define RTL8366RB_PORT_NUM_CPU          5
 122 #define RTL8366RB_NUM_PORTS             6
 123 #define RTL8366RB_NUM_VLANS             16
 124 #define RTL8366RB_NUM_LEDGROUPS         4
 125 #define RTL8366RB_NUM_VIDS              4096
 126 #define RTL8366RB_PRIORITYMAX           7
 127 #define RTL8366RB_FIDMAX                7
 128
 129
 130 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 131 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 132 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 133 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 134 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 135
 136 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 137
 138 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 139                                          RTL8366RB_PORT_2 |     \
 140                                          RTL8366RB_PORT_3 |     \
 141                                          RTL8366RB_PORT_4 |     \
 142                                          RTL8366RB_PORT_5 |     \
 143                                          RTL8366RB_PORT_CPU)
 144
 145 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 146                                          RTL8366RB_PORT_2 |     \
 147                                          RTL8366RB_PORT_3 |     \
 148                                          RTL8366RB_PORT_4 |     \
 149                                          RTL8366RB_PORT_5)
 150
 151 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 152                                          RTL8366RB_PORT_2 |     \
 153                                          RTL8366RB_PORT_3 |     \
 154                                          RTL8366RB_PORT_4)
 155
 156 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 157
 158 #define RTL8366RB_VLAN_VID_MASK         0xfff
 159 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 160 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 161 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 162 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 163 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 164 #define RTL8366RB_VLAN_FID_MASK         0x7
 165
 166 struct rtl8366rb {
 167         struct device           *parent;
 168         struct rtl8366_smi      smi;
 169 };
 170
 171 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 172         { 0,  0, 4, "IfInOctets"                                },
 173         { 0,  4, 4, "EtherStatsOctets"                          },
 174         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 175         { 0, 10, 2, "EtherFragments"                            },
 176         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 177         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 178         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 179         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 180         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 181         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 182         { 0, 24, 2, "EtherOversizeStats"                        },
 183         { 0, 26, 2, "EtherStatsJabbers"                         },
 184         { 0, 28, 2, "IfInUcastPkts"                             },
 185         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 186         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 187         { 0, 34, 2, "EtherStatsDropEvents"                      },
 188         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 189         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 190         { 0, 40, 2, "Dot3InPauseFrames"                         },
 191         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 192         { 0, 44, 4, "IfOutOctets"                               },
 193         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 194         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 195         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 196         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 197         { 0, 56, 2, "EtherStatsCollisions"                      },
 198         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 199         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 200         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 201         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 202         { 0, 66, 2, "IfOutUcastPkts"                            },
 203         { 0, 68, 2, "IfOutMulticastPkts"                        },
 204         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 205 };
 206
 207 #define REG_WR(_smi, _reg, _val)                                        \
 208         do {                                                            \
 209                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 210                 if (err)                                                \
 211                         return err;                                     \
 212         } while (0)
 213
 214 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 215         do {                                                            \
 216                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 217                 if (err)                                                \
 218                         return err;                                     \
 219         } while (0)
 220
 221 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
 222 {
 223         return container_of(smi, struct rtl8366rb, smi);
 224 }
 225
 226 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
 227 {
 228         struct rtl8366_smi *smi = sw_to_rtl8366_smi(sw);
 229         return smi_to_rtl8366rb(smi);
 230 }
 231
 232 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 233 {
 234         int timeout = 10;
 235         u32 data;
 236
 237         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 238                               RTL8366RB_CHIP_CTRL_RESET_HW);
 239         do {
 240                 msleep(1);
 241                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 242                         return -EIO;
 243
 244                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 245                         break;
 246         } while (--timeout);
 247
 248         if (!timeout) {
 249                 printk("Timeout waiting for the switch to reset\n");
 250                 return -EIO;
 251         }
 252
 253         return 0;
 254 }
 255
 256 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 257 {
 258         int err;
 259
 260         /* set maximum packet length to 1536 bytes */
 261         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 262                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 263
 264         /* enable all ports */
 265         REG_WR(smi, RTL8366RB_PECR, 0);
 266
 267         /* disable learning for all ports */
 268         REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
 269
 270         /* disable auto ageing for all ports */
 271         REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
 272
 273         /*
 274          * discard VLAN tagged packets if the port is not a member of
 275          * the VLAN with which the packets is associated.
 276          */
 277         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 278
 279         /* don't drop packets whose DA has not been learned */
 280         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 281
 282         return 0;
 283 }
 284
 285 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 286                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 287 {
 288         u32 reg;
 289         int ret;
 290
 291         if (phy_no > RTL8366RB_PHY_NO_MAX)
 292                 return -EINVAL;
 293
 294         if (page > RTL8366RB_PHY_PAGE_MAX)
 295                 return -EINVAL;
 296
 297         if (addr > RTL8366RB_PHY_ADDR_MAX)
 298                 return -EINVAL;
 299
 300         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 301                                     RTL8366RB_PHY_CTRL_READ);
 302         if (ret)
 303                 return ret;
 304
 305         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 306               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 307               (addr & RTL8366RB_PHY_REG_MASK);
 308
 309         ret = rtl8366_smi_write_reg(smi, reg, 0);
 310         if (ret)
 311                 return ret;
 312
 313         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 314         if (ret)
 315                 return ret;
 316
 317         return 0;
 318 }
 319
 320 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 321                                   u32 phy_no, u32 page, u32 addr, u32 data)
 322 {
 323         u32 reg;
 324         int ret;
 325
 326         if (phy_no > RTL8366RB_PHY_NO_MAX)
 327                 return -EINVAL;
 328
 329         if (page > RTL8366RB_PHY_PAGE_MAX)
 330                 return -EINVAL;
 331
 332         if (addr > RTL8366RB_PHY_ADDR_MAX)
 333                 return -EINVAL;
 334
 335         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 336                                     RTL8366RB_PHY_CTRL_WRITE);
 337         if (ret)
 338                 return ret;
 339
 340         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 341               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 342               (addr & RTL8366RB_PHY_REG_MASK);
 343
 344         ret = rtl8366_smi_write_reg(smi, reg, data);
 345         if (ret)
 346                 return ret;
 347
 348         return 0;
 349 }
 350
 351 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 352                                      int port, unsigned long long *val)
 353 {
 354         int i;
 355         int err;
 356         u32 addr, data;
 357         u64 mibvalue;
 358
 359         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 360                 return -EINVAL;
 361
 362         addr = RTL8366RB_MIB_COUNTER_BASE +
 363                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 364                rtl8366rb_mib_counters[counter].offset;
 365
 366         /*
 367          * Writing access counter address first
 368          * then ASIC will prepare 64bits counter wait for being retrived
 369          */
 370         data = 0; /* writing data will be discard by ASIC */
 371         err = rtl8366_smi_write_reg(smi, addr, data);
 372         if (err)
 373                 return err;
 374
 375         /* read MIB control register */
 376         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 377         if (err)
 378                 return err;
 379
 380         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 381                 return -EBUSY;
 382
 383         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 384                 return -EIO;
 385
 386         mibvalue = 0;
 387         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 388                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 389                 if (err)
 390                         return err;
 391
 392                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 393         }
 394
 395         *val = mibvalue;
 396         return 0;
 397 }
 398
 399 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 400                                  struct rtl8366_vlan_4k *vlan4k)
 401 {
 402         u32 data[3];
 403         int err;
 404         int i;
 405
 406         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 407
 408         if (vid >= RTL8366RB_NUM_VIDS)
 409                 return -EINVAL;
 410
 411         /* write VID */
 412         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 413                                     vid & RTL8366RB_VLAN_VID_MASK);
 414         if (err)
 415                 return err;
 416
 417         /* write table access control word */
 418         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 419                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 420         if (err)
 421                 return err;
 422
 423         for (i = 0; i < 3; i++) {
 424                 err = rtl8366_smi_read_reg(smi,
 425                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 426                                            &data[i]);
 427                 if (err)
 428                         return err;
 429         }
 430
 431         vlan4k->vid = vid;
 432         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 433                         RTL8366RB_VLAN_UNTAG_MASK;
 434         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 435         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 436
 437         return 0;
 438 }
 439
 440 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 441                                  const struct rtl8366_vlan_4k *vlan4k)
 442 {
 443         u32 data[3];
 444         int err;
 445         int i;
 446
 447         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 448             vlan4k->member > RTL8366RB_PORT_ALL ||
 449             vlan4k->untag > RTL8366RB_PORT_ALL ||
 450             vlan4k->fid > RTL8366RB_FIDMAX)
 451                 return -EINVAL;
 452
 453         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 454         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 455                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 456                         RTL8366RB_VLAN_UNTAG_SHIFT);
 457         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 458
 459         for (i = 0; i < 3; i++) {
 460                 err = rtl8366_smi_write_reg(smi,
 461                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 462                                             data[i]);
 463                 if (err)
 464                         return err;
 465         }
 466
 467         /* write table access control word */
 468         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 469                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 470
 471         return err;
 472 }
 473
 474 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 475                                  struct rtl8366_vlan_mc *vlanmc)
 476 {
 477         u32 data[3];
 478         int err;
 479         int i;
 480
 481         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 482
 483         if (index >= RTL8366RB_NUM_VLANS)
 484                 return -EINVAL;
 485
 486         for (i = 0; i < 3; i++) {
 487                 err = rtl8366_smi_read_reg(smi,
 488                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 489                                            &data[i]);
 490                 if (err)
 491                         return err;
 492         }
 493
 494         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 495         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 496                            RTL8366RB_VLAN_PRIORITY_MASK;
 497         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 498                         RTL8366RB_VLAN_UNTAG_MASK;
 499         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 500         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 501
 502         return 0;
 503 }
 504
 505 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 506                                  const struct rtl8366_vlan_mc *vlanmc)
 507 {
 508         u32 data[3];
 509         int err;
 510         int i;
 511
 512         if (index >= RTL8366RB_NUM_VLANS ||
 513             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 514             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 515             vlanmc->member > RTL8366RB_PORT_ALL ||
 516             vlanmc->untag > RTL8366RB_PORT_ALL ||
 517             vlanmc->fid > RTL8366RB_FIDMAX)
 518                 return -EINVAL;
 519
 520         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 521                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 522                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 523         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 524                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 525                         RTL8366RB_VLAN_UNTAG_SHIFT);
 526         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 527
 528         for (i = 0; i < 3; i++) {
 529                 err = rtl8366_smi_write_reg(smi,
 530                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 531                                             data[i]);
 532                 if (err)
 533                         return err;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 540 {
 541         u32 data;
 542         int err;
 543
 544         if (port >= RTL8366RB_NUM_PORTS)
 545                 return -EINVAL;
 546
 547         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 548                                    &data);
 549         if (err)
 550                 return err;
 551
 552         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 553                RTL8366RB_PORT_VLAN_CTRL_MASK;
 554
 555         return 0;
 556
 557 }
 558
 559 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 560 {
 561         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 562                 return -EINVAL;
 563
 564         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 565                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 566                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 567                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 568                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 569 }
 570
 571 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 572 {
 573         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 574                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 575 }
 576
 577 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 578 {
 579         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 580                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 581                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 582 }
 583
 584 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 585                                   const struct switch_attr *attr,
 586                                   struct switch_val *val)
 587 {
 588         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 589
 590         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 591                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 592 }
 593
 594 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
 595                                        const struct switch_attr *attr,
 596                                        struct switch_val *val)
 597 {
 598         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 599         u32 data;
 600
 601         if (attr->ofs == 1) {
 602                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 603
 604                 if (data & RTL8366RB_SGCR_EN_VLAN)
 605                         val->value.i = 1;
 606                 else
 607                         val->value.i = 0;
 608         } else if (attr->ofs == 2) {
 609                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 610
 611                 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
 612                         val->value.i = 1;
 613                 else
 614                         val->value.i = 0;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 621                                      const struct switch_attr *attr,
 622                                      struct switch_val *val)
 623 {
 624         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 625         u32 data;
 626
 627         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 628
 629         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 630
 631         return 0;
 632 }
 633
 634 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 635                                     const struct switch_attr *attr,
 636                                     struct switch_val *val)
 637 {
 638         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 639
 640         if (val->value.i >= 6)
 641                 return -EINVAL;
 642
 643         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 644                                 RTL8366RB_LED_BLINKRATE_MASK,
 645                                 val->value.i);
 646 }
 647
 648 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
 649                                        const struct switch_attr *attr,
 650                                        struct switch_val *val)
 651 {
 652         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 653
 654         if (attr->ofs == 1)
 655                 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
 656         else
 657                 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
 658 }
 659
 660 static const char *rtl8366rb_speed_str(unsigned speed)
 661 {
 662         switch (speed) {
 663         case 0:
 664                 return "10baseT";
 665         case 1:
 666                 return "100baseT";
 667         case 2:
 668                 return "1000baseT";
 669         }
 670
 671         return "unknown";
 672 }
 673
 674 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 675                                      const struct switch_attr *attr,
 676                                      struct switch_val *val)
 677 {
 678         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 679         u32 len = 0, data = 0;
 680
 681         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 682                 return -EINVAL;
 683
 684         memset(smi->buf, '\0', sizeof(smi->buf));
 685         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 686                              (val->port_vlan / 2), &data);
 687
 688         if (val->port_vlan % 2)
 689                 data = data >> 8;
 690
 691         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 692                 len = snprintf(smi->buf, sizeof(smi->buf),
 693                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 694                                 val->port_vlan,
 695                                 rtl8366rb_speed_str(data &
 696                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 697                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 698                                         "full" : "half",
 699                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 700                                         "tx-pause ": "",
 701                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 702                                         "rx-pause " : "",
 703                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 704                                         "nway ": "");
 705         } else {
 706                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 707                                 val->port_vlan);
 708         }
 709
 710         val->value.s = smi->buf;
 711         val->len = len;
 712
 713         return 0;
 714 }
 715
 716 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
 717                                      const struct switch_attr *attr,
 718                                      struct switch_val *val)
 719 {
 720         int i;
 721         u32 len = 0;
 722         struct rtl8366_vlan_4k vlan4k;
 723         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 724         char *buf = smi->buf;
 725         int err;
 726
 727         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 728                 return -EINVAL;
 729
 730         memset(buf, '\0', sizeof(smi->buf));
 731
 732         err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 733         if (err)
 734                 return err;
 735
 736         len += snprintf(buf + len, sizeof(smi->buf) - len,
 737                         "VLAN %d: Ports: '", vlan4k.vid);
 738
 739         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 740                 if (!(vlan4k.member & (1 << i)))
 741                         continue;
 742
 743                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 744                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 745         }
 746
 747         len += snprintf(buf + len, sizeof(smi->buf) - len,
 748                         "', members=%04x, untag=%04x, fid=%u",
 749                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 750
 751         val->value.s = buf;
 752         val->len = len;
 753
 754         return 0;
 755 }
 756
 757 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 758                                     const struct switch_attr *attr,
 759                                     struct switch_val *val)
 760 {
 761         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 762         u32 data;
 763         u32 mask;
 764         u32 reg;
 765
 766         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 767                 return -EINVAL;
 768
 769         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 770                 reg = RTL8366RB_LED_BLINKRATE_REG;
 771                 mask = 0xF << 4;
 772                 data = val->value.i << 4;
 773         } else {
 774                 reg = RTL8366RB_LED_CTRL_REG;
 775                 mask = 0xF << (val->port_vlan * 4),
 776                 data = val->value.i << (val->port_vlan * 4);
 777         }
 778
 779         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
 780 }
 781
 782 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 783                                     const struct switch_attr *attr,
 784                                     struct switch_val *val)
 785 {
 786         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 787         u32 data = 0;
 788
 789         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 790                 return -EINVAL;
 791
 792         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 793         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 794
 795         return 0;
 796 }
 797
 798 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 799                                        const struct switch_attr *attr,
 800                                        struct switch_val *val)
 801 {
 802         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 803
 804         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 805                 return -EINVAL;
 806
 807         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 808                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 809 }
 810
 811 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
 812                                     const struct switch_attr *attr,
 813                                     struct switch_val *val)
 814 {
 815         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 816         int i, len = 0;
 817         unsigned long long counter = 0;
 818         char *buf = smi->buf;
 819
 820         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 821                 return -EINVAL;
 822
 823         len += snprintf(buf + len, sizeof(smi->buf) - len,
 824                         "Port %d MIB counters\n",
 825                         val->port_vlan);
 826
 827         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 828                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 829                                 "%-36s: ", rtl8366rb_mib_counters[i].name);
 830                 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
 831                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 832                                         "%llu\n", counter);
 833                 else
 834                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 835                                         "%s\n", "error");
 836         }
 837
 838         val->value.s = buf;
 839         val->len = len;
 840         return 0;
 841 }
 842
 843 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
 844                                       struct switch_val *val)
 845 {
 846         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 847         struct switch_port *port;
 848         struct rtl8366_vlan_4k vlan4k;
 849         int i;
 850
 851         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 852                 return -EINVAL;
 853
 854         rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 855
 856         port = &val->value.ports[0];
 857         val->len = 0;
 858         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 859                 if (!(vlan4k.member & BIT(i)))
 860                         continue;
 861
 862                 port->id = i;
 863                 port->flags = (vlan4k.untag & BIT(i)) ?
 864                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
 865                 val->len++;
 866                 port++;
 867         }
 868         return 0;
 869 }
 870
 871 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
 872                                       struct switch_val *val)
 873 {
 874         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 875         struct switch_port *port;
 876         u32 member = 0;
 877         u32 untag = 0;
 878         int i;
 879
 880         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 881                 return -EINVAL;
 882
 883         port = &val->value.ports[0];
 884         for (i = 0; i < val->len; i++, port++) {
 885                 member |= BIT(port->id);
 886
 887                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
 888                         untag |= BIT(port->id);
 889         }
 890
 891         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
 892 }
 893
 894 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
 895 {
 896         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 897         return rtl8366_get_pvid(smi, port, val);
 898 }
 899
 900 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
 901 {
 902         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 903         return rtl8366_set_pvid(smi, port, val);
 904 }
 905
 906 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
 907 {
 908         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 909         int err;
 910
 911         err = rtl8366rb_reset_chip(smi);
 912         if (err)
 913                 return err;
 914
 915         err = rtl8366rb_hw_init(smi);
 916         if (err)
 917                 return err;
 918
 919         return rtl8366_reset_vlan(smi);
 920 }
 921
 922 static struct switch_attr rtl8366rb_globals[] = {
 923         {
 924                 .type = SWITCH_TYPE_INT,
 925                 .name = "enable_vlan",
 926                 .description = "Enable VLAN mode",
 927                 .set = rtl8366rb_sw_set_vlan_enable,
 928                 .get = rtl8366rb_sw_get_vlan_enable,
 929                 .max = 1,
 930                 .ofs = 1
 931         }, {
 932                 .type = SWITCH_TYPE_INT,
 933                 .name = "enable_vlan4k",
 934                 .description = "Enable VLAN 4K mode",
 935                 .set = rtl8366rb_sw_set_vlan_enable,
 936                 .get = rtl8366rb_sw_get_vlan_enable,
 937                 .max = 1,
 938                 .ofs = 2
 939         }, {
 940                 .type = SWITCH_TYPE_NOVAL,
 941                 .name = "reset_mibs",
 942                 .description = "Reset all MIB counters",
 943                 .set = rtl8366rb_sw_reset_mibs,
 944         }, {
 945                 .type = SWITCH_TYPE_INT,
 946                 .name = "blinkrate",
 947                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 948                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 949                 .set = rtl8366rb_sw_set_blinkrate,
 950                 .get = rtl8366rb_sw_get_blinkrate,
 951                 .max = 5
 952         },
 953 };
 954
 955 static struct switch_attr rtl8366rb_port[] = {
 956         {
 957                 .type = SWITCH_TYPE_STRING,
 958                 .name = "link",
 959                 .description = "Get port link information",
 960                 .max = 1,
 961                 .set = NULL,
 962                 .get = rtl8366rb_sw_get_port_link,
 963         }, {
 964                 .type = SWITCH_TYPE_NOVAL,
 965                 .name = "reset_mib",
 966                 .description = "Reset single port MIB counters",
 967                 .set = rtl8366rb_sw_reset_port_mibs,
 968         }, {
 969                 .type = SWITCH_TYPE_STRING,
 970                 .name = "mib",
 971                 .description = "Get MIB counters for port",
 972                 .max = 33,
 973                 .set = NULL,
 974                 .get = rtl8366rb_sw_get_port_mib,
 975         }, {
 976                 .type = SWITCH_TYPE_INT,
 977                 .name = "led",
 978                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 979                 .max = 15,
 980                 .set = rtl8366rb_sw_set_port_led,
 981                 .get = rtl8366rb_sw_get_port_led,
 982         },
 983 };
 984
 985 static struct switch_attr rtl8366rb_vlan[] = {
 986         {
 987                 .type = SWITCH_TYPE_STRING,
 988                 .name = "info",
 989                 .description = "Get vlan information",
 990                 .max = 1,
 991                 .set = NULL,
 992                 .get = rtl8366rb_sw_get_vlan_info,
 993         },
 994 };
 995
 996 /* template */
 997 static struct switch_dev rtl8366_switch_dev = {
 998         .name = "RTL8366S",
 999         .cpu_port = RTL8366RB_PORT_NUM_CPU,
1000         .ports = RTL8366RB_NUM_PORTS,
1001         .vlans = RTL8366RB_NUM_VLANS,
1002         .attr_global = {
1003                 .attr = rtl8366rb_globals,
1004                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1005         },
1006         .attr_port = {
1007                 .attr = rtl8366rb_port,
1008                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1009         },
1010         .attr_vlan = {
1011                 .attr = rtl8366rb_vlan,
1012                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1013         },
1014
1015         .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1016         .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1017         .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1018         .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1019         .reset_switch = rtl8366rb_sw_reset_switch,
1020 };
1021
1022 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1023 {
1024         struct switch_dev *dev = &rtl->smi.sw_dev;
1025         int err;
1026
1027         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1028         dev->priv = rtl;
1029         dev->devname = dev_name(rtl->parent);
1030
1031         err = register_switch(dev, NULL);
1032         if (err)
1033                 dev_err(rtl->parent, "switch registration failed\n");
1034
1035         return err;
1036 }
1037
1038 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1039 {
1040         unregister_switch(&rtl->smi.sw_dev);
1041 }
1042
1043 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1044 {
1045         struct rtl8366_smi *smi = bus->priv;
1046         u32 val = 0;
1047         int err;
1048
1049         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1050         if (err)
1051                 return 0xffff;
1052
1053         return val;
1054 }
1055
1056 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1057 {
1058         struct rtl8366_smi *smi = bus->priv;
1059         u32 t;
1060         int err;
1061
1062         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1063         /* flush write */
1064         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1065
1066         return err;
1067 }
1068
1069 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1070 {
1071         return (bus->read == rtl8366rb_mii_read &&
1072                 bus->write == rtl8366rb_mii_write);
1073 }
1074
1075 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1076 {
1077         struct rtl8366_smi *smi = &rtl->smi;
1078         int ret;
1079
1080         ret = rtl8366rb_reset_chip(smi);
1081         if (ret)
1082                 return ret;
1083
1084         ret = rtl8366rb_hw_init(smi);
1085         return ret;
1086 }
1087
1088 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1089 {
1090         u32 chip_id = 0;
1091         u32 chip_ver = 0;
1092         int ret;
1093
1094         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1095         if (ret) {
1096                 dev_err(smi->parent, "unable to read chip id\n");
1097                 return ret;
1098         }
1099
1100         switch (chip_id) {
1101         case RTL8366RB_CHIP_ID_8366:
1102                 break;
1103         default:
1104                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1105                 return -ENODEV;
1106         }
1107
1108         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1109                                    &chip_ver);
1110         if (ret) {
1111                 dev_err(smi->parent, "unable to read chip version\n");
1112                 return ret;
1113         }
1114
1115         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1116                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1117
1118         return 0;
1119 }
1120
1121 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1122         .detect         = rtl8366rb_detect,
1123         .mii_read       = rtl8366rb_mii_read,
1124         .mii_write      = rtl8366rb_mii_write,
1125
1126         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1127         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1128         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1129         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1130         .get_mc_index   = rtl8366rb_get_mc_index,
1131         .set_mc_index   = rtl8366rb_set_mc_index,
1132         .get_mib_counter = rtl8366rb_get_mib_counter,
1133 };
1134
1135 static int __init rtl8366rb_probe(struct platform_device *pdev)
1136 {
1137         static int rtl8366_smi_version_printed;
1138         struct rtl8366rb_platform_data *pdata;
1139         struct rtl8366rb *rtl;
1140         struct rtl8366_smi *smi;
1141         int err;
1142
1143         if (!rtl8366_smi_version_printed++)
1144                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1145                        " version " RTL8366RB_DRIVER_VER"\n");
1146
1147         pdata = pdev->dev.platform_data;
1148         if (!pdata) {
1149                 dev_err(&pdev->dev, "no platform data specified\n");
1150                 err = -EINVAL;
1151                 goto err_out;
1152         }
1153
1154         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1155         if (!rtl) {
1156                 dev_err(&pdev->dev, "no memory for private data\n");
1157                 err = -ENOMEM;
1158                 goto err_out;
1159         }
1160
1161         rtl->parent = &pdev->dev;
1162
1163         smi = &rtl->smi;
1164         smi->parent = &pdev->dev;
1165         smi->gpio_sda = pdata->gpio_sda;
1166         smi->gpio_sck = pdata->gpio_sck;
1167         smi->ops = &rtl8366rb_smi_ops;
1168         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1169         smi->num_ports = RTL8366RB_NUM_PORTS;
1170         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1171         smi->mib_counters = rtl8366rb_mib_counters;
1172         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1173
1174         err = rtl8366_smi_init(smi);
1175         if (err)
1176                 goto err_free_rtl;
1177
1178         platform_set_drvdata(pdev, rtl);
1179
1180         err = rtl8366rb_setup(rtl);
1181         if (err)
1182                 goto err_clear_drvdata;
1183
1184         err = rtl8366rb_switch_init(rtl);
1185         if (err)
1186                 goto err_clear_drvdata;
1187
1188         return 0;
1189
1190  err_clear_drvdata:
1191         platform_set_drvdata(pdev, NULL);
1192         rtl8366_smi_cleanup(smi);
1193  err_free_rtl:
1194         kfree(rtl);
1195  err_out:
1196         return err;
1197 }
1198
1199 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1200 {
1201         if (!rtl8366rb_mii_bus_match(phydev->bus))
1202                 return -EINVAL;
1203
1204         return 0;
1205 }
1206
1207 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1208 {
1209         return 0;
1210 }
1211
1212 static struct phy_driver rtl8366rb_phy_driver = {
1213         .phy_id         = 0x001cc960,
1214         .name           = "Realtek RTL8366RB",
1215         .phy_id_mask    = 0x1ffffff0,
1216         .features       = PHY_GBIT_FEATURES,
1217         .config_aneg    = rtl8366rb_phy_config_aneg,
1218         .config_init    = rtl8366rb_phy_config_init,
1219         .read_status    = genphy_read_status,
1220         .driver         = {
1221                 .owner = THIS_MODULE,
1222         },
1223 };
1224
1225 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1226 {
1227         struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1228
1229         if (rtl) {
1230                 rtl8366rb_switch_cleanup(rtl);
1231                 platform_set_drvdata(pdev, NULL);
1232                 rtl8366_smi_cleanup(&rtl->smi);
1233                 kfree(rtl);
1234         }
1235
1236         return 0;
1237 }
1238
1239 static struct platform_driver rtl8366rb_driver = {
1240         .driver = {
1241                 .name           = RTL8366RB_DRIVER_NAME,
1242                 .owner          = THIS_MODULE,
1243         },
1244         .probe          = rtl8366rb_probe,
1245         .remove         = __devexit_p(rtl8366rb_remove),
1246 };
1247
1248 static int __init rtl8366rb_module_init(void)
1249 {
1250         int ret;
1251         ret = platform_driver_register(&rtl8366rb_driver);
1252         if (ret)
1253                 return ret;
1254
1255         ret = phy_driver_register(&rtl8366rb_phy_driver);
1256         if (ret)
1257                 goto err_platform_unregister;
1258
1259         return 0;
1260
1261  err_platform_unregister:
1262         platform_driver_unregister(&rtl8366rb_driver);
1263         return ret;
1264 }
1265 module_init(rtl8366rb_module_init);
1266
1267 static void __exit rtl8366rb_module_exit(void)
1268 {
1269         phy_driver_unregister(&rtl8366rb_phy_driver);
1270         platform_driver_unregister(&rtl8366rb_driver);
1271 }
1272 module_exit(rtl8366rb_module_exit);
1273
1274 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1275 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1276 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1277 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1278 MODULE_LICENSE("GPL v2");
1279 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);