target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366rb.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #endif
  26
  27 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  28 #define RTL8366RB_DRIVER_VER    "0.2.2"
  29
  30 #define RTL8366RB_PHY_NO_MAX    4
  31 #define RTL8366RB_PHY_PAGE_MAX  7
  32 #define RTL8366RB_PHY_ADDR_MAX  31
  33
  34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG          0x0000
  35 #define RTL8366RB_CHIP_CTRL_VLAN                (1 << 13)
  36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB           (1 << 14)
  37
  38 /* Switch Global Configuration register */
  39 #define RTL8366RB_SGCR                          0x0000
  40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  41 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  43 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  44 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  45 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  46 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  47
  48 /* Port Enable Control register */
  49 #define RTL8366RB_PECR                          0x0001
  50
  51 /* Switch Security Control registers */
  52 #define RTL8366RB_SSCR0                         0x0002
  53 #define RTL8366RB_SSCR1                         0x0003
  54 #define RTL8366RB_SSCR2                         0x0004
  55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  56
  57 #define RTL8366RB_RESET_CTRL_REG                0x0100
  58 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  59 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  60
  61 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  62 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  63 #define RTL8366RB_CHIP_ID_REG                   0x0509
  64 #define RTL8366RB_CHIP_ID_8366                  0x5937
  65
  66 /* PHY registers control */
  67 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  68 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  69
  70 #define RTL8366RB_PHY_CTRL_READ                 1
  71 #define RTL8366RB_PHY_CTRL_WRITE                0
  72
  73 #define RTL8366RB_PHY_REG_MASK                  0x1f
  74 #define RTL8366RB_PHY_PAGE_OFFSET               5
  75 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  76 #define RTL8366RB_PHY_NO_OFFSET                 9
  77 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  78
  79 /* LED control registers */
  80 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  81 #define RTL8366RB_LED_BLINKRATE_BIT             0
  82 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  83
  84 #define RTL8366RB_LED_CTRL_REG                  0x0431
  85 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  86 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  87
  88 #define RTL8366RB_MIB_COUNT                     33
  89 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  91 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  92 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  93 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  94 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  95 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  98
  99 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
 100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
 101                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 102 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 104
 105
 106 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 108
 109
 110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 111 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 113
 114 #define RTL8366RB_VLAN_MEMCONF_BASE             0x0020
 115
 116
 117 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 118 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 120 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 123 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 124
 125
 126 #define RTL8366RB_PORT_NUM_CPU          5
 127 #define RTL8366RB_NUM_PORTS             6
 128 #define RTL8366RB_NUM_VLANS             16
 129 #define RTL8366RB_NUM_LEDGROUPS         4
 130 #define RTL8366RB_NUM_VIDS              4096
 131 #define RTL8366RB_PRIORITYMAX           7
 132 #define RTL8366RB_FIDMAX                7
 133
 134
 135 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 136 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 137 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 138 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 139 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 140
 141 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 142
 143 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 144                                          RTL8366RB_PORT_2 |     \
 145                                          RTL8366RB_PORT_3 |     \
 146                                          RTL8366RB_PORT_4 |     \
 147                                          RTL8366RB_PORT_5 |     \
 148                                          RTL8366RB_PORT_CPU)
 149
 150 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 151                                          RTL8366RB_PORT_2 |     \
 152                                          RTL8366RB_PORT_3 |     \
 153                                          RTL8366RB_PORT_4 |     \
 154                                          RTL8366RB_PORT_5)
 155
 156 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 157                                          RTL8366RB_PORT_2 |     \
 158                                          RTL8366RB_PORT_3 |     \
 159                                          RTL8366RB_PORT_4)
 160
 161 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 162
 163 struct rtl8366rb {
 164         struct device           *parent;
 165         struct rtl8366_smi      smi;
 166         struct switch_dev       dev;
 167 };
 168
 169 struct rtl8366rb_vlan_mc {
 170         u16     reserved2:1;
 171         u16     priority:3;
 172         u16     vid:12;
 173         u16     untag:8;
 174         u16     member:8;
 175         u16     stag_mbr:8;
 176         u16     stag_idx:3;
 177         u16     reserved1:2;
 178         u16     fid:3;
 179 };
 180
 181 struct rtl8366rb_vlan_4k {
 182         u16     reserved1:4;
 183         u16     vid:12;
 184         u16     untag:8;
 185         u16     member:8;
 186         u16     reserved2:13;
 187         u16     fid:3;
 188 };
 189
 190 struct mib_counter {
 191         unsigned        offset;
 192         unsigned        length;
 193         const char      *name;
 194 };
 195
 196 static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
 197         {  0, 4, "IfInOctets"                           },
 198         {  4, 4, "EtherStatsOctets"                     },
 199         {  8, 2, "EtherStatsUnderSizePkts"              },
 200         { 10, 2, "EtherFragments"                       },
 201         { 12, 2, "EtherStatsPkts64Octets"               },
 202         { 14, 2, "EtherStatsPkts65to127Octets"          },
 203         { 16, 2, "EtherStatsPkts128to255Octets"         },
 204         { 18, 2, "EtherStatsPkts256to511Octets"         },
 205         { 20, 2, "EtherStatsPkts512to1023Octets"        },
 206         { 22, 2, "EtherStatsPkts1024to1518Octets"       },
 207         { 24, 2, "EtherOversizeStats"                   },
 208         { 26, 2, "EtherStatsJabbers"                    },
 209         { 28, 2, "IfInUcastPkts"                        },
 210         { 30, 2, "EtherStatsMulticastPkts"              },
 211         { 32, 2, "EtherStatsBroadcastPkts"              },
 212         { 34, 2, "EtherStatsDropEvents"                 },
 213         { 36, 2, "Dot3StatsFCSErrors"                   },
 214         { 38, 2, "Dot3StatsSymbolErrors"                },
 215         { 40, 2, "Dot3InPauseFrames"                    },
 216         { 42, 2, "Dot3ControlInUnknownOpcodes"          },
 217         { 44, 4, "IfOutOctets"                          },
 218         { 48, 2, "Dot3StatsSingleCollisionFrames"       },
 219         { 50, 2, "Dot3StatMultipleCollisionFrames"      },
 220         { 52, 2, "Dot3sDeferredTransmissions"           },
 221         { 54, 2, "Dot3StatsLateCollisions"              },
 222         { 56, 2, "EtherStatsCollisions"                 },
 223         { 58, 2, "Dot3StatsExcessiveCollisions"         },
 224         { 60, 2, "Dot3OutPauseFrames"                   },
 225         { 62, 2, "Dot1dBasePortDelayExceededDiscards"   },
 226         { 64, 2, "Dot1dTpPortInDiscards"                },
 227         { 66, 2, "IfOutUcastPkts"                       },
 228         { 68, 2, "IfOutMulticastPkts"                   },
 229         { 70, 2, "IfOutBroadcastPkts"                   },
 230 };
 231
 232 #define REG_WR(_smi, _reg, _val)                                        \
 233         do {                                                            \
 234                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 235                 if (err)                                                \
 236                         return err;                                     \
 237         } while (0)
 238
 239 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 240         do {                                                            \
 241                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 242                 if (err)                                                \
 243                         return err;                                     \
 244         } while (0)
 245
 246 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
 247 {
 248         return container_of(smi, struct rtl8366rb, smi);
 249 }
 250
 251 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
 252 {
 253         return container_of(sw, struct rtl8366rb, dev);
 254 }
 255
 256 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 257 {
 258         struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
 259         return &rtl->smi;
 260 }
 261
 262 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 263 {
 264         int timeout = 10;
 265         u32 data;
 266
 267         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 268                               RTL8366RB_CHIP_CTRL_RESET_HW);
 269         do {
 270                 msleep(1);
 271                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 272                         return -EIO;
 273
 274                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 275                         break;
 276         } while (--timeout);
 277
 278         if (!timeout) {
 279                 printk("Timeout waiting for the switch to reset\n");
 280                 return -EIO;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 287 {
 288         int err;
 289
 290         /* set maximum packet length to 1536 bytes */
 291         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 292                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 293
 294         /* enable all ports */
 295         REG_WR(smi, RTL8366RB_PECR, 0);
 296
 297         /* disable learning for all ports */
 298         REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
 299
 300         /* disable auto ageing for all ports */
 301         REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
 302
 303         /* don't drop packets whose DA has not been learned */
 304         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 305
 306         return 0;
 307 }
 308
 309 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 310                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 311 {
 312         u32 reg;
 313         int ret;
 314
 315         if (phy_no > RTL8366RB_PHY_NO_MAX)
 316                 return -EINVAL;
 317
 318         if (page > RTL8366RB_PHY_PAGE_MAX)
 319                 return -EINVAL;
 320
 321         if (addr > RTL8366RB_PHY_ADDR_MAX)
 322                 return -EINVAL;
 323
 324         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 325                                     RTL8366RB_PHY_CTRL_READ);
 326         if (ret)
 327                 return ret;
 328
 329         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 330               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 331               (addr & RTL8366RB_PHY_REG_MASK);
 332
 333         ret = rtl8366_smi_write_reg(smi, reg, 0);
 334         if (ret)
 335                 return ret;
 336
 337         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 338         if (ret)
 339                 return ret;
 340
 341         return 0;
 342 }
 343
 344 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 345                                   u32 phy_no, u32 page, u32 addr, u32 data)
 346 {
 347         u32 reg;
 348         int ret;
 349
 350         if (phy_no > RTL8366RB_PHY_NO_MAX)
 351                 return -EINVAL;
 352
 353         if (page > RTL8366RB_PHY_PAGE_MAX)
 354                 return -EINVAL;
 355
 356         if (addr > RTL8366RB_PHY_ADDR_MAX)
 357                 return -EINVAL;
 358
 359         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 360                                     RTL8366RB_PHY_CTRL_WRITE);
 361         if (ret)
 362                 return ret;
 363
 364         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 365               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 366               (addr & RTL8366RB_PHY_REG_MASK);
 367
 368         ret = rtl8366_smi_write_reg(smi, reg, data);
 369         if (ret)
 370                 return ret;
 371
 372         return 0;
 373 }
 374
 375 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 376                                    int port, unsigned long long *val)
 377 {
 378         int i;
 379         int err;
 380         u32 addr, data;
 381         u64 mibvalue;
 382
 383         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 384                 return -EINVAL;
 385
 386         addr = RTL8366RB_MIB_COUNTER_BASE +
 387                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 388                rtl8366rb_mib_counters[counter].offset;
 389
 390         /*
 391          * Writing access counter address first
 392          * then ASIC will prepare 64bits counter wait for being retrived
 393          */
 394         data = 0; /* writing data will be discard by ASIC */
 395         err = rtl8366_smi_write_reg(smi, addr, data);
 396         if (err)
 397                 return err;
 398
 399         /* read MIB control register */
 400         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 401         if (err)
 402                 return err;
 403
 404         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 405                 return -EBUSY;
 406
 407         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 408                 return -EIO;
 409
 410         mibvalue = 0;
 411         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 412                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 413                 if (err)
 414                         return err;
 415
 416                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 417         }
 418
 419         *val = mibvalue;
 420         return 0;
 421 }
 422
 423 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 424                                  struct rtl8366_vlan_4k *vlan4k)
 425 {
 426         struct rtl8366rb_vlan_4k vlan4k_priv;
 427         int err;
 428         u32 data;
 429         u16 *tableaddr;
 430
 431         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 432         vlan4k_priv.vid = vid;
 433
 434         if (vid >= RTL8366RB_NUM_VIDS)
 435                 return -EINVAL;
 436
 437         tableaddr = (u16 *)&vlan4k_priv;
 438
 439         /* write VID */
 440         data = *tableaddr;
 441         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 442         if (err)
 443                 return err;
 444
 445         /* write table access control word */
 446         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 447                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 448         if (err)
 449                 return err;
 450
 451         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
 452         if (err)
 453                 return err;
 454
 455         *tableaddr = data;
 456         tableaddr++;
 457
 458         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
 459                                    &data);
 460         if (err)
 461                 return err;
 462
 463         *tableaddr = data;
 464         tableaddr++;
 465
 466         err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
 467                                    &data);
 468         if (err)
 469                 return err;
 470         *tableaddr = data;
 471
 472         vlan4k->vid = vid;
 473         vlan4k->untag = vlan4k_priv.untag;
 474         vlan4k->member = vlan4k_priv.member;
 475         vlan4k->fid = vlan4k_priv.fid;
 476
 477         return 0;
 478 }
 479
 480 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 481                                  const struct rtl8366_vlan_4k *vlan4k)
 482 {
 483         struct rtl8366rb_vlan_4k vlan4k_priv;
 484         int err;
 485         u32 data;
 486         u16 *tableaddr;
 487
 488         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 489             vlan4k->member > RTL8366RB_PORT_ALL ||
 490             vlan4k->untag > RTL8366RB_PORT_ALL ||
 491             vlan4k->fid > RTL8366RB_FIDMAX)
 492                 return -EINVAL;
 493
 494         vlan4k_priv.vid = vlan4k->vid;
 495         vlan4k_priv.untag = vlan4k->untag;
 496         vlan4k_priv.member = vlan4k->member;
 497         vlan4k_priv.fid = vlan4k->fid;
 498
 499         tableaddr = (u16 *)&vlan4k_priv;
 500
 501         data = *tableaddr;
 502
 503         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
 504         if (err)
 505                 return err;
 506
 507         tableaddr++;
 508
 509         data = *tableaddr;
 510
 511         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
 512                                     data);
 513         if (err)
 514                 return err;
 515
 516         tableaddr++;
 517
 518         data = *tableaddr;
 519
 520         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
 521                                     data);
 522         if (err)
 523                 return err;
 524
 525         /* write table access control word */
 526         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 527                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 528
 529         return err;
 530 }
 531
 532 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 533                                  struct rtl8366_vlan_mc *vlanmc)
 534 {
 535         struct rtl8366rb_vlan_mc vlanmc_priv;
 536         int err;
 537         u32 addr;
 538         u32 data;
 539         u16 *tableaddr;
 540
 541         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 542
 543         if (index >= RTL8366RB_NUM_VLANS)
 544                 return -EINVAL;
 545
 546         tableaddr = (u16 *)&vlanmc_priv;
 547
 548         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 549         err = rtl8366_smi_read_reg(smi, addr, &data);
 550         if (err)
 551                 return err;
 552
 553         *tableaddr = data;
 554         tableaddr++;
 555
 556         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 557         err = rtl8366_smi_read_reg(smi, addr, &data);
 558         if (err)
 559                 return err;
 560
 561         *tableaddr = data;
 562         tableaddr++;
 563
 564         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 565         err = rtl8366_smi_read_reg(smi, addr, &data);
 566         if (err)
 567                 return err;
 568
 569         *tableaddr = data;
 570
 571         vlanmc->vid = vlanmc_priv.vid;
 572         vlanmc->priority = vlanmc_priv.priority;
 573         vlanmc->untag = vlanmc_priv.untag;
 574         vlanmc->member = vlanmc_priv.member;
 575         vlanmc->fid = vlanmc_priv.fid;
 576
 577         return 0;
 578 }
 579
 580 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 581                                  const struct rtl8366_vlan_mc *vlanmc)
 582 {
 583         struct rtl8366rb_vlan_mc vlanmc_priv;
 584         int err;
 585         u32 addr;
 586         u32 data;
 587         u16 *tableaddr;
 588
 589         if (index >= RTL8366RB_NUM_VLANS ||
 590             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 591             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 592             vlanmc->member > RTL8366RB_PORT_ALL ||
 593             vlanmc->untag > RTL8366RB_PORT_ALL ||
 594             vlanmc->fid > RTL8366RB_FIDMAX)
 595                 return -EINVAL;
 596
 597         vlanmc_priv.vid = vlanmc->vid;
 598         vlanmc_priv.priority = vlanmc->priority;
 599         vlanmc_priv.untag = vlanmc->untag;
 600         vlanmc_priv.member = vlanmc->member;
 601         vlanmc_priv.stag_mbr = 0;
 602         vlanmc_priv.stag_idx = 0;
 603         vlanmc_priv.fid = vlanmc->fid;
 604
 605         addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
 606
 607         tableaddr = (u16 *)&vlanmc_priv;
 608         data = *tableaddr;
 609
 610         err = rtl8366_smi_write_reg(smi, addr, data);
 611         if (err)
 612                 return err;
 613
 614         addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
 615
 616         tableaddr++;
 617         data = *tableaddr;
 618
 619         err = rtl8366_smi_write_reg(smi, addr, data);
 620         if (err)
 621                 return err;
 622
 623         addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
 624
 625         tableaddr++;
 626         data = *tableaddr;
 627
 628         err = rtl8366_smi_write_reg(smi, addr, data);
 629         if (err)
 630                 return err;
 631         return 0;
 632 }
 633
 634 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 635 {
 636         u32 data;
 637         int err;
 638
 639         if (port >= RTL8366RB_NUM_PORTS)
 640                 return -EINVAL;
 641
 642         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 643                                    &data);
 644         if (err)
 645                 return err;
 646
 647         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 648                RTL8366RB_PORT_VLAN_CTRL_MASK;
 649
 650         return 0;
 651
 652 }
 653
 654 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 655 {
 656         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 657                 return -EINVAL;
 658
 659         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 660                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 661                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 662                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 663                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 664 }
 665
 666 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 667 {
 668         return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
 669                                 RTL8366RB_CHIP_CTRL_VLAN,
 670                                 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
 671 }
 672
 673 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 674 {
 675         return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
 676                                 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
 677                                 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
 678 }
 679
 680 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
 681 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
 682                                           char __user *user_buf,
 683                                           size_t count, loff_t *ppos)
 684 {
 685         struct rtl8366_smi *smi = file->private_data;
 686         int i, j, len = 0;
 687         char *buf = smi->buf;
 688
 689         len += snprintf(buf + len, sizeof(smi->buf) - len,
 690                         "%-36s %12s %12s %12s %12s %12s %12s\n",
 691                         "Counter",
 692                         "Port 0", "Port 1", "Port 2",
 693                         "Port 3", "Port 4", "Port 5");
 694
 695         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 696                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
 697                                 rtl8366rb_mib_counters[i].name);
 698                 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
 699                         unsigned long long counter = 0;
 700
 701                         if (!rtl8366_get_mib_counter(smi, i, j, &counter))
 702                                 len += snprintf(buf + len,
 703                                                 sizeof(smi->buf) - len,
 704                                                 "%12llu ", counter);
 705                         else
 706                                 len += snprintf(buf + len,
 707                                                 sizeof(smi->buf) - len,
 708                                                 "%12s ", "error");
 709                 }
 710                 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
 711         }
 712
 713         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 714 }
 715
 716 static const struct file_operations fops_rtl8366rb_mibs = {
 717         .read = rtl8366rb_read_debugfs_mibs,
 718         .open = rtl8366_debugfs_open,
 719         .owner = THIS_MODULE
 720 };
 721
 722 static void rtl8366rb_debugfs_init(struct rtl8366_smi *smi)
 723 {
 724         struct dentry *node;
 725
 726         if (!smi->debugfs_root)
 727                 return;
 728
 729         node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
 730                                    &fops_rtl8366rb_mibs);
 731         if (!node)
 732                 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
 733                         "mibs");
 734 }
 735
 736 #else
 737 static inline void rtl8366rb_debugfs_init(struct rtl8366_smi *smi) {}
 738 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
 739
 740 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 741                                   const struct switch_attr *attr,
 742                                   struct switch_val *val)
 743 {
 744         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 745         int err = 0;
 746
 747         if (val->value.i == 1)
 748                 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 749                                        RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 750
 751         return err;
 752 }
 753
 754 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
 755                                        const struct switch_attr *attr,
 756                                        struct switch_val *val)
 757 {
 758         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 759         u32 data;
 760
 761         if (attr->ofs == 1) {
 762                 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
 763
 764                 if (data & RTL8366RB_CHIP_CTRL_VLAN)
 765                         val->value.i = 1;
 766                 else
 767                         val->value.i = 0;
 768         } else if (attr->ofs == 2) {
 769                 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
 770
 771                 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
 772                         val->value.i = 1;
 773                 else
 774                         val->value.i = 0;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 781                                      const struct switch_attr *attr,
 782                                      struct switch_val *val)
 783 {
 784         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 785         u32 data;
 786
 787         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 788
 789         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 790
 791         return 0;
 792 }
 793
 794 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 795                                     const struct switch_attr *attr,
 796                                     struct switch_val *val)
 797 {
 798         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 799
 800         if (val->value.i >= 6)
 801                 return -EINVAL;
 802
 803         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 804                                 RTL8366RB_LED_BLINKRATE_MASK,
 805                                 val->value.i);
 806 }
 807
 808 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
 809                                        const struct switch_attr *attr,
 810                                        struct switch_val *val)
 811 {
 812         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 813
 814         if (attr->ofs == 1)
 815                 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
 816         else
 817                 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
 818 }
 819
 820 static const char *rtl8366rb_speed_str(unsigned speed)
 821 {
 822         switch (speed) {
 823         case 0:
 824                 return "10baseT";
 825         case 1:
 826                 return "100baseT";
 827         case 2:
 828                 return "1000baseT";
 829         }
 830
 831         return "unknown";
 832 }
 833
 834 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 835                                      const struct switch_attr *attr,
 836                                      struct switch_val *val)
 837 {
 838         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 839         u32 len = 0, data = 0;
 840
 841         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 842                 return -EINVAL;
 843
 844         memset(smi->buf, '\0', sizeof(smi->buf));
 845         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 846                              (val->port_vlan / 2), &data);
 847
 848         if (val->port_vlan % 2)
 849                 data = data >> 8;
 850
 851         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 852                 len = snprintf(smi->buf, sizeof(smi->buf),
 853                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 854                                 val->port_vlan,
 855                                 rtl8366rb_speed_str(data &
 856                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 857                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 858                                         "full" : "half",
 859                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 860                                         "tx-pause ": "",
 861                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 862                                         "rx-pause " : "",
 863                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 864                                         "nway ": "");
 865         } else {
 866                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 867                                 val->port_vlan);
 868         }
 869
 870         val->value.s = smi->buf;
 871         val->len = len;
 872
 873         return 0;
 874 }
 875
 876 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
 877                                      const struct switch_attr *attr,
 878                                      struct switch_val *val)
 879 {
 880         int i;
 881         u32 len = 0;
 882         struct rtl8366_vlan_4k vlan4k;
 883         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 884         char *buf = smi->buf;
 885         int err;
 886
 887         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 888                 return -EINVAL;
 889
 890         memset(buf, '\0', sizeof(smi->buf));
 891
 892         err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 893         if (err)
 894                 return err;
 895
 896         len += snprintf(buf + len, sizeof(smi->buf) - len,
 897                         "VLAN %d: Ports: '", vlan4k.vid);
 898
 899         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 900                 if (!(vlan4k.member & (1 << i)))
 901                         continue;
 902
 903                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 904                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 905         }
 906
 907         len += snprintf(buf + len, sizeof(smi->buf) - len,
 908                         "', members=%04x, untag=%04x, fid=%u",
 909                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 910
 911         val->value.s = buf;
 912         val->len = len;
 913
 914         return 0;
 915 }
 916
 917 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 918                                     const struct switch_attr *attr,
 919                                     struct switch_val *val)
 920 {
 921         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 922         u32 data;
 923         u32 mask;
 924         u32 reg;
 925
 926         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 927                 return -EINVAL;
 928
 929         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 930                 reg = RTL8366RB_LED_BLINKRATE_REG;
 931                 mask = 0xF << 4;
 932                 data = val->value.i << 4;
 933         } else {
 934                 reg = RTL8366RB_LED_CTRL_REG;
 935                 mask = 0xF << (val->port_vlan * 4),
 936                 data = val->value.i << (val->port_vlan * 4);
 937         }
 938
 939         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
 940 }
 941
 942 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 943                                     const struct switch_attr *attr,
 944                                     struct switch_val *val)
 945 {
 946         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 947         u32 data = 0;
 948
 949         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 950                 return -EINVAL;
 951
 952         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 953         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 954
 955         return 0;
 956 }
 957
 958 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 959                                        const struct switch_attr *attr,
 960                                        struct switch_val *val)
 961 {
 962         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 963
 964         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 965                 return -EINVAL;
 966
 967         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 968                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 969 }
 970
 971 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
 972                                     const struct switch_attr *attr,
 973                                     struct switch_val *val)
 974 {
 975         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 976         int i, len = 0;
 977         unsigned long long counter = 0;
 978         char *buf = smi->buf;
 979
 980         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 981                 return -EINVAL;
 982
 983         len += snprintf(buf + len, sizeof(smi->buf) - len,
 984                         "Port %d MIB counters\n",
 985                         val->port_vlan);
 986
 987         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 988                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 989                                 "%-36s: ", rtl8366rb_mib_counters[i].name);
 990                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 991                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 992                                         "%llu\n", counter);
 993                 else
 994                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 995                                         "%s\n", "error");
 996         }
 997
 998         val->value.s = buf;
 999         val->len = len;
1000         return 0;
1001 }
1002
1003 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1004                                       struct switch_val *val)
1005 {
1006         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1007         struct switch_port *port;
1008         struct rtl8366_vlan_4k vlan4k;
1009         int i;
1010
1011         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1012                 return -EINVAL;
1013
1014         rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1015
1016         port = &val->value.ports[0];
1017         val->len = 0;
1018         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1019                 if (!(vlan4k.member & BIT(i)))
1020                         continue;
1021
1022                 port->id = i;
1023                 port->flags = (vlan4k.untag & BIT(i)) ?
1024                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1025                 val->len++;
1026                 port++;
1027         }
1028         return 0;
1029 }
1030
1031 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1032                                       struct switch_val *val)
1033 {
1034         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1035         struct switch_port *port;
1036         u32 member = 0;
1037         u32 untag = 0;
1038         int i;
1039
1040         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1041                 return -EINVAL;
1042
1043         port = &val->value.ports[0];
1044         for (i = 0; i < val->len; i++, port++) {
1045                 member |= BIT(port->id);
1046
1047                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1048                         untag |= BIT(port->id);
1049         }
1050
1051         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1052 }
1053
1054 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1055 {
1056         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1057         return rtl8366_get_pvid(smi, port, val);
1058 }
1059
1060 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1061 {
1062         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1063         return rtl8366_set_pvid(smi, port, val);
1064 }
1065
1066 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1067 {
1068         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1069         int err;
1070
1071         err = rtl8366rb_reset_chip(smi);
1072         if (err)
1073                 return err;
1074
1075         err = rtl8366rb_hw_init(smi);
1076         if (err)
1077                 return err;
1078
1079         return rtl8366_reset_vlan(smi);
1080 }
1081
1082 static struct switch_attr rtl8366rb_globals[] = {
1083         {
1084                 .type = SWITCH_TYPE_INT,
1085                 .name = "enable_vlan",
1086                 .description = "Enable VLAN mode",
1087                 .set = rtl8366rb_sw_set_vlan_enable,
1088                 .get = rtl8366rb_sw_get_vlan_enable,
1089                 .max = 1,
1090                 .ofs = 1
1091         }, {
1092                 .type = SWITCH_TYPE_INT,
1093                 .name = "enable_vlan4k",
1094                 .description = "Enable VLAN 4K mode",
1095                 .set = rtl8366rb_sw_set_vlan_enable,
1096                 .get = rtl8366rb_sw_get_vlan_enable,
1097                 .max = 1,
1098                 .ofs = 2
1099         }, {
1100                 .type = SWITCH_TYPE_INT,
1101                 .name = "reset_mibs",
1102                 .description = "Reset all MIB counters",
1103                 .set = rtl8366rb_sw_reset_mibs,
1104                 .get = NULL,
1105                 .max = 1
1106         }, {
1107                 .type = SWITCH_TYPE_INT,
1108                 .name = "blinkrate",
1109                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1110                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1111                 .set = rtl8366rb_sw_set_blinkrate,
1112                 .get = rtl8366rb_sw_get_blinkrate,
1113                 .max = 5
1114         },
1115 };
1116
1117 static struct switch_attr rtl8366rb_port[] = {
1118         {
1119                 .type = SWITCH_TYPE_STRING,
1120                 .name = "link",
1121                 .description = "Get port link information",
1122                 .max = 1,
1123                 .set = NULL,
1124                 .get = rtl8366rb_sw_get_port_link,
1125         }, {
1126                 .type = SWITCH_TYPE_INT,
1127                 .name = "reset_mib",
1128                 .description = "Reset single port MIB counters",
1129                 .max = 1,
1130                 .set = rtl8366rb_sw_reset_port_mibs,
1131                 .get = NULL,
1132         }, {
1133                 .type = SWITCH_TYPE_STRING,
1134                 .name = "mib",
1135                 .description = "Get MIB counters for port",
1136                 .max = 33,
1137                 .set = NULL,
1138                 .get = rtl8366rb_sw_get_port_mib,
1139         }, {
1140                 .type = SWITCH_TYPE_INT,
1141                 .name = "led",
1142                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1143                 .max = 15,
1144                 .set = rtl8366rb_sw_set_port_led,
1145                 .get = rtl8366rb_sw_get_port_led,
1146         },
1147 };
1148
1149 static struct switch_attr rtl8366rb_vlan[] = {
1150         {
1151                 .type = SWITCH_TYPE_STRING,
1152                 .name = "info",
1153                 .description = "Get vlan information",
1154                 .max = 1,
1155                 .set = NULL,
1156                 .get = rtl8366rb_sw_get_vlan_info,
1157         },
1158 };
1159
1160 /* template */
1161 static struct switch_dev rtl8366_switch_dev = {
1162         .name = "RTL8366S",
1163         .cpu_port = RTL8366RB_PORT_NUM_CPU,
1164         .ports = RTL8366RB_NUM_PORTS,
1165         .vlans = RTL8366RB_NUM_VLANS,
1166         .attr_global = {
1167                 .attr = rtl8366rb_globals,
1168                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1169         },
1170         .attr_port = {
1171                 .attr = rtl8366rb_port,
1172                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1173         },
1174         .attr_vlan = {
1175                 .attr = rtl8366rb_vlan,
1176                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1177         },
1178
1179         .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1180         .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1181         .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1182         .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1183         .reset_switch = rtl8366rb_sw_reset_switch,
1184 };
1185
1186 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1187 {
1188         struct switch_dev *dev = &rtl->dev;
1189         int err;
1190
1191         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1192         dev->priv = rtl;
1193         dev->devname = dev_name(rtl->parent);
1194
1195         err = register_switch(dev, NULL);
1196         if (err)
1197                 dev_err(rtl->parent, "switch registration failed\n");
1198
1199         return err;
1200 }
1201
1202 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1203 {
1204         unregister_switch(&rtl->dev);
1205 }
1206
1207 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1208 {
1209         struct rtl8366_smi *smi = bus->priv;
1210         u32 val = 0;
1211         int err;
1212
1213         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1214         if (err)
1215                 return 0xffff;
1216
1217         return val;
1218 }
1219
1220 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1221 {
1222         struct rtl8366_smi *smi = bus->priv;
1223         u32 t;
1224         int err;
1225
1226         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1227         /* flush write */
1228         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1229
1230         return err;
1231 }
1232
1233 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1234 {
1235         return (bus->read == rtl8366rb_mii_read &&
1236                 bus->write == rtl8366rb_mii_write);
1237 }
1238
1239 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1240 {
1241         struct rtl8366_smi *smi = &rtl->smi;
1242         int ret;
1243
1244         rtl8366rb_debugfs_init(smi);
1245
1246         ret = rtl8366rb_reset_chip(smi);
1247         if (ret)
1248                 return ret;
1249
1250         ret = rtl8366rb_hw_init(smi);
1251         return ret;
1252 }
1253
1254 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1255 {
1256         u32 chip_id = 0;
1257         u32 chip_ver = 0;
1258         int ret;
1259
1260         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1261         if (ret) {
1262                 dev_err(smi->parent, "unable to read chip id\n");
1263                 return ret;
1264         }
1265
1266         switch (chip_id) {
1267         case RTL8366RB_CHIP_ID_8366:
1268                 break;
1269         default:
1270                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1271                 return -ENODEV;
1272         }
1273
1274         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1275                                    &chip_ver);
1276         if (ret) {
1277                 dev_err(smi->parent, "unable to read chip version\n");
1278                 return ret;
1279         }
1280
1281         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1282                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1283
1284         return 0;
1285 }
1286
1287 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1288         .detect         = rtl8366rb_detect,
1289         .mii_read       = rtl8366rb_mii_read,
1290         .mii_write      = rtl8366rb_mii_write,
1291
1292         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1293         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1294         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1295         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1296         .get_mc_index   = rtl8366rb_get_mc_index,
1297         .set_mc_index   = rtl8366rb_set_mc_index,
1298 };
1299
1300 static int __init rtl8366rb_probe(struct platform_device *pdev)
1301 {
1302         static int rtl8366_smi_version_printed;
1303         struct rtl8366rb_platform_data *pdata;
1304         struct rtl8366rb *rtl;
1305         struct rtl8366_smi *smi;
1306         int err;
1307
1308         if (!rtl8366_smi_version_printed++)
1309                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1310                        " version " RTL8366RB_DRIVER_VER"\n");
1311
1312         pdata = pdev->dev.platform_data;
1313         if (!pdata) {
1314                 dev_err(&pdev->dev, "no platform data specified\n");
1315                 err = -EINVAL;
1316                 goto err_out;
1317         }
1318
1319         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1320         if (!rtl) {
1321                 dev_err(&pdev->dev, "no memory for private data\n");
1322                 err = -ENOMEM;
1323                 goto err_out;
1324         }
1325
1326         rtl->parent = &pdev->dev;
1327
1328         smi = &rtl->smi;
1329         smi->parent = &pdev->dev;
1330         smi->gpio_sda = pdata->gpio_sda;
1331         smi->gpio_sck = pdata->gpio_sck;
1332         smi->ops = &rtl8366rb_smi_ops;
1333         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1334         smi->num_ports = RTL8366RB_NUM_PORTS;
1335         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1336
1337         err = rtl8366_smi_init(smi);
1338         if (err)
1339                 goto err_free_rtl;
1340
1341         platform_set_drvdata(pdev, rtl);
1342
1343         err = rtl8366rb_setup(rtl);
1344         if (err)
1345                 goto err_clear_drvdata;
1346
1347         err = rtl8366rb_switch_init(rtl);
1348         if (err)
1349                 goto err_clear_drvdata;
1350
1351         return 0;
1352
1353  err_clear_drvdata:
1354         platform_set_drvdata(pdev, NULL);
1355         rtl8366_smi_cleanup(smi);
1356  err_free_rtl:
1357         kfree(rtl);
1358  err_out:
1359         return err;
1360 }
1361
1362 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1363 {
1364         if (!rtl8366rb_mii_bus_match(phydev->bus))
1365                 return -EINVAL;
1366
1367         return 0;
1368 }
1369
1370 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1371 {
1372         return 0;
1373 }
1374
1375 static struct phy_driver rtl8366rb_phy_driver = {
1376         .phy_id         = 0x001cc960,
1377         .name           = "Realtek RTL8366RB",
1378         .phy_id_mask    = 0x1ffffff0,
1379         .features       = PHY_GBIT_FEATURES,
1380         .config_aneg    = rtl8366rb_phy_config_aneg,
1381         .config_init    = rtl8366rb_phy_config_init,
1382         .read_status    = genphy_read_status,
1383         .driver         = {
1384                 .owner = THIS_MODULE,
1385         },
1386 };
1387
1388 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1389 {
1390         struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1391
1392         if (rtl) {
1393                 rtl8366rb_switch_cleanup(rtl);
1394                 platform_set_drvdata(pdev, NULL);
1395                 rtl8366_smi_cleanup(&rtl->smi);
1396                 kfree(rtl);
1397         }
1398
1399         return 0;
1400 }
1401
1402 static struct platform_driver rtl8366rb_driver = {
1403         .driver = {
1404                 .name           = RTL8366RB_DRIVER_NAME,
1405                 .owner          = THIS_MODULE,
1406         },
1407         .probe          = rtl8366rb_probe,
1408         .remove         = __devexit_p(rtl8366rb_remove),
1409 };
1410
1411 static int __init rtl8366rb_module_init(void)
1412 {
1413         int ret;
1414         ret = platform_driver_register(&rtl8366rb_driver);
1415         if (ret)
1416                 return ret;
1417
1418         ret = phy_driver_register(&rtl8366rb_phy_driver);
1419         if (ret)
1420                 goto err_platform_unregister;
1421
1422         return 0;
1423
1424  err_platform_unregister:
1425         platform_driver_unregister(&rtl8366rb_driver);
1426         return ret;
1427 }
1428 module_init(rtl8366rb_module_init);
1429
1430 static void __exit rtl8366rb_module_exit(void)
1431 {
1432         phy_driver_unregister(&rtl8366rb_phy_driver);
1433         platform_driver_unregister(&rtl8366rb_driver);
1434 }
1435 module_exit(rtl8366rb_module_exit);
1436
1437 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1438 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1439 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1440 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1441 MODULE_LICENSE("GPL v2");
1442 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);