2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
21 #include "rtl8366_smi.h"
23 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
24 #define RTL8366S_DRIVER_VER "0.2.2"
26 #define RTL8366S_PHY_NO_MAX 4
27 #define RTL8366S_PHY_PAGE_MAX 7
28 #define RTL8366S_PHY_ADDR_MAX 31
30 /* Switch Global Configuration register */
31 #define RTL8366S_SGCR 0x0000
32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366S_SGCR_EN_VLAN BIT(13)
41 /* Port Enable Control register */
42 #define RTL8366S_PECR 0x0001
44 /* Switch Security Control registers */
45 #define RTL8366S_SSCR0 0x0002
46 #define RTL8366S_SSCR1 0x0003
47 #define RTL8366S_SSCR2 0x0004
48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
50 #define RTL8366S_RESET_CTRL_REG 0x0100
51 #define RTL8366S_CHIP_CTRL_RESET_HW 1
52 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
54 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55 #define RTL8366S_CHIP_VERSION_MASK 0xf
56 #define RTL8366S_CHIP_ID_REG 0x0105
57 #define RTL8366S_CHIP_ID_8366 0x8366
59 /* PHY registers control */
60 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
63 #define RTL8366S_PHY_CTRL_READ 1
64 #define RTL8366S_PHY_CTRL_WRITE 0
66 #define RTL8366S_PHY_REG_MASK 0x1f
67 #define RTL8366S_PHY_PAGE_OFFSET 5
68 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69 #define RTL8366S_PHY_NO_OFFSET 9
70 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
72 /* LED control registers */
73 #define RTL8366S_LED_BLINKRATE_REG 0x0420
74 #define RTL8366S_LED_BLINKRATE_BIT 0
75 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
77 #define RTL8366S_LED_CTRL_REG 0x0421
78 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
79 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
81 #define RTL8366S_MIB_COUNT 33
82 #define RTL8366S_GLOBAL_MIB_COUNT 1
83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84 #define RTL8366S_MIB_COUNTER_BASE 0x1000
85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
87 #define RTL8366S_MIB_CTRL_REG 0x11F0
88 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
97 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
107 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
109 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
113 #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
115 #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
117 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
118 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
126 #define RTL8366S_PORT_NUM_CPU 5
127 #define RTL8366S_NUM_PORTS 6
128 #define RTL8366S_NUM_VLANS 16
129 #define RTL8366S_NUM_LEDGROUPS 4
130 #define RTL8366S_NUM_VIDS 4096
131 #define RTL8366S_PRIORITYMAX 7
132 #define RTL8366S_FIDMAX 7
135 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
140 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
141 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
143 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
147 RTL8366S_PORT_UNKNOWN | \
150 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
154 RTL8366S_PORT_UNKNOWN)
156 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
161 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
164 #define RTL8366S_VLAN_VID_MASK 0xfff
165 #define RTL8366S_VLAN_PRIORITY_SHIFT 12
166 #define RTL8366S_VLAN_PRIORITY_MASK 0x7
167 #define RTL8366S_VLAN_MEMBER_MASK 0x3f
168 #define RTL8366S_VLAN_UNTAG_SHIFT 6
169 #define RTL8366S_VLAN_UNTAG_MASK 0x3f
170 #define RTL8366S_VLAN_FID_SHIFT 12
171 #define RTL8366S_VLAN_FID_MASK 0x7
174 struct device *parent;
175 struct rtl8366_smi smi;
176 struct switch_dev dev;
179 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
180 { 0, 0, 4, "IfInOctets" },
181 { 0, 4, 4, "EtherStatsOctets" },
182 { 0, 8, 2, "EtherStatsUnderSizePkts" },
183 { 0, 10, 2, "EtherFragments" },
184 { 0, 12, 2, "EtherStatsPkts64Octets" },
185 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
186 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
187 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
188 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
189 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
190 { 0, 24, 2, "EtherOversizeStats" },
191 { 0, 26, 2, "EtherStatsJabbers" },
192 { 0, 28, 2, "IfInUcastPkts" },
193 { 0, 30, 2, "EtherStatsMulticastPkts" },
194 { 0, 32, 2, "EtherStatsBroadcastPkts" },
195 { 0, 34, 2, "EtherStatsDropEvents" },
196 { 0, 36, 2, "Dot3StatsFCSErrors" },
197 { 0, 38, 2, "Dot3StatsSymbolErrors" },
198 { 0, 40, 2, "Dot3InPauseFrames" },
199 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
200 { 0, 44, 4, "IfOutOctets" },
201 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
202 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
203 { 0, 52, 2, "Dot3sDeferredTransmissions" },
204 { 0, 54, 2, "Dot3StatsLateCollisions" },
205 { 0, 56, 2, "EtherStatsCollisions" },
206 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
207 { 0, 60, 2, "Dot3OutPauseFrames" },
208 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
211 * The following counters are accessible at a different
214 { 1, 0, 2, "Dot1dTpPortInDiscards" },
215 { 1, 2, 2, "IfOutUcastPkts" },
216 { 1, 4, 2, "IfOutMulticastPkts" },
217 { 1, 6, 2, "IfOutBroadcastPkts" },
220 #define REG_WR(_smi, _reg, _val) \
222 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
227 #define REG_RMW(_smi, _reg, _mask, _val) \
229 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
234 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
236 return container_of(smi, struct rtl8366s, smi);
239 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
241 return container_of(sw, struct rtl8366s, dev);
244 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
246 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
250 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
255 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
256 RTL8366S_CHIP_CTRL_RESET_HW);
259 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
262 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
267 printk("Timeout waiting for the switch to reset\n");
274 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
278 /* set maximum packet length to 1536 bytes */
279 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
280 RTL8366S_SGCR_MAX_LENGTH_1536);
282 /* enable all ports */
283 REG_WR(smi, RTL8366S_PECR, 0);
285 /* disable learning for all ports */
286 REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
288 /* disable auto ageing for all ports */
289 REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
292 * discard VLAN tagged packets if the port is not a member of
293 * the VLAN with which the packets is associated.
295 REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
297 /* don't drop packets whose DA has not been learned */
298 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
303 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
304 u32 phy_no, u32 page, u32 addr, u32 *data)
309 if (phy_no > RTL8366S_PHY_NO_MAX)
312 if (page > RTL8366S_PHY_PAGE_MAX)
315 if (addr > RTL8366S_PHY_ADDR_MAX)
318 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
319 RTL8366S_PHY_CTRL_READ);
323 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
324 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
325 (addr & RTL8366S_PHY_REG_MASK);
327 ret = rtl8366_smi_write_reg(smi, reg, 0);
331 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
338 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
339 u32 phy_no, u32 page, u32 addr, u32 data)
344 if (phy_no > RTL8366S_PHY_NO_MAX)
347 if (page > RTL8366S_PHY_PAGE_MAX)
350 if (addr > RTL8366S_PHY_ADDR_MAX)
353 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
354 RTL8366S_PHY_CTRL_WRITE);
358 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
359 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
360 (addr & RTL8366S_PHY_REG_MASK);
362 ret = rtl8366_smi_write_reg(smi, reg, data);
369 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
370 int port, unsigned long long *val)
377 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
380 switch (rtl8366s_mib_counters[counter].base) {
382 addr = RTL8366S_MIB_COUNTER_BASE +
383 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
387 addr = RTL8366S_MIB_COUNTER_BASE2 +
388 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
395 addr += rtl8366s_mib_counters[counter].offset;
398 * Writing access counter address first
399 * then ASIC will prepare 64bits counter wait for being retrived
401 data = 0; /* writing data will be discard by ASIC */
402 err = rtl8366_smi_write_reg(smi, addr, data);
406 /* read MIB control register */
407 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
411 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
414 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
418 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
419 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
423 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
430 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
431 struct rtl8366_vlan_4k *vlan4k)
437 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
439 if (vid >= RTL8366S_NUM_VIDS)
443 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
444 vid & RTL8366S_VLAN_VID_MASK);
448 /* write table access control word */
449 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
450 RTL8366S_TABLE_VLAN_READ_CTRL);
454 for (i = 0; i < 2; i++) {
455 err = rtl8366_smi_read_reg(smi,
456 RTL8366S_VLAN_TABLE_READ_BASE + i,
463 vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
464 RTL8366S_VLAN_UNTAG_MASK;
465 vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
466 vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
467 RTL8366S_VLAN_FID_MASK;
472 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
473 const struct rtl8366_vlan_4k *vlan4k)
479 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
480 vlan4k->member > RTL8366S_PORT_ALL ||
481 vlan4k->untag > RTL8366S_PORT_ALL ||
482 vlan4k->fid > RTL8366S_FIDMAX)
485 data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
486 data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
487 ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
488 RTL8366S_VLAN_UNTAG_SHIFT) |
489 ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
490 RTL8366S_VLAN_FID_SHIFT);
492 for (i = 0; i < 2; i++) {
493 err = rtl8366_smi_write_reg(smi,
494 RTL8366S_VLAN_TABLE_WRITE_BASE + i,
500 /* write table access control word */
501 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
502 RTL8366S_TABLE_VLAN_WRITE_CTRL);
507 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
508 struct rtl8366_vlan_mc *vlanmc)
514 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
516 if (index >= RTL8366S_NUM_VLANS)
519 for (i = 0; i < 2; i++) {
520 err = rtl8366_smi_read_reg(smi,
521 RTL8366S_VLAN_MC_BASE(index) + i,
527 vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
528 vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
529 RTL8366S_VLAN_PRIORITY_MASK;
530 vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
531 RTL8366S_VLAN_UNTAG_MASK;
532 vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
533 vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
534 RTL8366S_VLAN_FID_MASK;
539 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
540 const struct rtl8366_vlan_mc *vlanmc)
546 if (index >= RTL8366S_NUM_VLANS ||
547 vlanmc->vid >= RTL8366S_NUM_VIDS ||
548 vlanmc->priority > RTL8366S_PRIORITYMAX ||
549 vlanmc->member > RTL8366S_PORT_ALL ||
550 vlanmc->untag > RTL8366S_PORT_ALL ||
551 vlanmc->fid > RTL8366S_FIDMAX)
554 data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
555 ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
556 RTL8366S_VLAN_PRIORITY_SHIFT);
557 data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
558 ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
559 RTL8366S_VLAN_UNTAG_SHIFT) |
560 ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
561 RTL8366S_VLAN_FID_SHIFT);
563 for (i = 0; i < 2; i++) {
564 err = rtl8366_smi_write_reg(smi,
565 RTL8366S_VLAN_MC_BASE(index) + i,
574 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
579 if (port >= RTL8366S_NUM_PORTS)
582 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
587 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
588 RTL8366S_PORT_VLAN_CTRL_MASK;
593 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
595 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
598 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
599 RTL8366S_PORT_VLAN_CTRL_MASK <<
600 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
601 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
602 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
605 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
607 return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
608 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
611 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
613 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
614 1, (enable) ? 1 : 0);
617 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
618 const struct switch_attr *attr,
619 struct switch_val *val)
621 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
623 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
626 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val)
630 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
633 if (attr->ofs == 1) {
634 rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
636 if (data & RTL8366S_SGCR_EN_VLAN)
640 } else if (attr->ofs == 2) {
641 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
652 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
653 const struct switch_attr *attr,
654 struct switch_val *val)
656 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
659 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
661 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
666 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
667 const struct switch_attr *attr,
668 struct switch_val *val)
670 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
672 if (val->value.i >= 6)
675 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
676 RTL8366S_LED_BLINKRATE_MASK,
680 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
681 const struct switch_attr *attr,
682 struct switch_val *val)
684 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
687 return rtl8366s_vlan_set_vlan(smi, val->value.i);
689 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
692 static const char *rtl8366s_speed_str(unsigned speed)
706 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
707 const struct switch_attr *attr,
708 struct switch_val *val)
710 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
711 u32 len = 0, data = 0;
713 if (val->port_vlan >= RTL8366S_NUM_PORTS)
716 memset(smi->buf, '\0', sizeof(smi->buf));
717 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
718 (val->port_vlan / 2), &data);
720 if (val->port_vlan % 2)
723 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
724 len = snprintf(smi->buf, sizeof(smi->buf),
725 "port:%d link:up speed:%s %s-duplex %s%s%s",
727 rtl8366s_speed_str(data &
728 RTL8366S_PORT_STATUS_SPEED_MASK),
729 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
731 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
733 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
735 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
738 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
742 val->value.s = smi->buf;
748 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
749 const struct switch_attr *attr,
750 struct switch_val *val)
754 struct rtl8366_vlan_4k vlan4k;
755 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
756 char *buf = smi->buf;
759 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
762 memset(buf, '\0', sizeof(smi->buf));
764 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
768 len += snprintf(buf + len, sizeof(smi->buf) - len,
769 "VLAN %d: Ports: '", vlan4k.vid);
771 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
772 if (!(vlan4k.member & (1 << i)))
775 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
776 (vlan4k.untag & (1 << i)) ? "" : "t");
779 len += snprintf(buf + len, sizeof(smi->buf) - len,
780 "', members=%04x, untag=%04x, fid=%u",
781 vlan4k.member, vlan4k.untag, vlan4k.fid);
789 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
790 const struct switch_attr *attr,
791 struct switch_val *val)
793 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
798 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
799 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
802 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
803 reg = RTL8366S_LED_BLINKRATE_REG;
805 data = val->value.i << 4;
807 reg = RTL8366S_LED_CTRL_REG;
808 mask = 0xF << (val->port_vlan * 4),
809 data = val->value.i << (val->port_vlan * 4);
812 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
815 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
816 const struct switch_attr *attr,
817 struct switch_val *val)
819 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
822 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
825 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
826 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
831 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
832 const struct switch_attr *attr,
833 struct switch_val *val)
835 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
837 if (val->port_vlan >= RTL8366S_NUM_PORTS)
841 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
842 0, (1 << (val->port_vlan + 3)));
845 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
846 const struct switch_attr *attr,
847 struct switch_val *val)
849 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
851 unsigned long long counter = 0;
852 char *buf = smi->buf;
854 if (val->port_vlan >= RTL8366S_NUM_PORTS)
857 len += snprintf(buf + len, sizeof(smi->buf) - len,
858 "Port %d MIB counters\n",
861 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
862 len += snprintf(buf + len, sizeof(smi->buf) - len,
863 "%-36s: ", rtl8366s_mib_counters[i].name);
864 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
865 len += snprintf(buf + len, sizeof(smi->buf) - len,
868 len += snprintf(buf + len, sizeof(smi->buf) - len,
877 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
878 struct switch_val *val)
880 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
881 struct switch_port *port;
882 struct rtl8366_vlan_4k vlan4k;
885 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
888 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
890 port = &val->value.ports[0];
892 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
893 if (!(vlan4k.member & BIT(i)))
897 port->flags = (vlan4k.untag & BIT(i)) ?
898 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
905 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
906 struct switch_val *val)
908 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
909 struct switch_port *port;
914 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
917 port = &val->value.ports[0];
918 for (i = 0; i < val->len; i++, port++) {
919 member |= BIT(port->id);
921 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
922 untag |= BIT(port->id);
925 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
928 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
930 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
931 return rtl8366_get_pvid(smi, port, val);
934 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
936 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
937 return rtl8366_set_pvid(smi, port, val);
940 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
942 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
945 err = rtl8366s_reset_chip(smi);
949 err = rtl8366s_hw_init(smi);
953 return rtl8366_reset_vlan(smi);
956 static struct switch_attr rtl8366s_globals[] = {
958 .type = SWITCH_TYPE_INT,
959 .name = "enable_vlan",
960 .description = "Enable VLAN mode",
961 .set = rtl8366s_sw_set_vlan_enable,
962 .get = rtl8366s_sw_get_vlan_enable,
966 .type = SWITCH_TYPE_INT,
967 .name = "enable_vlan4k",
968 .description = "Enable VLAN 4K mode",
969 .set = rtl8366s_sw_set_vlan_enable,
970 .get = rtl8366s_sw_get_vlan_enable,
974 .type = SWITCH_TYPE_NOVAL,
975 .name = "reset_mibs",
976 .description = "Reset all MIB counters",
977 .set = rtl8366s_sw_reset_mibs,
979 .type = SWITCH_TYPE_INT,
981 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
982 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
983 .set = rtl8366s_sw_set_blinkrate,
984 .get = rtl8366s_sw_get_blinkrate,
989 static struct switch_attr rtl8366s_port[] = {
991 .type = SWITCH_TYPE_STRING,
993 .description = "Get port link information",
996 .get = rtl8366s_sw_get_port_link,
998 .type = SWITCH_TYPE_NOVAL,
1000 .description = "Reset single port MIB counters",
1001 .set = rtl8366s_sw_reset_port_mibs,
1003 .type = SWITCH_TYPE_STRING,
1005 .description = "Get MIB counters for port",
1008 .get = rtl8366s_sw_get_port_mib,
1010 .type = SWITCH_TYPE_INT,
1012 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1014 .set = rtl8366s_sw_set_port_led,
1015 .get = rtl8366s_sw_get_port_led,
1019 static struct switch_attr rtl8366s_vlan[] = {
1021 .type = SWITCH_TYPE_STRING,
1023 .description = "Get vlan information",
1026 .get = rtl8366s_sw_get_vlan_info,
1031 static struct switch_dev rtl8366_switch_dev = {
1033 .cpu_port = RTL8366S_PORT_NUM_CPU,
1034 .ports = RTL8366S_NUM_PORTS,
1035 .vlans = RTL8366S_NUM_VLANS,
1037 .attr = rtl8366s_globals,
1038 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1041 .attr = rtl8366s_port,
1042 .n_attr = ARRAY_SIZE(rtl8366s_port),
1045 .attr = rtl8366s_vlan,
1046 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1049 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1050 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1051 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1052 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1053 .reset_switch = rtl8366s_sw_reset_switch,
1056 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1058 struct switch_dev *dev = &rtl->dev;
1061 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1063 dev->devname = dev_name(rtl->parent);
1065 err = register_switch(dev, NULL);
1067 dev_err(rtl->parent, "switch registration failed\n");
1072 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1074 unregister_switch(&rtl->dev);
1077 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1079 struct rtl8366_smi *smi = bus->priv;
1083 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1090 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1092 struct rtl8366_smi *smi = bus->priv;
1096 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1098 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1103 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1105 return (bus->read == rtl8366s_mii_read &&
1106 bus->write == rtl8366s_mii_write);
1109 static int rtl8366s_setup(struct rtl8366s *rtl)
1111 struct rtl8366_smi *smi = &rtl->smi;
1114 ret = rtl8366s_reset_chip(smi);
1118 ret = rtl8366s_hw_init(smi);
1122 static int rtl8366s_detect(struct rtl8366_smi *smi)
1128 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1130 dev_err(smi->parent, "unable to read chip id\n");
1135 case RTL8366S_CHIP_ID_8366:
1138 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1142 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1145 dev_err(smi->parent, "unable to read chip version\n");
1149 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1150 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1155 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1156 .detect = rtl8366s_detect,
1157 .mii_read = rtl8366s_mii_read,
1158 .mii_write = rtl8366s_mii_write,
1160 .get_vlan_mc = rtl8366s_get_vlan_mc,
1161 .set_vlan_mc = rtl8366s_set_vlan_mc,
1162 .get_vlan_4k = rtl8366s_get_vlan_4k,
1163 .set_vlan_4k = rtl8366s_set_vlan_4k,
1164 .get_mc_index = rtl8366s_get_mc_index,
1165 .set_mc_index = rtl8366s_set_mc_index,
1166 .get_mib_counter = rtl8366_get_mib_counter,
1169 static int __init rtl8366s_probe(struct platform_device *pdev)
1171 static int rtl8366_smi_version_printed;
1172 struct rtl8366s_platform_data *pdata;
1173 struct rtl8366s *rtl;
1174 struct rtl8366_smi *smi;
1177 if (!rtl8366_smi_version_printed++)
1178 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1179 " version " RTL8366S_DRIVER_VER"\n");
1181 pdata = pdev->dev.platform_data;
1183 dev_err(&pdev->dev, "no platform data specified\n");
1188 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1190 dev_err(&pdev->dev, "no memory for private data\n");
1195 rtl->parent = &pdev->dev;
1198 smi->parent = &pdev->dev;
1199 smi->gpio_sda = pdata->gpio_sda;
1200 smi->gpio_sck = pdata->gpio_sck;
1201 smi->ops = &rtl8366s_smi_ops;
1202 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1203 smi->num_ports = RTL8366S_NUM_PORTS;
1204 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1205 smi->mib_counters = rtl8366s_mib_counters;
1206 smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1208 err = rtl8366_smi_init(smi);
1212 platform_set_drvdata(pdev, rtl);
1214 err = rtl8366s_setup(rtl);
1216 goto err_clear_drvdata;
1218 err = rtl8366s_switch_init(rtl);
1220 goto err_clear_drvdata;
1225 platform_set_drvdata(pdev, NULL);
1226 rtl8366_smi_cleanup(smi);
1233 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1235 if (!rtl8366s_mii_bus_match(phydev->bus))
1241 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1246 static struct phy_driver rtl8366s_phy_driver = {
1247 .phy_id = 0x001cc960,
1248 .name = "Realtek RTL8366S",
1249 .phy_id_mask = 0x1ffffff0,
1250 .features = PHY_GBIT_FEATURES,
1251 .config_aneg = rtl8366s_phy_config_aneg,
1252 .config_init = rtl8366s_phy_config_init,
1253 .read_status = genphy_read_status,
1255 .owner = THIS_MODULE,
1259 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1261 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1264 rtl8366s_switch_cleanup(rtl);
1265 platform_set_drvdata(pdev, NULL);
1266 rtl8366_smi_cleanup(&rtl->smi);
1273 static struct platform_driver rtl8366s_driver = {
1275 .name = RTL8366S_DRIVER_NAME,
1276 .owner = THIS_MODULE,
1278 .probe = rtl8366s_probe,
1279 .remove = __devexit_p(rtl8366s_remove),
1282 static int __init rtl8366s_module_init(void)
1285 ret = platform_driver_register(&rtl8366s_driver);
1289 ret = phy_driver_register(&rtl8366s_phy_driver);
1291 goto err_platform_unregister;
1295 err_platform_unregister:
1296 platform_driver_unregister(&rtl8366s_driver);
1299 module_init(rtl8366s_module_init);
1301 static void __exit rtl8366s_module_exit(void)
1303 phy_driver_unregister(&rtl8366s_phy_driver);
1304 platform_driver_unregister(&rtl8366s_driver);
1306 module_exit(rtl8366s_module_exit);
1308 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1309 MODULE_VERSION(RTL8366S_DRIVER_VER);
1310 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1311 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1312 MODULE_LICENSE("GPL v2");
1313 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);