2 * Hifn HIPP-I/HIPP-II (7855/8155) driver.
3 * Copyright (c) 2006 Michael Richardson <mcr@xelerance.com> *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Effort sponsored by Hifn inc.
33 #ifndef __HIFNHIPPVAR_H__
34 #define __HIFNHIPPVAR_H__
36 #define HIPP_MAX_CHIPS 8
39 * Holds data specific to a single Hifn HIPP-I board.
42 softc_device_decl sc_dev;
44 struct pci_dev *sc_pcidev; /* device backpointer */
45 ocf_iomem_t sc_bar[5];
46 caddr_t sc_barphy[5]; /* physical address */
47 int sc_num; /* for multiple devs */
48 spinlock_t sc_mtx; /* per-instance lock */
55 u_int32_t sc_drammodel; /* 1=dram, 0=sram */
56 u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */
58 struct hifn_dma *sc_dma;
59 dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */
64 struct hifn_session *sc_sessions;
67 #define HIFN_HAS_RNG 0x1 /* includes random number generator */
68 #define HIFN_HAS_PUBLIC 0x2 /* includes public key support */
69 #define HIFN_HAS_AES 0x4 /* includes AES support */
70 #define HIFN_IS_7811 0x8 /* Hifn 7811 part */
71 #define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */
73 struct timer_list sc_tickto; /* for managing DMA */
76 int sc_rnghz; /* RNG polling frequency */
78 int sc_c_busy; /* command ring busy */
79 int sc_s_busy; /* source data ring busy */
80 int sc_d_busy; /* destination data ring busy */
81 int sc_r_busy; /* result ring busy */
82 int sc_active; /* for initial countdown */
83 int sc_needwakeup; /* ops q'd wating on resources */
84 int sc_curbatch; /* # ops submitted w/o int */
86 struct miscdevice sc_miscdev;
90 #define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags)
91 #define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags)
93 #endif /* __HIFNHIPPVAR_H__ */