1 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/init.h>
5 #include <linux/delay.h>
7 #include <asm/ifxmips/ifxmips.h>
8 #include <asm/ifxmips/ifxmips_irq.h>
9 #include <asm/addrspace.h>
10 #include <linux/vmalloc.h>
12 #define IFXMIPS_PCI_MEM_BASE 0x18000000
13 #define IFXMIPS_PCI_MEM_SIZE 0x02000000
14 #define IFXMIPS_PCI_IO_BASE 0x1AE00000
15 #define IFXMIPS_PCI_IO_SIZE 0x00200000
17 #define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
18 #define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
19 #define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
21 #define PCI_ACCESS_READ 0
22 #define PCI_ACCESS_WRITE 1
24 //#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
26 static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
27 static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
29 struct pci_ops ifxmips_pci_ops = {
30 .read = ifxmips_pci_read_config_dword,
31 .write = ifxmips_pci_write_config_dword
34 static struct resource pci_io_resource = {
35 .name = "io pci IO space",
36 .start = IFXMIPS_PCI_IO_BASE,
37 .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
38 .flags = IORESOURCE_IO
41 static struct resource pci_mem_resource = {
42 .name = "ext pci memory space",
43 .start = IFXMIPS_PCI_MEM_BASE,
44 .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
45 .flags = IORESOURCE_MEM
48 static struct pci_controller ifxmips_pci_controller = {
49 .pci_ops = &ifxmips_pci_ops,
50 .mem_resource = &pci_mem_resource,
51 .mem_offset = 0x00000000UL,
52 .io_resource = &pci_io_resource,
53 .io_offset = 0x00000000UL,
56 static u32 ifxmips_pci_mapped_cfg;
59 ifxmips_pci_config_access(unsigned char access_type,
60 struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
62 unsigned long cfg_base;
67 /* IFXMips support slot from 0 to 15 */
68 /* dev_fn 0&0x68 (AD29) is ifxmips itself */
69 if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
70 || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
73 local_irq_save(flags);
75 cfg_base = ifxmips_pci_mapped_cfg;
76 cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
77 IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
80 if (access_type == PCI_ACCESS_WRITE)
82 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
83 writel(swab32(*data), ((u32*)cfg_base));
85 writel(*data, ((u32*)cfg_base));
88 *data = readl(((u32*)(cfg_base)));
89 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
90 *data = swab32(*data);
95 /* clean possible Master abort */
96 cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
97 temp = readl(((u32*)(cfg_base)));
98 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
101 cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
102 writel(temp, ((u32*)cfg_base));
104 local_irq_restore(flags);
106 if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
112 static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 * val)
117 if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
118 return PCIBIOS_DEVICE_NOT_FOUND;
121 *val = (data >> ((where & 3) << 3)) & 0xff;
123 *val = (data >> ((where & 3) << 3)) & 0xffff;
127 return PCIBIOS_SUCCESSFUL;
130 static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
131 int where, int size, u32 val)
139 if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
140 return PCIBIOS_DEVICE_NOT_FOUND;
143 data = (data & ~(0xff << ((where & 3) << 3))) |
144 (val << ((where & 3) << 3));
146 data = (data & ~(0xffff << ((where & 3) << 3))) |
147 (val << ((where & 3) << 3));
150 if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
151 return PCIBIOS_DEVICE_NOT_FOUND;
153 return PCIBIOS_SUCCESSFUL;
157 int pcibios_plat_dev_init(struct pci_dev *dev){
160 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
166 //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
167 printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
168 writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
169 writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
174 printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
176 printk ("WARNING: invalid interrupt pin %d\n", pin);
183 static void __init ifxmips_pci_startup (void){
184 /*initialize the first PCI device--ifxmips itself */
186 /*TODO: trigger reset */
187 writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
188 writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
189 /* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
191 PADsel of PCI_CR of CGU : 1 =>From CGU
194 writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
195 writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
198 /* PCI_RST: P1.5 ALT 01 */
199 //pliu20060613: start
200 writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
201 writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
202 writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
203 writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
204 writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
206 /* PCI_REQ1: P1.13 ALT 01 */
207 /* PCI_GNT1: P1.14 ALT 01 */
208 writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
209 writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
210 writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
211 writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
212 /* PCI_REQ2: P1.15 ALT 10 */
213 /* PCI_GNT2: P1.7 ALT 10 */
216 /* enable auto-switching between PCI and EBU */
217 writel(0xa, PCI_CR_CLK_CTRL);
218 /* busy, i.e. configuration is not done, PCI access has to be retried */
219 writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
221 /* BUS Master/IO/MEM access */
222 writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
224 temp_buffer = readl(PCI_CR_PC_ARB);
225 /* enable external 2 PCI masters */
226 temp_buffer &= (~(0xf << 16));
227 /* enable internal arbiter */
228 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
229 /* enable internal PCI master reqest */
230 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
232 /* enable EBU reqest */
233 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
235 /* enable all external masters request */
236 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
237 writel(temp_buffer, PCI_CR_PC_ARB);
241 /* FPI ==> PCI MEM address mapping */
242 /* base: 0xb8000000 == > 0x18000000 */
243 /* size: 8x4M = 32M */
244 writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
245 writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
246 writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
247 writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
248 writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
249 writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
250 writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
251 writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
253 /* FPI ==> PCI IO address mapping */
254 /* base: 0xbAE00000 == > 0xbAE00000 */
256 writel(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
258 /* PCI ==> FPI address mapping */
259 /* base: 0x0 ==> 0x0 */
261 /* BAR1 32M map to SDR address */
262 writel(0x0e000008, PCI_CR_BAR11MASK);
263 writel(0, PCI_CR_PCI_ADDR_MAP11);
264 writel(0, PCI_CS_BASE_ADDR1);
265 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
266 /* both TX and RX endian swap are enabled */
267 writel(readl(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
270 /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
271 writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
272 writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
273 /*use 8 dw burse length */
274 writel(0x303, PCI_CR_FCI_BURST_LENGTH);
276 writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
278 writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
281 writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
284 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
287 /* IDSEL = AD29 --> USB Host Controller */
288 return (INT_NUM_IM1_IRL0 + 17);
290 /* IDSEL = AD30 --> mini PCI connector */
291 //return (INT_NUM_IM1_IRL0 + 14);
292 return (INT_NUM_IM0_IRL0 + 22);
294 printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
299 int pcibios_init(void){
300 extern int pci_probe_only;
303 printk ("PCI: Probing PCI hardware on host bus 0.\n");
305 ifxmips_pci_startup ();
307 // IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
308 ifxmips_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
309 printk("IFXMips PCI mapped to 0x%08X\n", (unsigned long)ifxmips_pci_mapped_cfg);
311 ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
313 printk("IFXMips PCI I/O mapped to 0x%08X\n", (unsigned long)ifxmips_pci_controller.io_map_base);
315 register_pci_controller(&ifxmips_pci_controller);
320 arch_initcall(pcibios_init);