1 Content-Type: text/plain; charset="utf-8"
3 Content-Transfer-Encoding: 7bit
4 Subject: [v3,11/13] clk: qcom: Add Krait clock controller driver
5 From: Stephen Boyd <sboyd@codeaurora.org>
6 X-Patchwork-Id: 6063121
7 Message-Id: <1426920332-9340-12-git-send-email-sboyd@codeaurora.org>
8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
10 linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
11 Viresh Kumar <viresh.kumar@linaro.org>, <devicetree@vger.kernel.org>
12 Date: Fri, 20 Mar 2015 23:45:30 -0700
14 The Krait CPU clocks are made up of a primary mux and secondary
15 mux for each CPU and the L2, controlled via cp15 accessors. For
16 Kraits within KPSSv1 each secondary mux accepts a different aux
17 source, but on KPSSv2 each secondary mux accepts the same aux
20 Cc: <devicetree@vger.kernel.org>
21 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
24 .../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++
25 drivers/clk/qcom/Kconfig | 8 +
26 drivers/clk/qcom/Makefile | 1 +
27 drivers/clk/qcom/krait-cc.c | 352 +++++++++++++++++++++
28 4 files changed, 383 insertions(+)
29 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
30 create mode 100644 drivers/clk/qcom/krait-cc.c
33 +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
35 +Krait Clock Controller
41 + Value type: <string>
42 + Definition: must be one of:
49 + Definition: must be 1
53 + kraitcc: clock-controller {
54 + compatible = "qcom,krait-cc-v1";
57 --- a/drivers/clk/qcom/Kconfig
58 +++ b/drivers/clk/qcom/Kconfig
59 @@ -105,6 +105,14 @@ config KPSS_XCC
60 if you want to support CPU frequency scaling on devices such
61 as MSM8960, APQ8064, etc.
64 + tristate "Krait Clock Controller"
65 + depends on COMMON_CLK_QCOM && ARM
68 + Support for the Krait CPU clocks on Qualcomm devices.
69 + Say Y if you want to support CPU frequency scaling.
73 select KRAIT_L2_ACCESSORS
74 --- a/drivers/clk/qcom/Makefile
75 +++ b/drivers/clk/qcom/Makefile
76 @@ -24,3 +24,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8
77 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
78 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
79 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
80 +obj-$(CONFIG_KRAITCC) += krait-cc.o
82 +++ b/drivers/clk/qcom/krait-cc.c
84 +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
86 + * This program is free software; you can redistribute it and/or modify
87 + * it under the terms of the GNU General Public License version 2 and
88 + * only version 2 as published by the Free Software Foundation.
90 + * This program is distributed in the hope that it will be useful,
91 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
92 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
93 + * GNU General Public License for more details.
96 +#include <linux/kernel.h>
97 +#include <linux/init.h>
98 +#include <linux/module.h>
99 +#include <linux/platform_device.h>
100 +#include <linux/err.h>
101 +#include <linux/io.h>
102 +#include <linux/of.h>
103 +#include <linux/of_device.h>
104 +#include <linux/clk.h>
105 +#include <linux/clk-provider.h>
106 +#include <linux/slab.h>
108 +#include "clk-krait.h"
110 +static unsigned int sec_mux_map[] = {
115 +static unsigned int pri_mux_map[] = {
122 +krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
124 + struct krait_div2_clk *div;
125 + struct clk_init_data init = {
127 + .ops = &krait_div2_clk_ops,
128 + .flags = CLK_SET_RATE_PARENT,
130 + const char *p_names[1];
133 + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
139 + div->lpl = id >= 0;
140 + div->offset = offset;
141 + div->hw.init = &init;
143 + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
147 + init.parent_names = p_names;
148 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
154 + clk = devm_clk_register(dev, &div->hw);
158 + return PTR_ERR_OR_ZERO(clk);
162 +krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
165 + struct krait_mux_clk *mux;
166 + static const char *sec_mux_list[] = {
170 + struct clk_init_data init = {
171 + .parent_names = sec_mux_list,
172 + .num_parents = ARRAY_SIZE(sec_mux_list),
173 + .ops = &krait_mux_clk_ops,
174 + .flags = CLK_SET_RATE_PARENT,
178 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
182 + mux->offset = offset;
183 + mux->lpl = id >= 0;
184 + mux->has_safe_parent = true;
188 + mux->parent_map = sec_mux_map;
189 + mux->hw.init = &init;
191 + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
196 + sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
197 + if (!sec_mux_list[0]) {
198 + clk = ERR_PTR(-ENOMEM);
203 + clk = devm_clk_register(dev, &mux->hw);
206 + kfree(sec_mux_list[0]);
209 + return PTR_ERR_OR_ZERO(clk);
213 +krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset)
215 + struct krait_mux_clk *mux;
216 + const char *p_names[3];
217 + struct clk_init_data init = {
218 + .parent_names = p_names,
219 + .num_parents = ARRAY_SIZE(p_names),
220 + .ops = &krait_mux_clk_ops,
221 + .flags = CLK_SET_RATE_PARENT,
225 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
227 + return ERR_PTR(-ENOMEM);
229 + mux->has_safe_parent = true;
233 + mux->offset = offset;
234 + mux->lpl = id >= 0;
235 + mux->parent_map = pri_mux_map;
236 + mux->hw.init = &init;
238 + init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
240 + return ERR_PTR(-ENOMEM);
242 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
244 + clk = ERR_PTR(-ENOMEM);
248 + p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
250 + clk = ERR_PTR(-ENOMEM);
254 + p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
256 + clk = ERR_PTR(-ENOMEM);
260 + clk = devm_clk_register(dev, &mux->hw);
272 +/* id < 0 for L2, otherwise id == physical CPU number */
273 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
282 + offset = 0x4501 + (0x1000 * id);
283 + s = p = kasprintf(GFP_KERNEL, "%d", id);
285 + return ERR_PTR(-ENOMEM);
291 + ret = krait_add_div(dev, id, s, offset);
293 + clk = ERR_PTR(ret);
297 + ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
299 + clk = ERR_PTR(ret);
303 + clk = krait_add_pri_mux(dev, id, s, offset);
309 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
311 + unsigned int idx = clkspec->args[0];
312 + struct clk **clks = data;
315 + pr_err("%s: invalid clock index %d\n", __func__, idx);
316 + return ERR_PTR(-EINVAL);
319 + return clks[idx] ? : ERR_PTR(-ENODEV);
322 +static const struct of_device_id krait_cc_match_table[] = {
323 + { .compatible = "qcom,krait-cc-v1", (void *)1UL },
324 + { .compatible = "qcom,krait-cc-v2" },
327 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
329 +static int krait_cc_probe(struct platform_device *pdev)
331 + struct device *dev = &pdev->dev;
332 + const struct of_device_id *id;
333 + unsigned long cur_rate, aux_rate;
337 + struct clk *l2_pri_mux_clk;
339 + id = of_match_device(krait_cc_match_table, dev);
343 + /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
344 + clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
346 + return PTR_ERR(clk);
349 + clk = clk_register_fixed_factor(dev, "acpu_aux",
350 + "gpll0_vote", 0, 1, 2);
352 + return PTR_ERR(clk);
355 + /* Krait configurations have at most 4 CPUs and one L2 */
356 + clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
360 + for_each_possible_cpu(cpu) {
361 + clk = krait_add_clks(dev, cpu, id->data);
363 + return PTR_ERR(clk);
367 + l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
368 + if (IS_ERR(l2_pri_mux_clk))
369 + return PTR_ERR(l2_pri_mux_clk);
370 + clks[4] = l2_pri_mux_clk;
373 + * We don't want the CPU or L2 clocks to be turned off at late init
374 + * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
375 + * refcount of these clocks. Any cpufreq/hotplug manager can assume
376 + * that the clocks have already been prepared and enabled by the time
379 + for_each_online_cpu(cpu) {
380 + clk_prepare_enable(l2_pri_mux_clk);
381 + WARN(clk_prepare_enable(clks[cpu]),
382 + "Unable to turn on CPU%d clock", cpu);
386 + * Force reinit of HFPLLs and muxes to overwrite any potential
387 + * incorrect configuration of HFPLLs and muxes by the bootloader.
388 + * While at it, also make sure the cores are running at known rates
389 + * and print the current rate.
391 + * The clocks are set to aux clock rate first to make sure the
392 + * secondary mux is not sourcing off of QSB. The rate is then set to
393 + * two different rates to force a HFPLL reinit under all
396 + cur_rate = clk_get_rate(l2_pri_mux_clk);
397 + aux_rate = 384000000;
398 + if (cur_rate == 1) {
399 + pr_info("L2 @ QSB rate. Forcing new rate.\n");
400 + cur_rate = aux_rate;
402 + clk_set_rate(l2_pri_mux_clk, aux_rate);
403 + clk_set_rate(l2_pri_mux_clk, 2);
404 + clk_set_rate(l2_pri_mux_clk, cur_rate);
405 + pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
406 + for_each_possible_cpu(cpu) {
408 + cur_rate = clk_get_rate(clk);
409 + if (cur_rate == 1) {
410 + pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
411 + cur_rate = aux_rate;
413 + clk_set_rate(clk, aux_rate);
414 + clk_set_rate(clk, 2);
415 + clk_set_rate(clk, cur_rate);
416 + pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
419 + of_clk_add_provider(dev->of_node, krait_of_get, clks);
424 +static struct platform_driver krait_cc_driver = {
425 + .probe = krait_cc_probe,
427 + .name = "krait-cc",
428 + .of_match_table = krait_cc_match_table,
431 +module_platform_driver(krait_cc_driver);
433 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
434 +MODULE_LICENSE("GPL v2");
435 +MODULE_ALIAS("platform:krait-cc");