target/linux/ixp4xx/patches-2.6.25/202-npe_hss.patch

   1 diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
   2 index a3df09e..94e7aa7 100644
   3 --- a/drivers/net/wan/Kconfig
   4 +++ b/drivers/net/wan/Kconfig
   5 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
   6
   7           Say Y if your card supports this feature.
   8
   9 +config IXP4XX_HSS
  10 +       tristate "IXP4xx HSS (synchronous serial port) support"
  11 +       depends on HDLC && ARM && ARCH_IXP4XX
  12 +       select IXP4XX_NPE
  13 +       select IXP4XX_QMGR
  14 +       help
  15 +         Say Y here if you want to use built-in HSS ports
  16 +         on IXP4xx processor.
  17 +
  18  config DLCI
  19         tristate "Frame Relay DLCI support"
  20         ---help---
  21 diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
  22 index d61fef3..1b1d116 100644
  23 --- a/drivers/net/wan/Makefile
  24 +++ b/drivers/net/wan/Makefile
  25 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101)            += c101.o
  26  obj-$(CONFIG_WANXL)            += wanxl.o
  27  obj-$(CONFIG_PCI200SYN)                += pci200syn.o
  28  obj-$(CONFIG_PC300TOO)         += pc300too.o
  29 +obj-$(CONFIG_IXP4XX_HSS)       += ixp4xx_hss.o
  30
  31  clean-files := wanxlfw.inc
  32  $(obj)/wanxl.o:        $(obj)/wanxlfw.inc
  33 diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
  34 new file mode 100644
  35 index 0000000..cf971b3
  36 --- /dev/null
  37 +++ b/drivers/net/wan/ixp4xx_hss.c
  38 @@ -0,0 +1,2886 @@
  39 +/*
  40 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
  41 + *
  42 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
  43 + *
  44 + * This program is free software; you can redistribute it and/or modify it
  45 + * under the terms of version 2 of the GNU General Public License
  46 + * as published by the Free Software Foundation.
  47 + */
  48 +
  49 +#include <linux/bitops.h>
  50 +#include <linux/cdev.h>
  51 +#include <linux/dma-mapping.h>
  52 +#include <linux/dmapool.h>
  53 +#include <linux/fs.h>
  54 +#include <linux/io.h>
  55 +#include <linux/kernel.h>
  56 +#include <linux/hdlc.h>
  57 +#include <linux/platform_device.h>
  58 +#include <linux/poll.h>
  59 +#include <asm/arch/npe.h>
  60 +#include <asm/arch/qmgr.h>
  61 +
  62 +#define DEBUG_QUEUES           0
  63 +#define DEBUG_DESC             0
  64 +#define DEBUG_RX               0
  65 +#define DEBUG_TX               0
  66 +#define DEBUG_PKT_BYTES                0
  67 +#define DEBUG_CLOSE            0
  68 +#define DEBUG_FRAMER           0
  69 +
  70 +#define DRV_NAME               "ixp4xx_hss"
  71 +
  72 +#define PKT_EXTRA_FLAGS                0 /* orig 1 */
  73 +#define TX_FRAME_SYNC_OFFSET   0 /* channelized */
  74 +#define PKT_NUM_PIPES          1 /* 1, 2 or 4 */
  75 +#define PKT_PIPE_FIFO_SIZEW    4 /* total 4 dwords per HSS */
  76 +
  77 +#define RX_DESCS               16 /* also length of all RX queues */
  78 +#define TX_DESCS               16 /* also length of all TX queues */
  79 +
  80 +#define POOL_ALLOC_SIZE                (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  81 +#define RX_SIZE                        (HDLC_MAX_MRU + 4) /* NPE needs more space */
  82 +#define MAX_CLOSE_WAIT         1000 /* microseconds */
  83 +#define HSS_COUNT              2
  84 +#define MIN_FRAME_SIZE         16   /* bits */
  85 +#define MAX_FRAME_SIZE         257  /* 256 bits + framing bit */
  86 +#define MAX_CHANNELS           (MAX_FRAME_SIZE / 8)
  87 +#define MAX_CHAN_DEVICES       32
  88 +#define CHANNEL_HDLC           0xFE
  89 +#define CHANNEL_UNUSED         0xFF
  90 +
  91 +#define NAPI_WEIGHT            16
  92 +#define CHAN_RX_TRIGGER                16 /* 8 RX frames = 1 ms @ E1 */
  93 +#define CHAN_RX_FRAMES         64
  94 +#define MAX_CHAN_RX_BAD_SYNC   (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
  95 +#define CHAN_TX_LIST_FRAMES    16 /* bytes/channel per list, 16 - 48 */
  96 +#define CHAN_TX_LISTS          8
  97 +#define CHAN_TX_FRAMES         (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
  98 +#define CHAN_QUEUE_LEN         16 /* minimum possible */
  99 +
 100 +
 101 +/* Queue IDs */
 102 +#define HSS0_CHL_RXTRIG_QUEUE  12      /* orig size = 32 dwords */
 103 +#define HSS0_PKT_RX_QUEUE      13      /* orig size = 32 dwords */
 104 +#define HSS0_PKT_TX0_QUEUE     14      /* orig size = 16 dwords */
 105 +#define HSS0_PKT_TX1_QUEUE     15
 106 +#define HSS0_PKT_TX2_QUEUE     16
 107 +#define HSS0_PKT_TX3_QUEUE     17
 108 +#define HSS0_PKT_RXFREE0_QUEUE 18      /* orig size = 16 dwords */
 109 +#define HSS0_PKT_RXFREE1_QUEUE 19
 110 +#define HSS0_PKT_RXFREE2_QUEUE 20
 111 +#define HSS0_PKT_RXFREE3_QUEUE 21
 112 +#define HSS0_PKT_TXDONE_QUEUE  22      /* orig size = 64 dwords */
 113 +
 114 +#define HSS1_CHL_RXTRIG_QUEUE  10
 115 +#define HSS1_PKT_RX_QUEUE      0
 116 +#define HSS1_PKT_TX0_QUEUE     5
 117 +#define HSS1_PKT_TX1_QUEUE     6
 118 +#define HSS1_PKT_TX2_QUEUE     7
 119 +#define HSS1_PKT_TX3_QUEUE     8
 120 +#define HSS1_PKT_RXFREE0_QUEUE 1
 121 +#define HSS1_PKT_RXFREE1_QUEUE 2
 122 +#define HSS1_PKT_RXFREE2_QUEUE 3
 123 +#define HSS1_PKT_RXFREE3_QUEUE 4
 124 +#define HSS1_PKT_TXDONE_QUEUE  9
 125 +
 126 +#define NPE_PKT_MODE_HDLC              0
 127 +#define NPE_PKT_MODE_RAW               1
 128 +#define NPE_PKT_MODE_56KMODE           2
 129 +#define NPE_PKT_MODE_56KENDIAN_MSB     4
 130 +
 131 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
 132 +#define PKT_HDLC_IDLE_ONES             0x1 /* default = flags */
 133 +#define PKT_HDLC_CRC_32                        0x2 /* default = CRC-16 */
 134 +#define PKT_HDLC_MSB_ENDIAN            0x4 /* default = LE */
 135 +
 136 +
 137 +/* hss_config, PCRs */
 138 +/* Frame sync sampling, default = active low */
 139 +#define PCR_FRM_SYNC_ACTIVE_HIGH       0x40000000
 140 +#define PCR_FRM_SYNC_FALLINGEDGE       0x80000000
 141 +#define PCR_FRM_SYNC_RISINGEDGE                0xC0000000
 142 +
 143 +/* Frame sync pin: input (default) or output generated off a given clk edge */
 144 +#define PCR_FRM_SYNC_OUTPUT_FALLING    0x20000000
 145 +#define PCR_FRM_SYNC_OUTPUT_RISING     0x30000000
 146 +
 147 +/* Frame and data clock sampling on edge, default = falling */
 148 +#define PCR_FCLK_EDGE_RISING           0x08000000
 149 +#define PCR_DCLK_EDGE_RISING           0x04000000
 150 +
 151 +/* Clock direction, default = input */
 152 +#define PCR_SYNC_CLK_DIR_OUTPUT                0x02000000
 153 +
 154 +/* Generate/Receive frame pulses, default = enabled */
 155 +#define PCR_FRM_PULSE_DISABLED         0x01000000
 156 +
 157 + /* Data rate is full (default) or half the configured clk speed */
 158 +#define PCR_HALF_CLK_RATE              0x00200000
 159 +
 160 +/* Invert data between NPE and HSS FIFOs? (default = no) */
 161 +#define PCR_DATA_POLARITY_INVERT       0x00100000
 162 +
 163 +/* TX/RX endianness, default = LSB */
 164 +#define PCR_MSB_ENDIAN                 0x00080000
 165 +
 166 +/* Normal (default) / open drain mode (TX only) */
 167 +#define PCR_TX_PINS_OPEN_DRAIN         0x00040000
 168 +
 169 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
 170 +#define PCR_SOF_NO_FBIT                        0x00020000
 171 +
 172 +/* Drive data pins? */
 173 +#define PCR_TX_DATA_ENABLE             0x00010000
 174 +
 175 +/* Voice 56k type: drive the data pins low (default), high, high Z */
 176 +#define PCR_TX_V56K_HIGH               0x00002000
 177 +#define PCR_TX_V56K_HIGH_IMP           0x00004000
 178 +
 179 +/* Unassigned type: drive the data pins low (default), high, high Z */
 180 +#define PCR_TX_UNASS_HIGH              0x00000800
 181 +#define PCR_TX_UNASS_HIGH_IMP          0x00001000
 182 +
 183 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
 184 +#define PCR_TX_FB_HIGH_IMP             0x00000400
 185 +
 186 +/* 56k data endiannes - which bit unused: high (default) or low */
 187 +#define PCR_TX_56KE_BIT_0_UNUSED       0x00000200
 188 +
 189 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
 190 +#define PCR_TX_56KS_56K_DATA           0x00000100
 191 +
 192 +/* hss_config, cCR */
 193 +/* Number of packetized clients, default = 1 */
 194 +#define CCR_NPE_HFIFO_2_HDLC           0x04000000
 195 +#define CCR_NPE_HFIFO_3_OR_4HDLC       0x08000000
 196 +
 197 +/* default = no loopback */
 198 +#define CCR_LOOPBACK                   0x02000000
 199 +
 200 +/* HSS number, default = 0 (first) */
 201 +#define CCR_SECOND_HSS                 0x01000000
 202 +
 203 +
 204 +/* hss_config, clkCR: main:10, num:10, denom:12 */
 205 +#define CLK42X_SPEED_EXP       ((0x3FF << 22) | (  2 << 12) |   15) /*65 KHz*/
 206 +
 207 +#define CLK42X_SPEED_512KHZ    ((  130 << 22) | (  2 << 12) |   15)
 208 +#define CLK42X_SPEED_1536KHZ   ((   43 << 22) | ( 18 << 12) |   47)
 209 +#define CLK42X_SPEED_1544KHZ   ((   43 << 22) | ( 33 << 12) |  192)
 210 +#define CLK42X_SPEED_2048KHZ   ((   32 << 22) | ( 34 << 12) |   63)
 211 +#define CLK42X_SPEED_4096KHZ   ((   16 << 22) | ( 34 << 12) |  127)
 212 +#define CLK42X_SPEED_8192KHZ   ((    8 << 22) | ( 34 << 12) |  255)
 213 +
 214 +#define CLK46X_SPEED_512KHZ    ((  130 << 22) | ( 24 << 12) |  127)
 215 +#define CLK46X_SPEED_1536KHZ   ((   43 << 22) | (152 << 12) |  383)
 216 +#define CLK46X_SPEED_1544KHZ   ((   43 << 22) | ( 66 << 12) |  385)
 217 +#define CLK46X_SPEED_2048KHZ   ((   32 << 22) | (280 << 12) |  511)
 218 +#define CLK46X_SPEED_4096KHZ   ((   16 << 22) | (280 << 12) | 1023)
 219 +#define CLK46X_SPEED_8192KHZ   ((    8 << 22) | (280 << 12) | 2047)
 220 +
 221 +
 222 +/* hss_config, LUT entries */
 223 +#define TDMMAP_UNASSIGNED      0
 224 +#define TDMMAP_HDLC            1       /* HDLC - packetized */
 225 +#define TDMMAP_VOICE56K                2       /* Voice56K - 7-bit channelized */
 226 +#define TDMMAP_VOICE64K                3       /* Voice64K - 8-bit channelized */
 227 +
 228 +/* offsets into HSS config */
 229 +#define HSS_CONFIG_TX_PCR      0x00 /* port configuration registers */
 230 +#define HSS_CONFIG_RX_PCR      0x04
 231 +#define HSS_CONFIG_CORE_CR     0x08 /* loopback control, HSS# */
 232 +#define HSS_CONFIG_CLOCK_CR    0x0C /* clock generator control */
 233 +#define HSS_CONFIG_TX_FCR      0x10 /* frame configuration registers */
 234 +#define HSS_CONFIG_RX_FCR      0x14
 235 +#define HSS_CONFIG_TX_LUT      0x18 /* channel look-up tables */
 236 +#define HSS_CONFIG_RX_LUT      0x38
 237 +
 238 +
 239 +/* NPE command codes */
 240 +/* writes the ConfigWord value to the location specified by offset */
 241 +#define PORT_CONFIG_WRITE              0x40
 242 +
 243 +/* triggers the NPE to load the contents of the configuration table */
 244 +#define PORT_CONFIG_LOAD               0x41
 245 +
 246 +/* triggers the NPE to return an HssErrorReadResponse message */
 247 +#define PORT_ERROR_READ                        0x42
 248 +
 249 +/* reset NPE internal status and enable the HssChannelized operation */
 250 +#define CHAN_FLOW_ENABLE               0x43
 251 +#define CHAN_FLOW_DISABLE              0x44
 252 +#define CHAN_IDLE_PATTERN_WRITE                0x45
 253 +#define CHAN_NUM_CHANS_WRITE           0x46
 254 +#define CHAN_RX_BUF_ADDR_WRITE         0x47
 255 +#define CHAN_RX_BUF_CFG_WRITE          0x48
 256 +#define CHAN_TX_BLK_CFG_WRITE          0x49
 257 +#define CHAN_TX_BUF_ADDR_WRITE         0x4A
 258 +#define CHAN_TX_BUF_SIZE_WRITE         0x4B
 259 +#define CHAN_TSLOTSWITCH_ENABLE                0x4C
 260 +#define CHAN_TSLOTSWITCH_DISABLE       0x4D
 261 +
 262 +/* downloads the gainWord value for a timeslot switching channel associated
 263 +   with bypassNum */
 264 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD  0x4E
 265 +
 266 +/* triggers the NPE to reset internal status and enable the HssPacketized
 267 +   operation for the flow specified by pPipe */
 268 +#define PKT_PIPE_FLOW_ENABLE           0x50
 269 +#define PKT_PIPE_FLOW_DISABLE          0x51
 270 +#define PKT_NUM_PIPES_WRITE            0x52
 271 +#define PKT_PIPE_FIFO_SIZEW_WRITE      0x53
 272 +#define PKT_PIPE_HDLC_CFG_WRITE                0x54
 273 +#define PKT_PIPE_IDLE_PATTERN_WRITE    0x55
 274 +#define PKT_PIPE_RX_SIZE_WRITE         0x56
 275 +#define PKT_PIPE_MODE_WRITE            0x57
 276 +
 277 +/* HDLC packet status values - desc->status */
 278 +#define ERR_SHUTDOWN           1 /* stop or shutdown occurrance */
 279 +#define ERR_HDLC_ALIGN         2 /* HDLC alignment error */
 280 +#define ERR_HDLC_FCS           3 /* HDLC Frame Check Sum error */
 281 +#define ERR_RXFREE_Q_EMPTY     4 /* RX-free queue became empty while receiving
 282 +                                    this packet (if buf_len < pkt_len) */
 283 +#define ERR_HDLC_TOO_LONG      5 /* HDLC frame size too long */
 284 +#define ERR_HDLC_ABORT         6 /* abort sequence received */
 285 +#define ERR_DISCONNECTING      7 /* disconnect is in progress */
 286 +
 287 +
 288 +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
 289 +enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
 290 +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
 291 +
 292 +#ifdef __ARMEB__
 293 +typedef struct sk_buff buffer_t;
 294 +#define free_buffer dev_kfree_skb
 295 +#define free_buffer_irq dev_kfree_skb_irq
 296 +#else
 297 +typedef void buffer_t;
 298 +#define free_buffer kfree
 299 +#define free_buffer_irq kfree
 300 +#endif
 301 +
 302 +struct chan_device {
 303 +       struct cdev cdev;
 304 +       struct device *dev;
 305 +       struct port *port;
 306 +       unsigned int open_count, excl_open;
 307 +       unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
 308 +       unsigned long errors_bitmap;
 309 +       u8 id, chan_count;
 310 +       u8 log_channels[MAX_CHANNELS];
 311 +};
 312 +
 313 +struct port {
 314 +       struct device *dev;
 315 +       struct npe *npe;
 316 +       struct net_device *netdev;
 317 +       struct napi_struct napi;
 318 +       struct hss_plat_info *plat;
 319 +       buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 320 +       struct desc *desc_tab;  /* coherent */
 321 +       u32 desc_tab_phys;
 322 +       unsigned int id;
 323 +       atomic_t chan_tx_irq_number, chan_rx_irq_number;
 324 +       wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
 325 +       u8 hdlc_cfg;
 326 +
 327 +       /* the following fields must be protected by npe_lock */
 328 +       enum mode mode;
 329 +       unsigned int clock_type, clock_rate, loopback;
 330 +       unsigned int frame_size, frame_sync_offset;
 331 +
 332 +       struct chan_device *chan_devices[MAX_CHAN_DEVICES];
 333 +       u8 *chan_buf;
 334 +       u32 chan_tx_buf_phys, chan_rx_buf_phys;
 335 +       unsigned int chan_open_count, hdlc_open;
 336 +       unsigned int chan_started, initialized, just_set_offset;
 337 +       enum alignment aligned, carrier;
 338 +       unsigned int chan_last_rx, chan_last_tx;
 339 +       /* assigned channels, may be invalid with given frame length or mode */
 340 +       u8 channels[MAX_CHANNELS];
 341 +       int msg_count;
 342 +};
 343 +
 344 +/* NPE message structure */
 345 +struct msg {
 346 +#ifdef __ARMEB__
 347 +       u8 cmd, unused, hss_port, index;
 348 +       union {
 349 +               struct { u8 data8a, data8b, data8c, data8d; };
 350 +               struct { u16 data16a, data16b; };
 351 +               struct { u32 data32; };
 352 +       };
 353 +#else
 354 +       u8 index, hss_port, unused, cmd;
 355 +       union {
 356 +               struct { u8 data8d, data8c, data8b, data8a; };
 357 +               struct { u16 data16b, data16a; };
 358 +               struct { u32 data32; };
 359 +       };
 360 +#endif
 361 +};
 362 +
 363 +/* HDLC packet descriptor */
 364 +struct desc {
 365 +       u32 next;               /* pointer to next buffer, unused */
 366 +
 367 +#ifdef __ARMEB__
 368 +       u16 buf_len;            /* buffer length */
 369 +       u16 pkt_len;            /* packet length */
 370 +       u32 data;               /* pointer to data buffer in RAM */
 371 +       u8 status;
 372 +       u8 error_count;
 373 +       u16 __reserved;
 374 +#else
 375 +       u16 pkt_len;            /* packet length */
 376 +       u16 buf_len;            /* buffer length */
 377 +       u32 data;               /* pointer to data buffer in RAM */
 378 +       u16 __reserved;
 379 +       u8 error_count;
 380 +       u8 status;
 381 +#endif
 382 +       u32 __reserved1[4];
 383 +};
 384 +
 385 +
 386 +#define rx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 387 +                                (n) * sizeof(struct desc))
 388 +#define rx_desc_ptr(port, n)   (&(port)->desc_tab[n])
 389 +
 390 +#define tx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 391 +                                ((n) + RX_DESCS) * sizeof(struct desc))
 392 +#define tx_desc_ptr(port, n)   (&(port)->desc_tab[(n) + RX_DESCS])
 393 +
 394 +#define chan_tx_buf_len(port)  (port->frame_size / 8 * CHAN_TX_FRAMES)
 395 +#define chan_tx_lists_len(port)        (port->frame_size / 8 * CHAN_TX_LISTS * \
 396 +                                sizeof(u32))
 397 +#define chan_rx_buf_len(port)  (port->frame_size / 8 * CHAN_RX_FRAMES)
 398 +
 399 +#define chan_tx_buf(port)      ((port)->chan_buf)
 400 +#define chan_tx_lists(port)    (chan_tx_buf(port) + chan_tx_buf_len(port))
 401 +#define chan_rx_buf(port)      (chan_tx_lists(port) + chan_tx_lists_len(port))
 402 +
 403 +#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys +   \
 404 +                                 chan_tx_buf_len(port))
 405 +
 406 +static int hss_prepare_chan(struct port *port);
 407 +void hss_chan_stop(struct port *port);
 408 +
 409 +/*****************************************************************************
 410 + * global variables
 411 + ****************************************************************************/
 412 +
 413 +static struct class *hss_class;
 414 +static int chan_major;
 415 +static int ports_open;
 416 +static struct dma_pool *dma_pool;
 417 +static spinlock_t npe_lock;
 418 +
 419 +static const struct {
 420 +       int tx, txdone, rx, rxfree, chan;
 421 +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
 422 +                 HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
 423 +                {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
 424 +                 HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
 425 +};
 426 +
 427 +/*****************************************************************************
 428 + * utility functions
 429 + ****************************************************************************/
 430 +
 431 +static inline struct port* dev_to_port(struct net_device *dev)
 432 +{
 433 +       return dev_to_hdlc(dev)->priv;
 434 +}
 435 +
 436 +static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
 437 +{
 438 +       return container_of(inode->i_cdev, struct chan_device, cdev);
 439 +}
 440 +
 441 +#ifndef __ARMEB__
 442 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 443 +{
 444 +       int i;
 445 +       for (i = 0; i < cnt; i++)
 446 +               dest[i] = swab32(src[i]);
 447 +}
 448 +#endif
 449 +
 450 +static int get_number(const char **buf, size_t *len, unsigned int *ptr,
 451 +                     unsigned int min, unsigned int max)
 452 +{
 453 +       char *endp;
 454 +       unsigned long val = simple_strtoul(*buf, &endp, 10);
 455 +
 456 +       if (endp == *buf || endp - *buf > *len || val < min || val > max)
 457 +               return -EINVAL;
 458 +       *len -= endp - *buf;
 459 +       *buf = endp;
 460 +       *ptr = val;
 461 +       return 0;
 462 +}
 463 +
 464 +static int parse_channels(const char **buf, size_t *len, u8 *channels)
 465 +{
 466 +       unsigned int ch, next = 0;
 467 +
 468 +       if (*len && (*buf)[*len - 1] == '\n')
 469 +               (*len)--;
 470 +
 471 +       memset(channels, 0, MAX_CHANNELS);
 472 +
 473 +       if (!*len)
 474 +               return 0;
 475 +
 476 +       /* Format: "A,B-C,...", A > B > C */
 477 +       while (1) {
 478 +               if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
 479 +                       return -EINVAL;
 480 +               channels[ch] = 1;
 481 +               next = ch + 1;
 482 +               if (!*len)
 483 +                       break;
 484 +               if (**buf == ',') {
 485 +                       (*buf)++;
 486 +                       (*len)--;
 487 +                       continue;
 488 +               }
 489 +               if (**buf != '-')
 490 +                       return -EINVAL;
 491 +               (*buf)++;
 492 +               (*len)--;
 493 +               if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
 494 +                       return -EINVAL;
 495 +               while (next <= ch)
 496 +                       channels[next++] = 1;
 497 +               if (!*len)
 498 +                       break;
 499 +               if (**buf != ',')
 500 +                       return -EINVAL;
 501 +               (*buf)++;
 502 +               (*len)--;
 503 +       }
 504 +       return 1;
 505 +}
 506 +
 507 +static size_t print_channels(struct port *port, char *buf, u8 id)
 508 +{
 509 +       unsigned int ch, cnt = 0;
 510 +       size_t len = 0;
 511 +
 512 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
 513 +               if (port->channels[ch] == id) {
 514 +                       if (cnt == 0) {
 515 +                               sprintf(buf + len, "%s%u", len ? "," : "", ch);
 516 +                               len += strlen(buf + len);
 517 +                       }
 518 +                       cnt++;
 519 +               } else {
 520 +                       if (cnt > 1) {
 521 +                               sprintf(buf + len, "-%u", ch - 1);
 522 +                               len += strlen(buf + len);
 523 +                       }
 524 +                       cnt = 0;
 525 +               }
 526 +       if (cnt > 1) {
 527 +               sprintf(buf + len, "-%u", ch - 1);
 528 +               len += strlen(buf + len);
 529 +       }
 530 +
 531 +       buf[len++] = '\n';
 532 +       return len;
 533 +}
 534 +
 535 +static inline unsigned int sub_offset(unsigned int a, unsigned int b,
 536 +                                     unsigned int modulo)
 537 +{
 538 +       return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
 539 +}
 540 +
 541 +/*****************************************************************************
 542 + * HSS access
 543 + ****************************************************************************/
 544 +
 545 +static void hss_config_load(struct port *port)
 546 +{
 547 +       struct msg msg;
 548 +
 549 +       do {
 550 +               memset(&msg, 0, sizeof(msg));
 551 +               msg.cmd = PORT_CONFIG_LOAD;
 552 +               msg.hss_port = port->id;
 553 +               if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
 554 +                       break;
 555 +               if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
 556 +                       break;
 557 +
 558 +               /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
 559 +               if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
 560 +                       break;
 561 +
 562 +               /* HDLC may stop working without this */
 563 +               npe_recv_message(port->npe, &msg, "FLUSH_IT");
 564 +               return;
 565 +       } while (0);
 566 +
 567 +       printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
 568 +              port->id);
 569 +       BUG();
 570 +}
 571 +
 572 +static void hss_config_set_pcr(struct port *port)
 573 +{
 574 +       struct msg msg;
 575 +
 576 +       do {
 577 +               memset(&msg, 0, sizeof(msg));
 578 +               msg.cmd = PORT_CONFIG_WRITE;
 579 +               msg.hss_port = port->id;
 580 +               msg.index = HSS_CONFIG_TX_PCR;
 581 +               msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
 582 +                       PCR_TX_DATA_ENABLE;
 583 +               if (port->frame_size % 8 == 0)
 584 +                       msg.data32 |= PCR_SOF_NO_FBIT;
 585 +               if (port->clock_type == CLOCK_INT)
 586 +                       msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
 587 +               if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
 588 +                       break;
 589 +
 590 +               msg.index = HSS_CONFIG_RX_PCR;
 591 +               msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
 592 +               if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
 593 +                       break;
 594 +               return;
 595 +       } while (0);
 596 +
 597 +       printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
 598 +       BUG();
 599 +}
 600 +
 601 +static void hss_config_set_hdlc_cfg(struct port *port)
 602 +{
 603 +       struct msg msg;
 604 +
 605 +       memset(&msg, 0, sizeof(msg));
 606 +       msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
 607 +       msg.hss_port = port->id;
 608 +       msg.data8a = port->hdlc_cfg; /* rx_cfg */
 609 +       msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
 610 +       if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
 611 +               printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
 612 +                      " configuration\n", port->id);
 613 +               BUG();
 614 +       }
 615 +}
 616 +
 617 +static void hss_config_set_core(struct port *port)
 618 +{
 619 +       struct msg msg;
 620 +
 621 +       memset(&msg, 0, sizeof(msg));
 622 +       msg.cmd = PORT_CONFIG_WRITE;
 623 +       msg.hss_port = port->id;
 624 +       msg.index = HSS_CONFIG_CORE_CR;
 625 +       msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
 626 +               (port->id ? CCR_SECOND_HSS : 0);
 627 +       if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
 628 +               printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
 629 +                      " register\n", port->id);
 630 +               BUG();
 631 +       }
 632 +}
 633 +
 634 +static void hss_config_set_line(struct port *port)
 635 +{
 636 +       struct msg msg;
 637 +
 638 +       hss_config_set_pcr(port);
 639 +       hss_config_set_core(port);
 640 +
 641 +       memset(&msg, 0, sizeof(msg));
 642 +       msg.cmd = PORT_CONFIG_WRITE;
 643 +       msg.hss_port = port->id;
 644 +       msg.index = HSS_CONFIG_CLOCK_CR;
 645 +       msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
 646 +       if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
 647 +               printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
 648 +                      " register\n", port->id);
 649 +               BUG();
 650 +       }
 651 +}
 652 +
 653 +static void hss_config_set_rx_frame(struct port *port)
 654 +{
 655 +       struct msg msg;
 656 +
 657 +       memset(&msg, 0, sizeof(msg));
 658 +       msg.cmd = PORT_CONFIG_WRITE;
 659 +       msg.hss_port = port->id;
 660 +       msg.index = HSS_CONFIG_RX_FCR;
 661 +       msg.data16a = port->frame_sync_offset;
 662 +       msg.data16b = port->frame_size - 1;
 663 +       if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
 664 +               printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
 665 +                      " and offset\n", port->id);
 666 +               BUG();
 667 +       }
 668 +}
 669 +
 670 +static void hss_config_set_frame(struct port *port)
 671 +{
 672 +       struct msg msg;
 673 +
 674 +       memset(&msg, 0, sizeof(msg));
 675 +       msg.cmd = PORT_CONFIG_WRITE;
 676 +       msg.hss_port = port->id;
 677 +       msg.index = HSS_CONFIG_TX_FCR;
 678 +       msg.data16a = TX_FRAME_SYNC_OFFSET;
 679 +       msg.data16b = port->frame_size - 1;
 680 +       if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
 681 +               printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
 682 +                      " and offset\n", port->id);
 683 +               BUG();
 684 +       }
 685 +       hss_config_set_rx_frame(port);
 686 +}
 687 +
 688 +static void hss_config_set_lut(struct port *port)
 689 +{
 690 +       struct msg msg;
 691 +       int chan_count = 0, log_chan = 0, i, ch;
 692 +       u32 lut[MAX_CHANNELS / 4];
 693 +
 694 +       memset(lut, 0, sizeof(lut));
 695 +       for (i = 0; i < MAX_CHAN_DEVICES; i++)
 696 +               if (port->chan_devices[i])
 697 +                       port->chan_devices[i]->chan_count = 0;
 698 +
 699 +       memset(&msg, 0, sizeof(msg));
 700 +       msg.cmd = PORT_CONFIG_WRITE;
 701 +       msg.hss_port = port->id;
 702 +
 703 +       for (ch = 0; ch < MAX_CHANNELS; ch++) {
 704 +               struct chan_device *chdev = NULL;
 705 +               unsigned int entry;
 706 +
 707 +               if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
 708 +                       chdev = port->chan_devices[port->channels[ch]];
 709 +
 710 +               if (port->mode == MODE_G704 && ch == 0)
 711 +                       entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
 712 +               else if (port->mode == MODE_HDLC ||
 713 +                        port->channels[ch] == CHANNEL_HDLC)
 714 +                       entry = TDMMAP_HDLC;
 715 +               else if (chdev && chdev->open_count) {
 716 +                       entry = TDMMAP_VOICE64K;
 717 +                       chdev->log_channels[chdev->chan_count++] = log_chan;
 718 +               } else
 719 +                       entry = TDMMAP_UNASSIGNED;
 720 +               if (entry == TDMMAP_VOICE64K) {
 721 +                       chan_count++;
 722 +                       log_chan++;
 723 +               }
 724 +
 725 +               msg.data32 >>= 2;
 726 +               msg.data32 |= entry << 30;
 727 +
 728 +               if (ch % 16 == 15) {
 729 +                       msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
 730 +                       if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
 731 +                               break;
 732 +
 733 +                       msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
 734 +                       if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
 735 +                               break;
 736 +               }
 737 +       }
 738 +       if (ch != MAX_CHANNELS) {
 739 +               printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
 740 +                      " table\n", port->id);
 741 +               BUG();
 742 +       }
 743 +
 744 +       hss_config_set_frame(port);
 745 +
 746 +       if (!chan_count)
 747 +               return;
 748 +
 749 +       memset(&msg, 0, sizeof(msg));
 750 +       msg.cmd = CHAN_NUM_CHANS_WRITE;
 751 +       msg.hss_port = port->id;
 752 +       msg.data8a = chan_count;
 753 +       if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
 754 +               printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
 755 +                      port->id);
 756 +               BUG();
 757 +       }
 758 +
 759 +       /* don't leak data */
 760 +       // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
 761 +       if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
 762 +               for (i = 0; i < CHAN_TX_FRAMES; i += 4)
 763 +                       *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
 764 +
 765 +       for (i = 0; i < CHAN_TX_LISTS; i++) {
 766 +               u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
 767 +               u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
 768 +               for (ch = 0; ch < chan_count; ch++)
 769 +                       list[ch] = phys + ch * CHAN_TX_FRAMES;
 770 +       }
 771 +       dma_sync_single(port->dev, port->chan_tx_buf_phys,
 772 +                       chan_tx_buf_len(port) + chan_tx_lists_len(port),
 773 +                       DMA_TO_DEVICE);
 774 +}
 775 +
 776 +static u32 hss_config_get_status(struct port *port)
 777 +{
 778 +       struct msg msg;
 779 +
 780 +       do {
 781 +               memset(&msg, 0, sizeof(msg));
 782 +               msg.cmd = PORT_ERROR_READ;
 783 +               msg.hss_port = port->id;
 784 +               if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
 785 +                       break;
 786 +               if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
 787 +                       break;
 788 +
 789 +               return msg.data32;
 790 +       } while (0);
 791 +
 792 +       printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
 793 +       BUG();
 794 +}
 795 +
 796 +static void hss_config_start_chan(struct port *port)
 797 +{
 798 +       struct msg msg;
 799 +
 800 +       port->chan_last_tx = 0;
 801 +       port->chan_last_rx = 0;
 802 +
 803 +       do {
 804 +               memset(&msg, 0, sizeof(msg));
 805 +               msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
 806 +               msg.hss_port = port->id;
 807 +               msg.data32 = port->chan_rx_buf_phys;
 808 +               if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
 809 +                       break;
 810 +
 811 +               memset(&msg, 0, sizeof(msg));
 812 +               msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
 813 +               msg.hss_port = port->id;
 814 +               msg.data32 = chan_tx_lists_phys(port);
 815 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
 816 +                       break;
 817 +
 818 +               memset(&msg, 0, sizeof(msg));
 819 +               msg.cmd = CHAN_FLOW_ENABLE;
 820 +               msg.hss_port = port->id;
 821 +               if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
 822 +                       break;
 823 +               port->chan_started = 1;
 824 +               return;
 825 +       } while (0);
 826 +
 827 +       printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
 828 +              port->id);
 829 +       BUG();
 830 +}
 831 +
 832 +static void hss_config_stop_chan(struct port *port)
 833 +{
 834 +       struct msg msg;
 835 +
 836 +       if (!port->chan_started)
 837 +               return;
 838 +
 839 +       memset(&msg, 0, sizeof(msg));
 840 +       msg.cmd = CHAN_FLOW_DISABLE;
 841 +       msg.hss_port = port->id;
 842 +       if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
 843 +               printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
 844 +                      port->id);
 845 +               BUG();
 846 +       }
 847 +       hss_config_get_status(port); /* make sure it's halted */
 848 +}
 849 +
 850 +static void hss_config_start_hdlc(struct port *port)
 851 +{
 852 +       struct msg msg;
 853 +
 854 +       memset(&msg, 0, sizeof(msg));
 855 +       msg.cmd = PKT_PIPE_FLOW_ENABLE;
 856 +       msg.hss_port = port->id;
 857 +       msg.data32 = 0;
 858 +       if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
 859 +               printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
 860 +                      port->id);
 861 +               BUG();
 862 +       }
 863 +}
 864 +
 865 +static void hss_config_stop_hdlc(struct port *port)
 866 +{
 867 +       struct msg msg;
 868 +
 869 +       memset(&msg, 0, sizeof(msg));
 870 +       msg.cmd = PKT_PIPE_FLOW_DISABLE;
 871 +       msg.hss_port = port->id;
 872 +       if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
 873 +               printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
 874 +                      port->id);
 875 +               BUG();
 876 +       }
 877 +       hss_config_get_status(port); /* make sure it's halted */
 878 +}
 879 +
 880 +static int hss_config_load_firmware(struct port *port)
 881 +{
 882 +       struct msg msg;
 883 +
 884 +       if (port->initialized)
 885 +               return 0;
 886 +
 887 +       if (!npe_running(port->npe)) {
 888 +               int err;
 889 +               if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
 890 +                                            port->dev)))
 891 +                       return err;
 892 +       }
 893 +
 894 +       do {
 895 +               /* HSS main configuration */
 896 +               hss_config_set_line(port);
 897 +
 898 +               hss_config_set_frame(port);
 899 +
 900 +               /* HDLC mode configuration */
 901 +               memset(&msg, 0, sizeof(msg));
 902 +               msg.cmd = PKT_NUM_PIPES_WRITE;
 903 +               msg.hss_port = port->id;
 904 +               msg.data8a = PKT_NUM_PIPES;
 905 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
 906 +                       break;
 907 +
 908 +               msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
 909 +               msg.data8a = PKT_PIPE_FIFO_SIZEW;
 910 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
 911 +                       break;
 912 +
 913 +               msg.cmd = PKT_PIPE_MODE_WRITE;
 914 +               msg.data8a = NPE_PKT_MODE_HDLC;
 915 +               /* msg.data8b = inv_mask */
 916 +               /* msg.data8c = or_mask */
 917 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
 918 +                       break;
 919 +
 920 +               msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
 921 +               msg.data16a = HDLC_MAX_MRU; /* including CRC */
 922 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
 923 +                       break;
 924 +
 925 +               msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
 926 +               msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
 927 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
 928 +                       break;
 929 +
 930 +               /* Channelized operation settings */
 931 +               memset(&msg, 0, sizeof(msg));
 932 +               msg.cmd = CHAN_TX_BLK_CFG_WRITE;
 933 +               msg.hss_port = port->id;
 934 +               msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
 935 +               msg.data8a = msg.data8b / 4;
 936 +               msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
 937 +               msg.data8c = msg.data8d / 4;
 938 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
 939 +                       break;
 940 +
 941 +               memset(&msg, 0, sizeof(msg));
 942 +               msg.cmd = CHAN_RX_BUF_CFG_WRITE;
 943 +               msg.hss_port = port->id;
 944 +               msg.data8a = CHAN_RX_TRIGGER / 8;
 945 +               msg.data8b = CHAN_RX_FRAMES;
 946 +               if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
 947 +                       break;
 948 +
 949 +               memset(&msg, 0, sizeof(msg));
 950 +               msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
 951 +               msg.hss_port = port->id;
 952 +               msg.data8a = CHAN_TX_LISTS;
 953 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
 954 +                       break;
 955 +
 956 +               port->initialized = 1;
 957 +               return 0;
 958 +       } while (0);
 959 +
 960 +       printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
 961 +       BUG();
 962 +}
 963 +
 964 +/*****************************************************************************
 965 + * packetized (HDLC) operation
 966 + ****************************************************************************/
 967 +
 968 +static inline void debug_pkt(struct net_device *dev, const char *func,
 969 +                            u8 *data, int len)
 970 +{
 971 +#if DEBUG_PKT_BYTES
 972 +       int i;
 973 +
 974 +       printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 975 +       for (i = 0; i < len; i++) {
 976 +               if (i >= DEBUG_PKT_BYTES)
 977 +                       break;
 978 +               printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
 979 +       }
 980 +       printk(KERN_DEBUG "\n");
 981 +#endif
 982 +}
 983 +
 984 +
 985 +static inline void debug_desc(u32 phys, struct desc *desc)
 986 +{
 987 +#if DEBUG_DESC
 988 +       printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
 989 +              phys, desc->next, desc->buf_len, desc->pkt_len,
 990 +              desc->data, desc->status, desc->error_count);
 991 +#endif
 992 +}
 993 +
 994 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
 995 +{
 996 +#if DEBUG_QUEUES
 997 +       static struct {
 998 +               int queue;
 999 +               char *name;
1000 +       } names[] = {
1001 +               { HSS0_PKT_TX0_QUEUE, "TX#0 " },
1002 +               { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
1003 +               { HSS0_PKT_RX_QUEUE, "RX#0 " },
1004 +               { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
1005 +               { HSS1_PKT_TX0_QUEUE, "TX#1 " },
1006 +               { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
1007 +               { HSS1_PKT_RX_QUEUE, "RX#1 " },
1008 +               { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
1009 +       };
1010 +       int i;
1011 +
1012 +       for (i = 0; i < ARRAY_SIZE(names); i++)
1013 +               if (names[i].queue == queue)
1014 +                       break;
1015 +
1016 +       printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1017 +              i < ARRAY_SIZE(names) ? names[i].name : "",
1018 +              is_get ? "->" : "<-", phys);
1019 +#endif
1020 +}
1021 +
1022 +static inline u32 queue_get_entry(unsigned int queue)
1023 +{
1024 +       u32 phys = qmgr_get_entry(queue);
1025 +       debug_queue(queue, 1, phys);
1026 +       return phys;
1027 +}
1028 +
1029 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1030 +                                int is_tx)
1031 +{
1032 +       u32 phys, tab_phys, n_desc;
1033 +       struct desc *tab;
1034 +
1035 +       if (!(phys = queue_get_entry(queue)))
1036 +               return -1;
1037 +
1038 +       BUG_ON(phys & 0x1F);
1039 +       tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1040 +       tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1041 +       n_desc = (phys - tab_phys) / sizeof(struct desc);
1042 +       BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1043 +       debug_desc(phys, &tab[n_desc]);
1044 +       BUG_ON(tab[n_desc].next);
1045 +       return n_desc;
1046 +}
1047 +
1048 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1049 +                                 struct desc *desc)
1050 +{
1051 +       debug_queue(queue, 0, phys);
1052 +       debug_desc(phys, desc);
1053 +       BUG_ON(phys & 0x1F);
1054 +       qmgr_put_entry(queue, phys);
1055 +       BUG_ON(qmgr_stat_overflow(queue));
1056 +}
1057 +
1058 +
1059 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1060 +{
1061 +#ifdef __ARMEB__
1062 +       dma_unmap_single(&port->netdev->dev, desc->data,
1063 +                        desc->buf_len, DMA_TO_DEVICE);
1064 +#else
1065 +       dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1066 +                        ALIGN((desc->data & 3) + desc->buf_len, 4),
1067 +                        DMA_TO_DEVICE);
1068 +#endif
1069 +}
1070 +
1071 +
1072 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
1073 +{
1074 +       struct net_device *netdev = pdev;
1075 +       struct port *port = dev_to_port(netdev);
1076 +       unsigned long flags;
1077 +
1078 +       spin_lock_irqsave(&npe_lock, flags);
1079 +       port->carrier = carrier;
1080 +       if (!port->loopback) {
1081 +               if (carrier)
1082 +                       netif_carrier_on(netdev);
1083 +               else
1084 +                       netif_carrier_off(netdev);
1085 +       }
1086 +       spin_unlock_irqrestore(&npe_lock, flags);
1087 +}
1088 +
1089 +static void hss_hdlc_rx_irq(void *pdev)
1090 +{
1091 +       struct net_device *dev = pdev;
1092 +       struct port *port = dev_to_port(dev);
1093 +
1094 +#if DEBUG_RX
1095 +       printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
1096 +#endif
1097 +       qmgr_disable_irq(queue_ids[port->id].rx);
1098 +       netif_rx_schedule(dev, &port->napi);
1099 +}
1100 +
1101 +static int hss_hdlc_poll(struct napi_struct *napi, int budget)
1102 +{
1103 +       struct port *port = container_of(napi, struct port, napi);
1104 +       struct net_device *dev = port->netdev;
1105 +       unsigned int rxq = queue_ids[port->id].rx;
1106 +       unsigned int rxfreeq = queue_ids[port->id].rxfree;
1107 +       struct net_device_stats *stats = hdlc_stats(dev);
1108 +       int received = 0;
1109 +
1110 +#if DEBUG_RX
1111 +       printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
1112 +#endif
1113 +
1114 +       while (received < budget) {
1115 +               struct sk_buff *skb;
1116 +               struct desc *desc;
1117 +               int n;
1118 +#ifdef __ARMEB__
1119 +               struct sk_buff *temp;
1120 +               u32 phys;
1121 +#endif
1122 +
1123 +               if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1124 +                       received = 0; /* No packet received */
1125 +#if DEBUG_RX
1126 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll"
1127 +                              " netif_rx_complete\n", dev->name);
1128 +#endif
1129 +                       netif_rx_complete(dev, napi);
1130 +                       qmgr_enable_irq(rxq);
1131 +                       if (!qmgr_stat_empty(rxq) &&
1132 +                           netif_rx_reschedule(dev, napi)) {
1133 +#if DEBUG_RX
1134 +                               printk(KERN_DEBUG "%s: hss_hdlc_poll"
1135 +                                      " netif_rx_reschedule succeeded\n",
1136 +                                      dev->name);
1137 +#endif
1138 +                               qmgr_disable_irq(rxq);
1139 +                               continue;
1140 +                       }
1141 +#if DEBUG_RX
1142 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
1143 +                              dev->name);
1144 +#endif
1145 +                       return 0; /* all work done */
1146 +               }
1147 +
1148 +               desc = rx_desc_ptr(port, n);
1149 +#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
1150 +               if (desc->error_count)
1151 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
1152 +                              " errors %u\n", dev->name, desc->status,
1153 +                              desc->error_count);
1154 +#endif
1155 +               skb = NULL;
1156 +               switch (desc->status) {
1157 +               case 0:
1158 +#ifdef __ARMEB__
1159 +                       if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
1160 +                               phys = dma_map_single(&dev->dev, skb->data,
1161 +                                                     RX_SIZE,
1162 +                                                     DMA_FROM_DEVICE);
1163 +                               if (dma_mapping_error(phys)) {
1164 +                                       dev_kfree_skb(skb);
1165 +                                       skb = NULL;
1166 +                               }
1167 +                       }
1168 +#else
1169 +                       skb = netdev_alloc_skb(dev, desc->pkt_len);
1170 +#endif
1171 +                       if (!skb)
1172 +                               stats->rx_dropped++;
1173 +                       break;
1174 +               case ERR_HDLC_ALIGN:
1175 +               case ERR_HDLC_ABORT:
1176 +                       stats->rx_frame_errors++;
1177 +                       stats->rx_errors++;
1178 +                       break;
1179 +               case ERR_HDLC_FCS:
1180 +                       stats->rx_crc_errors++;
1181 +                       stats->rx_errors++;
1182 +                       break;
1183 +               case ERR_HDLC_TOO_LONG:
1184 +                       stats->rx_length_errors++;
1185 +                       stats->rx_errors++;
1186 +                       break;
1187 +               default:        /* FIXME - remove printk */
1188 +                       printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
1189 +                              " errors %u\n", dev->name, desc->status,
1190 +                              desc->error_count);
1191 +                       stats->rx_errors++;
1192 +               }
1193 +
1194 +               if (!skb) {
1195 +                       /* put the desc back on RX-ready queue */
1196 +                       desc->buf_len = RX_SIZE;
1197 +                       desc->pkt_len = desc->status = 0;
1198 +                       queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1199 +                       continue;
1200 +               }
1201 +
1202 +               /* process received frame */
1203 +#ifdef __ARMEB__
1204 +               temp = skb;
1205 +               skb = port->rx_buff_tab[n];
1206 +               dma_unmap_single(&dev->dev, desc->data,
1207 +                                RX_SIZE, DMA_FROM_DEVICE);
1208 +#else
1209 +               dma_sync_single(&dev->dev, desc->data,
1210 +                               RX_SIZE, DMA_FROM_DEVICE);
1211 +               memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1212 +                             ALIGN(desc->pkt_len, 4) / 4);
1213 +#endif
1214 +               skb_put(skb, desc->pkt_len);
1215 +
1216 +               debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
1217 +
1218 +               skb->protocol = hdlc_type_trans(skb, dev);
1219 +               dev->last_rx = jiffies;
1220 +               stats->rx_packets++;
1221 +               stats->rx_bytes += skb->len;
1222 +               netif_receive_skb(skb);
1223 +
1224 +               /* put the new buffer on RX-free queue */
1225 +#ifdef __ARMEB__
1226 +               port->rx_buff_tab[n] = temp;
1227 +               desc->data = phys;
1228 +#endif
1229 +               desc->buf_len = RX_SIZE;
1230 +               desc->pkt_len = 0;
1231 +               queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1232 +               received++;
1233 +       }
1234 +#if DEBUG_RX
1235 +       printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
1236 +#endif
1237 +       return received;        /* not all work done */
1238 +}
1239 +
1240 +
1241 +static void hss_hdlc_txdone_irq(void *pdev)
1242 +{
1243 +       struct net_device *dev = pdev;
1244 +       struct port *port = dev_to_port(dev);
1245 +       struct net_device_stats *stats = hdlc_stats(dev);
1246 +       int n_desc;
1247 +
1248 +#if DEBUG_TX
1249 +       printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
1250 +#endif
1251 +       while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
1252 +                                       port, 1)) >= 0) {
1253 +               struct desc *desc;
1254 +               int start;
1255 +
1256 +               desc = tx_desc_ptr(port, n_desc);
1257 +
1258 +               stats->tx_packets++;
1259 +               stats->tx_bytes += desc->pkt_len;
1260 +
1261 +               dma_unmap_tx(port, desc);
1262 +#if DEBUG_TX
1263 +               printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
1264 +                      dev->name, port->tx_buff_tab[n_desc]);
1265 +#endif
1266 +               free_buffer_irq(port->tx_buff_tab[n_desc]);
1267 +               port->tx_buff_tab[n_desc] = NULL;
1268 +
1269 +               start = qmgr_stat_empty(port->plat->txreadyq);
1270 +               queue_put_desc(port->plat->txreadyq,
1271 +                              tx_desc_phys(port, n_desc), desc);
1272 +               if (start) {
1273 +#if DEBUG_TX
1274 +                       printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
1275 +                              " ready\n", dev->name);
1276 +#endif
1277 +                       netif_wake_queue(dev);
1278 +               }
1279 +       }
1280 +}
1281 +
1282 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
1283 +{
1284 +       struct port *port = dev_to_port(dev);
1285 +       struct net_device_stats *stats = hdlc_stats(dev);
1286 +       unsigned int txreadyq = port->plat->txreadyq;
1287 +       int len, offset, bytes, n;
1288 +       void *mem;
1289 +       u32 phys;
1290 +       struct desc *desc;
1291 +
1292 +#if DEBUG_TX
1293 +       printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
1294 +#endif
1295 +
1296 +       if (unlikely(skb->len > HDLC_MAX_MRU)) {
1297 +               dev_kfree_skb(skb);
1298 +               stats->tx_errors++;
1299 +               return NETDEV_TX_OK;
1300 +       }
1301 +
1302 +       debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
1303 +
1304 +       len = skb->len;
1305 +#ifdef __ARMEB__
1306 +       offset = 0; /* no need to keep alignment */
1307 +       bytes = len;
1308 +       mem = skb->data;
1309 +#else
1310 +       offset = (int)skb->data & 3; /* keep 32-bit alignment */
1311 +       bytes = ALIGN(offset + len, 4);
1312 +       if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1313 +               dev_kfree_skb(skb);
1314 +               stats->tx_dropped++;
1315 +               return NETDEV_TX_OK;
1316 +       }
1317 +       memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1318 +       dev_kfree_skb(skb);
1319 +#endif
1320 +
1321 +       phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1322 +       if (dma_mapping_error(phys)) {
1323 +#ifdef __ARMEB__
1324 +               dev_kfree_skb(skb);
1325 +#else
1326 +               kfree(mem);
1327 +#endif
1328 +               stats->tx_dropped++;
1329 +               return NETDEV_TX_OK;
1330 +       }
1331 +
1332 +       n = queue_get_desc(txreadyq, port, 1);
1333 +       BUG_ON(n < 0);
1334 +       desc = tx_desc_ptr(port, n);
1335 +
1336 +#ifdef __ARMEB__
1337 +       port->tx_buff_tab[n] = skb;
1338 +#else
1339 +       port->tx_buff_tab[n] = mem;
1340 +#endif
1341 +       desc->data = phys + offset;
1342 +       desc->buf_len = desc->pkt_len = len;
1343 +
1344 +       wmb();
1345 +       queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
1346 +       dev->trans_start = jiffies;
1347 +
1348 +       if (qmgr_stat_empty(txreadyq)) {
1349 +#if DEBUG_TX
1350 +               printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
1351 +#endif
1352 +               netif_stop_queue(dev);
1353 +               /* we could miss TX ready interrupt */
1354 +               if (!qmgr_stat_empty(txreadyq)) {
1355 +#if DEBUG_TX
1356 +                       printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
1357 +                              dev->name);
1358 +#endif
1359 +                       netif_wake_queue(dev);
1360 +               }
1361 +       }
1362 +
1363 +#if DEBUG_TX
1364 +       printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
1365 +#endif
1366 +       return NETDEV_TX_OK;
1367 +}
1368 +
1369 +
1370 +static int request_hdlc_queues(struct port *port)
1371 +{
1372 +       int err;
1373 +
1374 +       err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
1375 +       if (err)
1376 +               return err;
1377 +
1378 +       err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
1379 +       if (err)
1380 +               goto rel_rxfree;
1381 +
1382 +       err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
1383 +       if (err)
1384 +               goto rel_rx;
1385 +
1386 +       err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1387 +       if (err)
1388 +               goto rel_tx;
1389 +
1390 +       err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
1391 +       if (err)
1392 +               goto rel_txready;
1393 +       return 0;
1394 +
1395 +rel_txready:
1396 +       qmgr_release_queue(port->plat->txreadyq);
1397 +rel_tx:
1398 +       qmgr_release_queue(queue_ids[port->id].tx);
1399 +rel_rx:
1400 +       qmgr_release_queue(queue_ids[port->id].rx);
1401 +rel_rxfree:
1402 +       qmgr_release_queue(queue_ids[port->id].rxfree);
1403 +       printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1404 +              port->netdev->name);
1405 +       return err;
1406 +}
1407 +
1408 +static void release_hdlc_queues(struct port *port)
1409 +{
1410 +       qmgr_release_queue(queue_ids[port->id].rxfree);
1411 +       qmgr_release_queue(queue_ids[port->id].rx);
1412 +       qmgr_release_queue(queue_ids[port->id].txdone);
1413 +       qmgr_release_queue(queue_ids[port->id].tx);
1414 +       qmgr_release_queue(port->plat->txreadyq);
1415 +}
1416 +
1417 +static int init_hdlc_queues(struct port *port)
1418 +{
1419 +       int i;
1420 +
1421 +       if (!ports_open)
1422 +               if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
1423 +                                                POOL_ALLOC_SIZE, 32, 0)))
1424 +                       return -ENOMEM;
1425 +
1426 +       if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1427 +                                             &port->desc_tab_phys)))
1428 +               return -ENOMEM;
1429 +       memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1430 +       memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1431 +       memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1432 +
1433 +       /* Setup RX buffers */
1434 +       for (i = 0; i < RX_DESCS; i++) {
1435 +               struct desc *desc = rx_desc_ptr(port, i);
1436 +               buffer_t *buff;
1437 +               void *data;
1438 +#ifdef __ARMEB__
1439 +               if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
1440 +                       return -ENOMEM;
1441 +               data = buff->data;
1442 +#else
1443 +               if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
1444 +                       return -ENOMEM;
1445 +               data = buff;
1446 +#endif
1447 +               desc->buf_len = RX_SIZE;
1448 +               desc->data = dma_map_single(&port->netdev->dev, data,
1449 +                                           RX_SIZE, DMA_FROM_DEVICE);
1450 +               if (dma_mapping_error(desc->data)) {
1451 +                       free_buffer(buff);
1452 +                       return -EIO;
1453 +               }
1454 +               port->rx_buff_tab[i] = buff;
1455 +       }
1456 +
1457 +       return 0;
1458 +}
1459 +
1460 +static void destroy_hdlc_queues(struct port *port)
1461 +{
1462 +       int i;
1463 +
1464 +       if (port->desc_tab) {
1465 +               for (i = 0; i < RX_DESCS; i++) {
1466 +                       struct desc *desc = rx_desc_ptr(port, i);
1467 +                       buffer_t *buff = port->rx_buff_tab[i];
1468 +                       if (buff) {
1469 +                               dma_unmap_single(&port->netdev->dev,
1470 +                                                desc->data, RX_SIZE,
1471 +                                                DMA_FROM_DEVICE);
1472 +                               free_buffer(buff);
1473 +                       }
1474 +               }
1475 +               for (i = 0; i < TX_DESCS; i++) {
1476 +                       struct desc *desc = tx_desc_ptr(port, i);
1477 +                       buffer_t *buff = port->tx_buff_tab[i];
1478 +                       if (buff) {
1479 +                               dma_unmap_tx(port, desc);
1480 +                               free_buffer(buff);
1481 +                       }
1482 +               }
1483 +               dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1484 +               port->desc_tab = NULL;
1485 +       }
1486 +
1487 +       if (!ports_open && dma_pool) {
1488 +               dma_pool_destroy(dma_pool);
1489 +               dma_pool = NULL;
1490 +       }
1491 +}
1492 +
1493 +static int hss_hdlc_open(struct net_device *dev)
1494 +{
1495 +       struct port *port = dev_to_port(dev);
1496 +       unsigned long flags;
1497 +       int i, err = 0;
1498 +
1499 +       if ((err = hdlc_open(dev)))
1500 +               return err;
1501 +
1502 +       if ((err = request_hdlc_queues(port)))
1503 +               goto err_hdlc_close;
1504 +
1505 +       if ((err = init_hdlc_queues(port)))
1506 +               goto err_destroy_queues;
1507 +
1508 +       spin_lock_irqsave(&npe_lock, flags);
1509 +
1510 +       if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
1511 +               err = -EBUSY; /* channel #0 is used for G.704 framing */
1512 +               goto err_unlock;
1513 +       }
1514 +       if (port->mode != MODE_HDLC)
1515 +               for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
1516 +                       if (port->channels[i] == CHANNEL_HDLC) {
1517 +                               err = -ECHRNG; /* frame too short */
1518 +                               goto err_unlock;
1519 +                       }
1520 +
1521 +       if ((err = hss_config_load_firmware(port)))
1522 +               goto err_unlock;
1523 +
1524 +       if (!port->chan_open_count && port->plat->open)
1525 +               if ((err = port->plat->open(port->id, dev,
1526 +                                           hss_hdlc_set_carrier)))
1527 +                       goto err_unlock;
1528 +
1529 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1530 +               if ((err = hss_prepare_chan(port)))
1531 +                       goto err_plat_close;
1532 +
1533 +       spin_unlock_irqrestore(&npe_lock, flags);
1534 +
1535 +       /* Populate queues with buffers, no failure after this point */
1536 +       for (i = 0; i < TX_DESCS; i++)
1537 +               queue_put_desc(port->plat->txreadyq,
1538 +                              tx_desc_phys(port, i), tx_desc_ptr(port, i));
1539 +
1540 +       for (i = 0; i < RX_DESCS; i++)
1541 +               queue_put_desc(queue_ids[port->id].rxfree,
1542 +                              rx_desc_phys(port, i), rx_desc_ptr(port, i));
1543 +
1544 +       napi_enable(&port->napi);
1545 +       netif_start_queue(dev);
1546 +
1547 +       qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1548 +                    hss_hdlc_rx_irq, dev);
1549 +
1550 +       qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1551 +                    hss_hdlc_txdone_irq, dev);
1552 +       qmgr_enable_irq(queue_ids[port->id].txdone);
1553 +
1554 +       ports_open++;
1555 +       port->hdlc_open = 1;
1556 +
1557 +       hss_config_set_hdlc_cfg(port);
1558 +       hss_config_set_lut(port);
1559 +       hss_config_load(port);
1560 +
1561 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1562 +               hss_config_start_chan(port);
1563 +
1564 +       hss_config_start_hdlc(port);
1565 +
1566 +       /* we may already have RX data, enables IRQ */
1567 +       netif_rx_schedule(dev, &port->napi);
1568 +       return 0;
1569 +
1570 +err_plat_close:
1571 +       if (!port->chan_open_count && port->plat->close)
1572 +               port->plat->close(port->id, dev);
1573 +err_unlock:
1574 +       spin_unlock_irqrestore(&npe_lock, flags);
1575 +err_destroy_queues:
1576 +       destroy_hdlc_queues(port);
1577 +       release_hdlc_queues(port);
1578 +err_hdlc_close:
1579 +       hdlc_close(dev);
1580 +       return err;
1581 +}
1582 +
1583 +static int hss_hdlc_close(struct net_device *dev)
1584 +{
1585 +       struct port *port = dev_to_port(dev);
1586 +       unsigned long flags;
1587 +       int i, buffs = RX_DESCS; /* allocated RX buffers */
1588 +
1589 +       spin_lock_irqsave(&npe_lock, flags);
1590 +       ports_open--;
1591 +       port->hdlc_open = 0;
1592 +       qmgr_disable_irq(queue_ids[port->id].rx);
1593 +       netif_stop_queue(dev);
1594 +       napi_disable(&port->napi);
1595 +
1596 +       hss_config_stop_hdlc(port);
1597 +
1598 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1599 +               hss_chan_stop(port);
1600 +
1601 +       while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1602 +               buffs--;
1603 +       while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1604 +               buffs--;
1605 +
1606 +       if (buffs)
1607 +               printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1608 +                      " left in NPE\n", dev->name, buffs);
1609 +
1610 +       buffs = TX_DESCS;
1611 +       while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1612 +               buffs--; /* cancel TX */
1613 +
1614 +       i = 0;
1615 +       do {
1616 +               while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1617 +                       buffs--;
1618 +               if (!buffs)
1619 +                       break;
1620 +       } while (++i < MAX_CLOSE_WAIT);
1621 +
1622 +       if (buffs)
1623 +               printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1624 +                      "left in NPE\n", dev->name, buffs);
1625 +#if DEBUG_CLOSE
1626 +       if (!buffs)
1627 +               printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1628 +#endif
1629 +       qmgr_disable_irq(queue_ids[port->id].txdone);
1630 +
1631 +       if (!port->chan_open_count && port->plat->close)
1632 +               port->plat->close(port->id, dev);
1633 +       spin_unlock_irqrestore(&npe_lock, flags);
1634 +
1635 +       destroy_hdlc_queues(port);
1636 +       release_hdlc_queues(port);
1637 +       hdlc_close(dev);
1638 +       return 0;
1639 +}
1640 +
1641 +
1642 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1643 +                          unsigned short parity)
1644 +{
1645 +       struct port *port = dev_to_port(dev);
1646 +
1647 +       if (encoding != ENCODING_NRZ)
1648 +               return -EINVAL;
1649 +
1650 +       switch(parity) {
1651 +       case PARITY_CRC16_PR1_CCITT:
1652 +               port->hdlc_cfg = 0;
1653 +               return 0;
1654 +
1655 +       case PARITY_CRC32_PR1_CCITT:
1656 +               port->hdlc_cfg = PKT_HDLC_CRC_32;
1657 +               return 0;
1658 +
1659 +       default:
1660 +               return -EINVAL;
1661 +       }
1662 +}
1663 +
1664 +
1665 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1666 +{
1667 +       const size_t size = sizeof(sync_serial_settings);
1668 +       sync_serial_settings new_line;
1669 +       sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1670 +       struct port *port = dev_to_port(dev);
1671 +       unsigned long flags;
1672 +       int i, clk;
1673 +
1674 +       if (cmd != SIOCWANDEV)
1675 +               return hdlc_ioctl(dev, ifr, cmd);
1676 +
1677 +       switch(ifr->ifr_settings.type) {
1678 +       case IF_GET_IFACE:
1679 +               ifr->ifr_settings.type = IF_IFACE_V35;
1680 +               if (ifr->ifr_settings.size < size) {
1681 +                       ifr->ifr_settings.size = size; /* data size wanted */
1682 +                       return -ENOBUFS;
1683 +               }
1684 +               memset(&new_line, 0, sizeof(new_line));
1685 +               new_line.clock_type = port->clock_type;
1686 +               new_line.clock_rate = port->clock_rate;
1687 +               new_line.loopback = port->loopback;
1688 +               if (copy_to_user(line, &new_line, size))
1689 +                       return -EFAULT;
1690 +
1691 +               if (!port->chan_buf)
1692 +                       return 0;
1693 +
1694 +               dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
1695 +                               chan_rx_buf_len(port), DMA_FROM_DEVICE);
1696 +               printk(KERN_DEBUG "RX:\n");
1697 +               for (i = 0; i < chan_rx_buf_len(port); i++) {
1698 +                       if (i % 32 == 0)
1699 +                               printk(KERN_DEBUG "%03X ", i);
1700 +                       printk("%02X%c", chan_rx_buf(port)[i],
1701 +                              (i + 1) % 32 ? ' ' : '\n');
1702 +               }
1703 +
1704 +#if 0
1705 +               printk(KERN_DEBUG "TX:\n");
1706 +               for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
1707 +                            + chan_tx_lists_len(port); i++) {
1708 +                       if (i % 32 == 0)
1709 +                               printk(KERN_DEBUG "%03X ", i);
1710 +                       printk("%02X%c", chan_tx_buf(port)[i],
1711 +                              (i + 1) % 32 ? ' ' : '\n');
1712 +               }
1713 +#endif
1714 +               port->msg_count = 10;
1715 +               return 0;
1716 +
1717 +       case IF_IFACE_SYNC_SERIAL:
1718 +       case IF_IFACE_V35:
1719 +               if(!capable(CAP_NET_ADMIN))
1720 +                       return -EPERM;
1721 +               if (copy_from_user(&new_line, line, size))
1722 +                       return -EFAULT;
1723 +
1724 +               clk = new_line.clock_type;
1725 +               if (port->plat->set_clock)
1726 +                       clk = port->plat->set_clock(port->id, clk);
1727 +
1728 +               if (clk != CLOCK_EXT && clk != CLOCK_INT)
1729 +                       return -EINVAL; /* No such clock setting */
1730 +
1731 +               if (new_line.loopback != 0 && new_line.loopback != 1)
1732 +                       return -EINVAL;
1733 +
1734 +               port->clock_type = clk; /* Update settings */
1735 +               /* FIXME port->clock_rate = new_line.clock_rate */;
1736 +               port->loopback = new_line.loopback;
1737 +
1738 +               spin_lock_irqsave(&npe_lock, flags);
1739 +
1740 +               if (port->chan_open_count || port->hdlc_open) {
1741 +                       hss_config_set_line(port);
1742 +                       hss_config_load(port);
1743 +               }
1744 +               if (port->loopback || port->carrier)
1745 +                       netif_carrier_on(port->netdev);
1746 +               else
1747 +                       netif_carrier_off(port->netdev);
1748 +               spin_unlock_irqrestore(&npe_lock, flags);
1749 +
1750 +               return 0;
1751 +
1752 +       default:
1753 +               return hdlc_ioctl(dev, ifr, cmd);
1754 +       }
1755 +}
1756 +
1757 +/*****************************************************************************
1758 + * channelized (G.704) operation
1759 + ****************************************************************************/
1760 +
1761 +static void g704_rx_framer(struct port *port, unsigned int offset)
1762 +{
1763 +       u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
1764 +                                                 CHAN_RX_FRAMES);
1765 +       unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
1766 +       unsigned int is_first = port->just_set_offset;
1767 +       u8 zeros_even, zeros_odd, ones_even, ones_odd;
1768 +       enum alignment aligned;
1769 +
1770 +       port->just_set_offset = 0;
1771 +       dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
1772 +                       DMA_FROM_DEVICE);
1773 +
1774 +       /* check if aligned first */
1775 +       for (frame = 0; frame < CHAN_RX_TRIGGER &&
1776 +                    (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
1777 +                     bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
1778 +               u8 ve = data[frame];
1779 +               u8 vo = data[frame + 1];
1780 +
1781 +               if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
1782 +                       bad_even++;
1783 +
1784 +               if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
1785 +                       bad_odd++;
1786 +       }
1787 +
1788 +       if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
1789 +               aligned = EVEN_FIRST;
1790 +       else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
1791 +               aligned = ODD_FIRST;
1792 +       else
1793 +               aligned = NOT_ALIGNED;
1794 +
1795 +       if (aligned != NOT_ALIGNED) {
1796 +               if (aligned == port->aligned)
1797 +                       return; /* no change */
1798 +               if (printk_ratelimit())
1799 +                       printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
1800 +                              " first)\n", port->id, port->frame_sync_offset,
1801 +                              aligned == EVEN_FIRST ? "even" : "odd");
1802 +               port->aligned = aligned;
1803 +
1804 +               atomic_inc(&port->chan_tx_irq_number);
1805 +               wake_up_interruptible(&port->chan_tx_waitq);
1806 +               atomic_inc(&port->chan_rx_irq_number);
1807 +               wake_up_interruptible(&port->chan_rx_waitq);
1808 +               return;
1809 +       }
1810 +
1811 +       /* not aligned */
1812 +       if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
1813 +               printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
1814 +               port->aligned = NOT_ALIGNED;
1815 +#if DEBUG_FRAMER
1816 +               for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
1817 +                       printk("%c%02X%s", cnt == offset ? '>' : ' ',
1818 +                              chan_rx_buf(port)[cnt],
1819 +                              (cnt + 1) % 32 ? "" : "\n");
1820 +#endif
1821 +
1822 +               for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
1823 +                       if (port->chan_devices[cnt]) {
1824 +                               set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
1825 +                                       ->errors_bitmap);
1826 +                               set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
1827 +                                       ->errors_bitmap);
1828 +                       }
1829 +               atomic_inc(&port->chan_tx_irq_number);
1830 +               wake_up_interruptible(&port->chan_tx_waitq);
1831 +               atomic_inc(&port->chan_rx_irq_number);
1832 +               wake_up_interruptible(&port->chan_rx_waitq);
1833 +       }
1834 +
1835 +       if (is_first)
1836 +               return;
1837 +
1838 +       zeros_even = zeros_odd = 0;
1839 +       ones_even = ones_odd = 0xFF;
1840 +       for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
1841 +               zeros_even |= data[frame];
1842 +               zeros_odd |= data[frame + 1];
1843 +               ones_even &= data[frame];
1844 +               ones_odd &= data[frame + 1];
1845 +       }
1846 +
1847 +       for (bit = 0; bit < 7; bit++) {
1848 +               if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
1849 +                   (ones_odd & 0x40) == 0x40) {
1850 +                       aligned = EVEN_FIRST; /* maybe */
1851 +                       break;
1852 +               }
1853 +               if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
1854 +                   (ones_even & 0x40) == 0x40) {
1855 +                       aligned = ODD_FIRST; /* maybe */
1856 +                       break;
1857 +               }
1858 +               zeros_even <<= 1;
1859 +               ones_even = ones_even << 1 | 1;
1860 +               zeros_odd <<= 1;
1861 +               ones_odd = ones_odd << 1 | 1;
1862 +       }
1863 +
1864 +       port->frame_sync_offset += port->frame_size - bit;
1865 +       port->frame_sync_offset %= port->frame_size;
1866 +       port->just_set_offset = 1;
1867 +
1868 +#if DEBUG_FRAMER
1869 +       if (bit == 7)
1870 +               printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
1871 +                      port->id, port->frame_sync_offset);
1872 +       else
1873 +               printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
1874 +                      " %u (%s frame first)\n", port->id,
1875 +                      port->frame_sync_offset,
1876 +                      aligned == EVEN_FIRST ? "even" : "odd");
1877 +#endif
1878 +
1879 +       hss_config_set_rx_frame(port);
1880 +       hss_config_load(port);
1881 +}
1882 +
1883 +static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
1884 +{
1885 +       /* in bytes */
1886 +       unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
1887 +       unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
1888 +       int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
1889 +
1890 +       offset *= list_len;
1891 +       eaten = sub_offset(offset, last_offset, buff_len);
1892 +
1893 +       if (chan_dev->tx_count > eaten + 2 * list_len) {
1894 +               /* two pages must be reserved for the transmitter */
1895 +               chan_dev->tx_first += eaten;
1896 +               chan_dev->tx_first %= buff_len;
1897 +               chan_dev->tx_count -= eaten;
1898 +       } else {
1899 +               /* FIXME check
1900 +                  0
1901 +                  1 tx_first (may still be transmited)
1902 +                  2 tx_offset (currently reported by the NPE)
1903 +                  3 tx_first + 2 * list_len (free to write here)
1904 +                  4
1905 +                  5
1906 +               */
1907 +
1908 +               /* printk(KERN_DEBUG "TX buffer underflow\n"); */
1909 +               chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
1910 +               chan_dev->tx_count = 2 * list_len; /* reserve */
1911 +               set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
1912 +       }
1913 +}
1914 +
1915 +static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
1916 +{
1917 +       /* in bytes */
1918 +       unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
1919 +       unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
1920 +       int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
1921 +
1922 +       offset *= chan_dev->chan_count;
1923 +       chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
1924 +                                        buff_len) + trig_len;
1925 +       if (chan_dev->rx_count > buff_len - 2 * trig_len) {
1926 +               /* two pages - offset[0] and offset[1] are lost - FIXME check */
1927 +               /* printk(KERN_DEBUG "RX buffer overflow\n"); */
1928 +               chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
1929 +               chan_dev->rx_count = buff_len - 2 * trig_len;
1930 +               set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
1931 +       }
1932 +}
1933 +
1934 +static void hss_chan_irq(void *pdev)
1935 +{
1936 +       struct port *port = pdev;
1937 +       u32 v;
1938 +
1939 +#if DEBUG_RX
1940 +       printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
1941 +#endif
1942 +       spin_lock(&npe_lock);
1943 +       while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
1944 +               unsigned int first, errors, tx_list, rx_frame;
1945 +               int i, bad;
1946 +
1947 +               first = v >> 24;
1948 +               errors = (v >> 16) & 0xFF;
1949 +               tx_list = (v >> 8) & 0xFF;
1950 +               rx_frame = v & 0xFF;
1951 +
1952 +               if (port->msg_count) {
1953 +                       printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
1954 +                              " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
1955 +                              " 0x%02X\n", port->id, jiffies, first, errors,
1956 +                              tx_list, rx_frame);
1957 +                       port->msg_count--;
1958 +               }
1959 +
1960 +               BUG_ON(rx_frame % CHAN_RX_TRIGGER);
1961 +               BUG_ON(rx_frame >= CHAN_RX_FRAMES);
1962 +               BUG_ON(tx_list >= CHAN_TX_LISTS);
1963 +
1964 +               bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
1965 +               if (!bad && tx_list != port->chan_last_tx) {
1966 +                       if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
1967 +                               printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
1968 +                                      " current %i\n", port->chan_last_tx,
1969 +                                      tx_list);
1970 +                       for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1971 +                               if (!port->chan_devices[i] ||
1972 +                                   !port->chan_devices[i]->open_count)
1973 +                                       continue;
1974 +                               chan_process_tx_irq(port->chan_devices[i],
1975 +                                                   tx_list);
1976 +                       }
1977 +                       atomic_inc(&port->chan_tx_irq_number);
1978 +#if 0
1979 +                       printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
1980 +                              jiffies, errors);
1981 +#endif
1982 +                       wake_up_interruptible(&port->chan_tx_waitq);
1983 +               }
1984 +
1985 +               if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
1986 +                   CHAN_RX_FRAMES)
1987 +                       printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
1988 +                              " current %i\n", port->chan_last_rx, rx_frame);
1989 +
1990 +               if (port->mode == MODE_G704)
1991 +                       g704_rx_framer(port, rx_frame);
1992 +
1993 +               if (!bad &&
1994 +                   (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
1995 +                       for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1996 +                               if (!port->chan_devices[i] ||
1997 +                                   !port->chan_devices[i]->open_count)
1998 +                                       continue;
1999 +                               chan_process_rx_irq(port->chan_devices[i],
2000 +                                                   rx_frame);
2001 +                       }
2002 +                       atomic_inc(&port->chan_rx_irq_number);
2003 +                       wake_up_interruptible(&port->chan_rx_waitq);
2004 +               }
2005 +               port->chan_last_tx = tx_list;
2006 +               port->chan_last_rx = rx_frame;
2007 +       }
2008 +       spin_unlock(&npe_lock);
2009 +}
2010 +
2011 +
2012 +static int hss_prepare_chan(struct port *port)
2013 +{
2014 +       int err;
2015 +
2016 +       if ((err = hss_config_load_firmware(port)))
2017 +               return err;
2018 +
2019 +       if ((err = qmgr_request_queue(queue_ids[port->id].chan,
2020 +                                     CHAN_QUEUE_LEN, 0, 0)))
2021 +               return err;
2022 +
2023 +       if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
2024 +                                      chan_tx_lists_len(port) +
2025 +                                      chan_rx_buf_len(port), GFP_KERNEL))) {
2026 +               goto release_queue;
2027 +               err = -ENOBUFS;
2028 +       }
2029 +
2030 +       port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
2031 +                                               chan_tx_buf_len(port) +
2032 +                                               chan_tx_lists_len(port),
2033 +                                               DMA_TO_DEVICE);
2034 +       if (dma_mapping_error(port->chan_tx_buf_phys)) {
2035 +               err = -EIO;
2036 +               goto free;
2037 +       }
2038 +
2039 +       port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
2040 +                                               chan_rx_buf_len(port),
2041 +                                               DMA_FROM_DEVICE);
2042 +       if (dma_mapping_error(port->chan_rx_buf_phys)) {
2043 +               err = -EIO;
2044 +               goto unmap_tx;
2045 +       }
2046 +
2047 +       qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
2048 +                    hss_chan_irq, port);
2049 +       qmgr_enable_irq(queue_ids[port->id].chan);
2050 +       hss_chan_irq(port);
2051 +       return 0;
2052 +
2053 +unmap_tx:
2054 +       dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2055 +                        chan_tx_buf_len(port) + chan_tx_lists_len(port),
2056 +                        DMA_TO_DEVICE);
2057 +free:
2058 +       kfree(port->chan_buf);
2059 +       port->chan_buf = NULL;
2060 +release_queue:
2061 +       qmgr_release_queue(queue_ids[port->id].chan);
2062 +       return err;
2063 +}
2064 +
2065 +void hss_chan_stop(struct port *port)
2066 +{
2067 +       if (!port->chan_open_count && !port->hdlc_open)
2068 +               qmgr_disable_irq(queue_ids[port->id].chan);
2069 +
2070 +       hss_config_stop_chan(port);
2071 +       hss_config_set_lut(port);
2072 +       hss_config_load(port);
2073 +
2074 +       if (!port->chan_open_count && !port->hdlc_open) {
2075 +               dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2076 +                                chan_tx_buf_len(port) +
2077 +                                chan_tx_lists_len(port), DMA_TO_DEVICE);
2078 +               dma_unmap_single(port->dev, port->chan_rx_buf_phys,
2079 +                                chan_rx_buf_len(port), DMA_FROM_DEVICE);
2080 +               kfree(port->chan_buf);
2081 +               port->chan_buf = NULL;
2082 +               qmgr_release_queue(queue_ids[port->id].chan);
2083 +       }
2084 +}
2085 +
2086 +static int hss_chan_open(struct inode *inode, struct file *file)
2087 +{
2088 +       struct chan_device *chan_dev = inode_to_chan_dev(inode);
2089 +       struct port *port = chan_dev->port;
2090 +       unsigned long flags;
2091 +       int i, err = 0;
2092 +
2093 +       spin_lock_irqsave(&npe_lock, flags);
2094 +
2095 +       if (chan_dev->open_count) {
2096 +               if (chan_dev->excl_open || (file->f_flags & O_EXCL))
2097 +                       err = -EBUSY;
2098 +               else
2099 +                       chan_dev->open_count++;
2100 +               goto out;
2101 +       }
2102 +
2103 +       if (port->mode == MODE_HDLC) {
2104 +               err = -ENOSYS;
2105 +               goto out;
2106 +       }
2107 +
2108 +       if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
2109 +               err = -EBUSY; /* channel #0 is used for G.704 signaling */
2110 +               goto out;
2111 +       }
2112 +       for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
2113 +               if (port->channels[i - 1] == chan_dev->id) {
2114 +                       err = -ECHRNG; /* frame too short */
2115 +                       goto out;
2116 +               }
2117 +
2118 +       chan_dev->rx_first = chan_dev->tx_first = 0;
2119 +       chan_dev->rx_count = chan_dev->tx_count = 0;
2120 +       clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
2121 +       clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
2122 +
2123 +       if (!port->chan_open_count && !port->hdlc_open) {
2124 +               if (port->plat->open)
2125 +                       if ((err = port->plat->open(port->id, port->netdev,
2126 +                                                   hss_hdlc_set_carrier)))
2127 +                               goto out;
2128 +               if ((err = hss_prepare_chan(port))) {
2129 +                       if (port->plat->close)
2130 +                               port->plat->close(port->id, port->netdev);
2131 +                       goto out;
2132 +               }
2133 +       }
2134 +
2135 +       hss_config_stop_chan(port);
2136 +       chan_dev->open_count++;
2137 +       port->chan_open_count++;
2138 +       chan_dev->excl_open = !!file->f_flags & O_EXCL;
2139 +
2140 +       hss_config_set_lut(port);
2141 +       hss_config_load(port);
2142 +       hss_config_start_chan(port);
2143 +out:
2144 +       spin_unlock_irqrestore(&npe_lock, flags);
2145 +       return err;
2146 +}
2147 +
2148 +static int hss_chan_release(struct inode *inode, struct file *file)
2149 +{
2150 +       struct chan_device *chan_dev = inode_to_chan_dev(inode);
2151 +       struct port *port = chan_dev->port;
2152 +       unsigned long flags;
2153 +
2154 +       spin_lock_irqsave(&npe_lock, flags);
2155 +
2156 +       if (!--chan_dev->open_count) {
2157 +               if (!--port->chan_open_count && !port->hdlc_open) {
2158 +                       hss_chan_stop(port);
2159 +                       if (port->plat->close)
2160 +                               port->plat->close(port->id, port->netdev);
2161 +               } else {
2162 +                       hss_config_stop_chan(port);
2163 +                       hss_config_set_lut(port);
2164 +                       hss_config_set_line(port); //
2165 +                       hss_config_start_chan(port);
2166 +               }
2167 +       }
2168 +
2169 +       spin_unlock_irqrestore(&npe_lock, flags);
2170 +       return 0;
2171 +}
2172 +
2173 +static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
2174 +                            loff_t *f_pos)
2175 +{
2176 +       struct chan_device *chan_dev = inode_to_chan_dev
2177 +               (file->f_path.dentry->d_inode);
2178 +       struct port *port = chan_dev->port;
2179 +       unsigned long flags;
2180 +       u8 *rx_buf;
2181 +       int res = 0, loops = 0;
2182 +
2183 +       spin_lock_irqsave(&npe_lock, flags);
2184 +
2185 +       while (1) {
2186 +               int prev_irq = atomic_read(&port->chan_rx_irq_number);
2187 +#if 0
2188 +               if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
2189 +                   || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2190 +                       res = -EIO;
2191 +                       goto out;
2192 +               }
2193 +#endif
2194 +               if (count == 0)
2195 +                       goto out;       /* no need to wait */
2196 +
2197 +               if (chan_dev->rx_count)
2198 +                       break;
2199 +
2200 +               spin_unlock_irqrestore(&npe_lock, flags);
2201 +               loops++;
2202 +               if ((res = wait_event_interruptible
2203 +                    (port->chan_rx_waitq,
2204 +                     atomic_read(&port->chan_rx_irq_number) != prev_irq)))
2205 +                       goto out;
2206 +               spin_lock_irqsave(&npe_lock, flags);
2207 +               continue;
2208 +       }
2209 +
2210 +       dma_sync_single(port->dev, port->chan_rx_buf_phys,
2211 +                       chan_rx_buf_len(port), DMA_FROM_DEVICE);
2212 +
2213 +#if 0
2214 +       if (loops > 1)
2215 +               printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
2216 +                      " last_rx %u loops %i\n", chan_dev->rx_first,
2217 +                      chan_dev->rx_count, count, port->chan_last_rx, loops);
2218 +#endif
2219 +       rx_buf = chan_rx_buf(port);
2220 +       while (chan_dev->rx_count > 0 && res < count) {
2221 +               unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
2222 +               unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
2223 +
2224 +               chan = chan_dev->log_channels[chan];
2225 +               if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
2226 +                       res = -EFAULT;
2227 +                       goto out;
2228 +               }
2229 +               chan_dev->rx_first++;
2230 +               chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
2231 +               chan_dev->rx_count--;
2232 +               res++;
2233 +       }
2234 +out:
2235 +#if 0
2236 +       printk(KERN_DEBUG "EXIT  rx_first %u rx_count %u res %i\n",
2237 +              chan_dev->rx_first, chan_dev->rx_count, res);
2238 +#endif
2239 +       spin_unlock_irqrestore(&npe_lock, flags);
2240 +       return res;
2241 +}
2242 +
2243 +static ssize_t hss_chan_write(struct file *file, const char __user *buf,
2244 +                             size_t count, loff_t *f_pos)
2245 +{
2246 +       struct chan_device *chan_dev = inode_to_chan_dev
2247 +               (file->f_path.dentry->d_inode);
2248 +       struct port *port = chan_dev->port;
2249 +       unsigned long flags;
2250 +       u8 *tx_buf;
2251 +       int res = 0, loops = 0;
2252 +
2253 +       spin_lock_irqsave(&npe_lock, flags);
2254 +       while (1) {
2255 +               int prev_irq = atomic_read(&port->chan_tx_irq_number);
2256 +#if 0
2257 +               if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
2258 +                   || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2259 +                       res = -EIO;
2260 +                       goto out;
2261 +               }
2262 +#endif
2263 +               if (count == 0)
2264 +                       goto out;       /* no need to wait */
2265 +
2266 +               if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2267 +                       break;
2268 +
2269 +               spin_unlock_irqrestore(&npe_lock, flags);
2270 +               loops++;
2271 +               if ((res = wait_event_interruptible
2272 +                    (port->chan_tx_waitq,
2273 +                     atomic_read (&port->chan_tx_irq_number) != prev_irq)))
2274 +                       goto out;
2275 +               spin_lock_irqsave(&npe_lock, flags);
2276 +               continue;
2277 +       }
2278 +
2279 +#if 0
2280 +       if (loops > 1)
2281 +               printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
2282 +                      " last_tx %u loops %i\n", chan_dev->tx_first,
2283 +                      chan_dev->tx_count, count, port->chan_last_tx, loops);
2284 +#endif
2285 +       tx_buf = chan_tx_buf(port);
2286 +       while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
2287 +              res < count) {
2288 +               unsigned int tail, chan, frame;
2289 +
2290 +               tail = (chan_dev->tx_first + chan_dev->tx_count) %
2291 +                       (CHAN_TX_FRAMES * chan_dev->chan_count);
2292 +               chan = tail % chan_dev->chan_count;
2293 +               frame = tail / chan_dev->chan_count;
2294 +               chan = chan_dev->log_channels[chan];
2295 +
2296 +               if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
2297 +                       printk(KERN_DEBUG "BUG? TX %u %u %u\n",
2298 +                              tail, chan, frame);
2299 +                       res = -EFAULT;
2300 +                       goto out_sync;
2301 +               }
2302 +               chan_dev->tx_count++;
2303 +               res++;
2304 +       }
2305 +out_sync:
2306 +       dma_sync_single(port->dev, port->chan_tx_buf_phys,
2307 +                       chan_tx_buf_len(port), DMA_TO_DEVICE);
2308 +out:
2309 +#if 0
2310 +       printk(KERN_DEBUG "EXIT  TX_first %u tx_count %u res %i\n",
2311 +              chan_dev->tx_first, chan_dev->tx_count, res);
2312 +#endif
2313 +       spin_unlock_irqrestore(&npe_lock, flags);
2314 +       return res;
2315 +}
2316 +
2317 +
2318 +static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
2319 +{
2320 +       struct chan_device *chan_dev = inode_to_chan_dev
2321 +               (file->f_path.dentry->d_inode);
2322 +       struct port *port = chan_dev->port;
2323 +       unsigned long flags;
2324 +       unsigned int mask = 0;
2325 +
2326 +       spin_lock_irqsave(&npe_lock, flags);
2327 +       poll_wait(file, &port->chan_tx_waitq, wait);
2328 +       poll_wait(file, &port->chan_rx_waitq, wait);
2329 +
2330 +       if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2331 +               mask |= POLLOUT | POLLWRNORM;
2332 +       if (chan_dev->rx_count)
2333 +               mask |= POLLIN | POLLRDNORM;
2334 +       spin_unlock_irqrestore(&npe_lock, flags);
2335 +       return mask;
2336 +}
2337 +
2338 +/*****************************************************************************
2339 + * channelized device sysfs attributes
2340 + ****************************************************************************/
2341 +
2342 +static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
2343 +                             char *buf)
2344 +{
2345 +       struct chan_device *chan_dev = dev_get_drvdata(dev);
2346 +
2347 +       return print_channels(chan_dev->port, buf, chan_dev->id);
2348 +}
2349 +
2350 +static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
2351 +                            const char *buf, size_t len)
2352 +{
2353 +       struct chan_device *chan_dev = dev_get_drvdata(dev);
2354 +       struct port *port = chan_dev->port;
2355 +       unsigned long flags;
2356 +       unsigned int ch;
2357 +       size_t orig_len = len;
2358 +       int err;
2359 +
2360 +       if (len && buf[len - 1] == '\n')
2361 +               len--;
2362 +
2363 +       if (len != 7 || memcmp(buf, "destroy", 7))
2364 +               return -EINVAL;
2365 +
2366 +       spin_lock_irqsave(&npe_lock, flags);
2367 +       cdev_del(&chan_dev->cdev);
2368 +
2369 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2370 +               if (port->channels[ch] == chan_dev->id)
2371 +                       port->channels[ch] = CHANNEL_UNUSED;
2372 +       port->chan_devices[chan_dev->id] = NULL;
2373 +       kfree(chan_dev);
2374 +       spin_unlock_irqrestore(&npe_lock, flags);
2375 +
2376 +       if ((err = device_schedule_callback(dev, device_unregister)))
2377 +               return err;
2378 +       return orig_len;
2379 +}
2380 +
2381 +static struct device_attribute chan_attr =
2382 +       __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
2383 +
2384 +/*****************************************************************************
2385 + * main sysfs attributes
2386 + ****************************************************************************/
2387 +
2388 +static const struct file_operations chan_fops = {
2389 +       .owner   = THIS_MODULE,
2390 +       .llseek  = no_llseek,
2391 +       .read    = hss_chan_read,
2392 +       .write   = hss_chan_write,
2393 +       .poll    = hss_chan_poll,
2394 +       .open    = hss_chan_open,
2395 +       .release = hss_chan_release,
2396 +};
2397 +
2398 +static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
2399 +                          const char *buf, size_t len)
2400 +{
2401 +       struct port *port = dev_get_drvdata(dev);
2402 +       struct chan_device *chan_dev;
2403 +       u8 channels[MAX_CHANNELS];
2404 +       size_t orig_len = len;
2405 +       unsigned long flags;
2406 +       unsigned int ch, id;
2407 +       int minor, err;
2408 +
2409 +       if ((err = parse_channels(&buf, &len, channels)) < 1)
2410 +               return err;
2411 +
2412 +       if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
2413 +               return -ENOBUFS;
2414 +
2415 +       spin_lock_irqsave(&npe_lock, flags);
2416 +
2417 +       if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2418 +               err = -EINVAL;
2419 +               goto free;
2420 +       }
2421 +
2422 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2423 +               if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
2424 +                       printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2425 +                       err = -EBUSY;
2426 +                       goto free;
2427 +               }
2428 +
2429 +       for (id = 0; id < MAX_CHAN_DEVICES; id++)
2430 +               if (port->chan_devices[id] == NULL)
2431 +                       break;
2432 +
2433 +       if (id == MAX_CHAN_DEVICES) {
2434 +               err = -EBUSY;
2435 +               goto free;
2436 +       }
2437 +
2438 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2439 +               if (channels[ch])
2440 +                       break;
2441 +
2442 +       minor = port->id * MAX_CHAN_DEVICES + ch;
2443 +       chan_dev->id = id;
2444 +       chan_dev->port = port;
2445 +       chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
2446 +                                     "hss%uch%u", port->id, ch);
2447 +       if (IS_ERR(chan_dev->dev)) {
2448 +               err = PTR_ERR(chan_dev->dev);
2449 +               goto free;
2450 +       }
2451 +
2452 +       cdev_init(&chan_dev->cdev, &chan_fops);
2453 +       chan_dev->cdev.owner = THIS_MODULE;
2454 +       if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
2455 +               goto destroy_device;
2456 +
2457 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2458 +               if (channels[ch])
2459 +                       port->channels[ch] = id;
2460 +       port->chan_devices[id] = chan_dev;
2461 +       dev_set_drvdata(chan_dev->dev, chan_dev);
2462 +       BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
2463 +
2464 +       spin_unlock_irqrestore(&npe_lock, flags);
2465 +       return orig_len;
2466 +
2467 +destroy_device:
2468 +       device_unregister(chan_dev->dev);
2469 +free:
2470 +       kfree(chan_dev);
2471 +       spin_unlock_irqrestore(&npe_lock, flags);
2472 +       return err;
2473 +}
2474 +
2475 +static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
2476 +                             char *buf)
2477 +{
2478 +       return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
2479 +}
2480 +
2481 +static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
2482 +                            const char *buf, size_t len)
2483 +{
2484 +       struct port *port = dev_get_drvdata(dev);
2485 +       u8 channels[MAX_CHANNELS];
2486 +       size_t orig_len = len;
2487 +       unsigned long flags;
2488 +       unsigned int ch;
2489 +       int err;
2490 +
2491 +       if ((err = parse_channels(&buf, &len, channels)) < 0)
2492 +               return err;
2493 +
2494 +       spin_lock_irqsave(&npe_lock, flags);
2495 +
2496 +       if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2497 +               err = -EINVAL;
2498 +               goto err;
2499 +       }
2500 +
2501 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2502 +               if (channels[ch] &&
2503 +                   port->channels[ch] != CHANNEL_UNUSED &&
2504 +                   port->channels[ch] != CHANNEL_HDLC) {
2505 +                       printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2506 +                       err = -EBUSY;
2507 +                       goto err;
2508 +               }
2509 +
2510 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2511 +               if (channels[ch])
2512 +                       port->channels[ch] = CHANNEL_HDLC;
2513 +               else if (port->channels[ch] == CHANNEL_HDLC)
2514 +                       port->channels[ch] = CHANNEL_UNUSED;
2515 +
2516 +       if (port->chan_open_count || port->hdlc_open) {
2517 +               hss_config_set_lut(port);
2518 +               hss_config_load(port);
2519 +       }
2520 +
2521 +       spin_unlock_irqrestore(&npe_lock, flags);
2522 +       return orig_len;
2523 +
2524 +err:
2525 +       spin_unlock_irqrestore(&npe_lock, flags);
2526 +       return err;
2527 +}
2528 +
2529 +static ssize_t show_clock_type(struct device *dev,
2530 +                              struct device_attribute *attr, char *buf)
2531 +{
2532 +       struct port *port = dev_get_drvdata(dev);
2533 +
2534 +       strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
2535 +       return 5;
2536 +}
2537 +
2538 +static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
2539 +                             const char *buf, size_t len)
2540 +{
2541 +       struct port *port = dev_get_drvdata(dev);
2542 +       size_t orig_len = len;
2543 +       unsigned long flags;
2544 +       unsigned int clk, err;
2545 +
2546 +       if (len && buf[len - 1] == '\n')
2547 +               len--;
2548 +
2549 +       if (len != 3)
2550 +               return -EINVAL;
2551 +       if (!memcmp(buf, "ext", 3))
2552 +               clk = CLOCK_EXT;
2553 +       else if (!memcmp(buf, "int", 3))
2554 +               clk = CLOCK_INT;
2555 +       else
2556 +               return -EINVAL;
2557 +
2558 +       spin_lock_irqsave(&npe_lock, flags);
2559 +       if (port->plat->set_clock)
2560 +               clk = port->plat->set_clock(port->id, clk);
2561 +       if (clk != CLOCK_EXT && clk != CLOCK_INT) {
2562 +               err = -EINVAL; /* plat->set_clock shouldn't change the state */
2563 +               goto err;
2564 +       }
2565 +       port->clock_type = clk;
2566 +       if (port->chan_open_count || port->hdlc_open) {
2567 +               hss_config_set_line(port);
2568 +               hss_config_load(port);
2569 +       }
2570 +       spin_unlock_irqrestore(&npe_lock, flags);
2571 +
2572 +       return orig_len;
2573 +err:
2574 +       spin_unlock_irqrestore(&npe_lock, flags);
2575 +       return err;
2576 +}
2577 +
2578 +static ssize_t show_clock_rate(struct device *dev,
2579 +                              struct device_attribute *attr, char *buf)
2580 +{
2581 +       struct port *port = dev_get_drvdata(dev);
2582 +
2583 +       sprintf(buf, "%u\n", port->clock_rate);
2584 +       return strlen(buf) + 1;
2585 +}
2586 +
2587 +static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
2588 +                             const char *buf, size_t len)
2589 +{
2590 +#if 0
2591 +       struct port *port = dev_get_drvdata(dev);
2592 +       size_t orig_len = len;
2593 +       unsigned long flags;
2594 +       unsigned int rate;
2595 +
2596 +       if (len && buf[len - 1] == '\n')
2597 +               len--;
2598 +
2599 +       if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
2600 +               return -EINVAL;
2601 +       if (len)
2602 +               return -EINVAL;
2603 +
2604 +       spin_lock_irqsave(&npe_lock, flags);
2605 +       port->clock_rate = rate;
2606 +       spin_unlock_irqrestore(&npe_lock, flags);
2607 +       return orig_len;
2608 +#endif
2609 +       return -EINVAL; /* FIXME not yet supported */
2610 +}
2611 +
2612 +static ssize_t show_frame_size(struct device *dev,
2613 +                              struct device_attribute *attr, char *buf)
2614 +{
2615 +       struct port *port = dev_get_drvdata(dev);
2616 +
2617 +       if (port->mode != MODE_RAW && port->mode != MODE_G704)
2618 +               return -EINVAL;
2619 +
2620 +       sprintf(buf, "%u\n", port->frame_size);
2621 +       return strlen(buf) + 1;
2622 +}
2623 +
2624 +static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
2625 +                             const char *buf, size_t len)
2626 +{
2627 +       struct port *port = dev_get_drvdata(dev);
2628 +       size_t ret = len;
2629 +       unsigned long flags;
2630 +       unsigned int size;
2631 +
2632 +       if (len && buf[len - 1] == '\n')
2633 +               len--;
2634 +
2635 +       if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
2636 +               return -EINVAL;
2637 +       if (len || size % 8 > 1)
2638 +               return -EINVAL;
2639 +
2640 +       spin_lock_irqsave(&npe_lock, flags);
2641 +       if (port->mode != MODE_RAW && port->mode != MODE_G704)
2642 +               ret = -EINVAL;
2643 +       else if (!port->chan_open_count && !port->hdlc_open)
2644 +               ret = -EBUSY;
2645 +       else {
2646 +               port->frame_size = size;
2647 +               port->frame_sync_offset = 0;
2648 +       }
2649 +       spin_unlock_irqrestore(&npe_lock, flags);
2650 +       return ret;
2651 +}
2652 +
2653 +static ssize_t show_frame_offset(struct device *dev,
2654 +                                struct device_attribute *attr, char *buf)
2655 +{
2656 +       struct port *port = dev_get_drvdata(dev);
2657 +
2658 +       sprintf(buf, "%u\n", port->frame_sync_offset);
2659 +       return strlen(buf) + 1;
2660 +}
2661 +
2662 +static ssize_t set_frame_offset(struct device *dev,
2663 +                               struct device_attribute *attr,
2664 +                               const char *buf, size_t len)
2665 +{
2666 +       struct port *port = dev_get_drvdata(dev);
2667 +       size_t orig_len = len;
2668 +       unsigned long flags;
2669 +       unsigned int offset;
2670 +
2671 +       if (len && buf[len - 1] == '\n')
2672 +               len--;
2673 +
2674 +       if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
2675 +               return -EINVAL;
2676 +       if (len)
2677 +               return -EINVAL;
2678 +
2679 +       spin_lock_irqsave(&npe_lock, flags);
2680 +
2681 +       port->frame_sync_offset = offset;
2682 +       if (port->chan_open_count || port->hdlc_open) {
2683 +               hss_config_set_rx_frame(port);
2684 +               hss_config_load(port);
2685 +       }
2686 +
2687 +       spin_unlock_irqrestore(&npe_lock, flags);
2688 +       return orig_len;
2689 +}
2690 +
2691 +static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
2692 +                            char *buf)
2693 +{
2694 +       struct port *port = dev_get_drvdata(dev);
2695 +
2696 +       sprintf(buf, "%u\n", port->loopback);
2697 +       return strlen(buf) + 1;
2698 +}
2699 +
2700 +static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
2701 +                           const char *buf, size_t len)
2702 +{
2703 +       struct port *port = dev_get_drvdata(dev);
2704 +       size_t orig_len = len;
2705 +       unsigned long flags;
2706 +       unsigned int lb;
2707 +
2708 +       if (len && buf[len - 1] == '\n')
2709 +               len--;
2710 +
2711 +       if (get_number(&buf, &len, &lb, 0, 1))
2712 +               return -EINVAL;
2713 +       if (len)
2714 +               return -EINVAL;
2715 +
2716 +       spin_lock_irqsave(&npe_lock, flags);
2717 +
2718 +       if (port->loopback != lb) {
2719 +               port->loopback = lb;
2720 +               if (port->chan_open_count || port->hdlc_open) {
2721 +                       hss_config_set_core(port);
2722 +                       hss_config_load(port);
2723 +               }
2724 +               if (port->loopback || port->carrier)
2725 +                       netif_carrier_on(port->netdev);
2726 +               else
2727 +                       netif_carrier_off(port->netdev);
2728 +       }
2729 +
2730 +       spin_unlock_irqrestore(&npe_lock, flags);
2731 +       return orig_len;
2732 +}
2733 +
2734 +static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
2735 +                        char *buf)
2736 +{
2737 +       struct port *port = dev_get_drvdata(dev);
2738 +
2739 +       switch(port->mode) {
2740 +       case MODE_RAW:
2741 +               strcpy(buf, "raw\n");
2742 +               break;
2743 +       case MODE_G704:
2744 +               strcpy(buf, "g704\n");
2745 +               break;
2746 +       default:
2747 +               strcpy(buf, "hdlc\n");
2748 +               break;
2749 +       }
2750 +       return strlen(buf) + 1;
2751 +}
2752 +
2753 +static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
2754 +                       const char *buf, size_t len)
2755 +{
2756 +       struct port *port = dev_get_drvdata(dev);
2757 +       size_t ret = len;
2758 +       unsigned long flags;
2759 +
2760 +       if (len && buf[len - 1] == '\n')
2761 +               len--;
2762 +
2763 +       spin_lock_irqsave(&npe_lock, flags);
2764 +
2765 +       if (port->chan_open_count || port->hdlc_open) {
2766 +               ret = -EBUSY;
2767 +       } else if (len == 4 && !memcmp(buf, "hdlc", 4))
2768 +               port->mode = MODE_HDLC;
2769 +       else if (len == 3 && !memcmp(buf, "raw", 3))
2770 +               port->mode = MODE_RAW;
2771 +       else if (len == 4 && !memcmp(buf, "g704", 4))
2772 +               port->mode = MODE_G704;
2773 +       else
2774 +               ret = -EINVAL;
2775 +
2776 +       spin_unlock_irqrestore(&npe_lock, flags);
2777 +       return ret;
2778 +}
2779 +
2780 +static struct device_attribute hss_attrs[] = {
2781 +       __ATTR(create_chan, 0200, NULL, create_chan),
2782 +       __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
2783 +       __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
2784 +       __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
2785 +       __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
2786 +       __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
2787 +       __ATTR(loopback, 0644, show_loopback, set_loopback),
2788 +       __ATTR(mode, 0644, show_mode, set_mode),
2789 +};
2790 +
2791 +/*****************************************************************************
2792 + * initialization
2793 + ****************************************************************************/
2794 +
2795 +static int __devinit hss_init_one(struct platform_device *pdev)
2796 +{
2797 +       struct port *port;
2798 +       struct net_device *dev;
2799 +       hdlc_device *hdlc;
2800 +       int i, err;
2801 +
2802 +       if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
2803 +               return -ENOMEM;
2804 +       platform_set_drvdata(pdev, port);
2805 +       port->id = pdev->id;
2806 +
2807 +       if ((port->npe = npe_request(0)) == NULL) {
2808 +               err = -ENOSYS;
2809 +               goto err_free;
2810 +       }
2811 +
2812 +       port->dev = &pdev->dev;
2813 +       port->plat = pdev->dev.platform_data;
2814 +       if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
2815 +               err = -ENOMEM;
2816 +               goto err_plat;
2817 +       }
2818 +
2819 +       SET_NETDEV_DEV(dev, &pdev->dev);
2820 +       hdlc = dev_to_hdlc(dev);
2821 +       hdlc->attach = hss_hdlc_attach;
2822 +       hdlc->xmit = hss_hdlc_xmit;
2823 +       dev->open = hss_hdlc_open;
2824 +       dev->stop = hss_hdlc_close;
2825 +       dev->do_ioctl = hss_hdlc_ioctl;
2826 +       dev->tx_queue_len = 100;
2827 +       port->clock_type = CLOCK_EXT;
2828 +       port->clock_rate = 2048000;
2829 +       port->frame_size = 256; /* E1 */
2830 +       memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
2831 +       init_waitqueue_head(&port->chan_tx_waitq);
2832 +       init_waitqueue_head(&port->chan_rx_waitq);
2833 +       netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
2834 +
2835 +       if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
2836 +               goto err_free_netdev;
2837 +
2838 +       for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2839 +               BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
2840 +
2841 +       printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
2842 +       return 0;
2843 +
2844 +err_free_netdev:
2845 +       free_netdev(dev);
2846 +err_plat:
2847 +       npe_release(port->npe);
2848 +       platform_set_drvdata(pdev, NULL);
2849 +err_free:
2850 +       kfree(port);
2851 +       return err;
2852 +}
2853 +
2854 +static int __devexit hss_remove_one(struct platform_device *pdev)
2855 +{
2856 +       struct port *port = platform_get_drvdata(pdev);
2857 +       int i;
2858 +
2859 +       for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2860 +               device_remove_file(port->dev, &hss_attrs[i]);
2861 +
2862 +       unregister_hdlc_device(port->netdev);
2863 +       free_netdev(port->netdev);
2864 +       npe_release(port->npe);
2865 +       platform_set_drvdata(pdev, NULL);
2866 +       kfree(port);
2867 +       return 0;
2868 +}
2869 +
2870 +static struct platform_driver drv = {
2871 +       .driver.name    = DRV_NAME,
2872 +       .probe          = hss_init_one,
2873 +       .remove         = hss_remove_one,
2874 +};
2875 +
2876 +static int __init hss_init_module(void)
2877 +{
2878 +       int err;
2879 +       dev_t rdev;
2880 +
2881 +       if ((ixp4xx_read_feature_bits() &
2882 +            (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
2883 +           (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
2884 +               return -ENOSYS;
2885 +
2886 +       if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
2887 +                                      "hss")))
2888 +               return err;
2889 +
2890 +       spin_lock_init(&npe_lock);
2891 +
2892 +       if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
2893 +               printk(KERN_ERR "Can't register device class 'hss'\n");
2894 +               err = PTR_ERR(hss_class);
2895 +               goto free_chrdev;
2896 +       }
2897 +       if ((err = platform_driver_register(&drv)))
2898 +               goto destroy_class;
2899 +
2900 +       chan_major = MAJOR(rdev);
2901 +       return 0;
2902 +
2903 +destroy_class:
2904 +       class_destroy(hss_class);
2905 +free_chrdev:
2906 +       unregister_chrdev_region(MKDEV(chan_major, 0),
2907 +                                HSS_COUNT * MAX_CHAN_DEVICES);
2908 +       return err;
2909 +}
2910 +
2911 +static void __exit hss_cleanup_module(void)
2912 +{
2913 +       platform_driver_unregister(&drv);
2914 +       class_destroy(hss_class);
2915 +       unregister_chrdev_region(MKDEV(chan_major, 0),
2916 +                                HSS_COUNT * MAX_CHAN_DEVICES);
2917 +}
2918 +
2919 +MODULE_AUTHOR("Krzysztof Halasa");
2920 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
2921 +MODULE_LICENSE("GPL v2");
2922 +MODULE_ALIAS("platform:ixp4xx_hss");
2923 +module_init(hss_init_module);
2924 +module_exit(hss_cleanup_module);