target/linux/lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Thu, 19 Jan 2017 12:14:44 +0100
   3 Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
   4
   5 With the IRQ stack changes integrated, the XRX200 devices started
   6 emitting a constant stream of kernel messages like this:
   7
   8 [  565.415310] Spurious IRQ: CAUSE=0x1100c300
   9
  10 This appears to be caused by IP0 firing for some reason without being
  11 handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
  12 calling do_IRQ for all MIPS CPU interrupts.
  13
  14 Cc: john@phrozen.org
  15 Cc: stable@vger.kernel.org
  16 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  17 ---
  18
  19 --- a/arch/mips/lantiq/irq.c
  20 +++ b/arch/mips/lantiq/irq.c
  21 @@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
  22  DEFINE_HWx_IRQDISPATCH(5)
  23  #endif
  24
  25 +static void ltq_hw_irq_handler(struct irq_desc *desc)
  26 +{
  27 +       ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
  28 +}
  29 +
  30  #ifdef CONFIG_MIPS_MT_SMP
  31  void __init arch_init_ipiirq(int irq, struct irqaction *action)
  32  {
  33 @@ -315,23 +320,19 @@ static struct irqaction irq_call = {
  34  asmlinkage void plat_irq_dispatch(void)
  35  {
  36         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  37 -       unsigned int i;
  38 +       int irq;
  39
  40 -       if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
  41 -               do_IRQ(MIPS_CPU_TIMER_IRQ);
  42 -               goto out;
  43 -       } else {
  44 -               for (i = 0; i < MAX_IM; i++) {
  45 -                       if (pending & (CAUSEF_IP2 << i)) {
  46 -                               ltq_hw_irqdispatch(i);
  47 -                               goto out;
  48 -                       }
  49 -               }
  50 +       if (!pending) {
  51 +               spurious_interrupt();
  52 +               return;
  53         }
  54 -       pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
  55
  56 -out:
  57 -       return;
  58 +       pending >>= CAUSEB_IP;
  59 +       while (pending) {
  60 +               irq = fls(pending) - 1;
  61 +               do_IRQ(MIPS_CPU_IRQ_BASE + irq);
  62 +               pending &= ~BIT(irq);
  63 +       }
  64  }
  65
  66  static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  67 @@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
  68         .map = icu_map,
  69  };
  70
  71 -static struct irqaction cascade = {
  72 -       .handler = no_action,
  73 -       .name = "cascade",
  74 -};
  75 -
  76  int __init icu_of_init(struct device_node *node, struct device_node *parent)
  77  {
  78         struct device_node *eiu_node;
  79 @@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
  80         mips_cpu_irq_init();
  81
  82         for (i = 0; i < MAX_IM; i++)
  83 -               setup_irq(i + 2, &cascade);
  84 +               irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
  85
  86         if (cpu_has_vint) {
  87                 pr_info("Setting up vectored interrupts\n");