target/linux/layerscape/patches-4.4/1099-mtd-spi-nor-fsl-quadspi-Add-fast-read-mode-support.patch

   1 From c501cdf57682265b72a8180c06e4a01dc2978375 Mon Sep 17 00:00:00 2001
   2 From: Yunhui Cui <B56489@freescale.com>
   3 Date: Mon, 1 Feb 2016 18:26:23 +0800
   4 Subject: [PATCH 099/113] mtd:spi-nor:fsl-quadspi:Add fast-read mode support
   5
   6 The qspi driver add generic fast-read mode for different
   7 flash venders. There are some different board flash work on
   8 different mode, such fast-read, quad-mode.
   9 So we have to modify the third entrace parameter of spi_nor_scan().
  10
  11 Signed-off-by: Yunhui Cui <B56489@freescale.com>
  12 ---
  13  drivers/mtd/spi-nor/fsl-quadspi.c |   27 +++++++++++++++++++++------
  14  1 file changed, 21 insertions(+), 6 deletions(-)
  15
  16 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  17 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  18 @@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl
  19         /* Read */
  20         lut_base = SEQID_READ * 4;
  21
  22 -       qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
  23 -                       base + QUADSPI_LUT(lut_base));
  24 -       qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
  25 -                   LUT1(FSL_READ, PAD4, rxfifo),
  26 -                       base + QUADSPI_LUT(lut_base + 1));
  27 +       if (nor->flash_read == SPI_NOR_FAST) {
  28 +               qspi_writel(q, LUT0(CMD, PAD1, read_op) |
  29 +                           LUT1(ADDR, PAD1, addrlen),
  30 +                               base + QUADSPI_LUT(lut_base));
  31 +               qspi_writel(q,  LUT0(DUMMY, PAD1, read_dm) |
  32 +                           LUT1(FSL_READ, PAD1, rxfifo),
  33 +                               base + QUADSPI_LUT(lut_base + 1));
  34 +       } else if (nor->flash_read == SPI_NOR_QUAD) {
  35 +               qspi_writel(q, LUT0(CMD, PAD1, read_op) |
  36 +                           LUT1(ADDR, PAD1, addrlen),
  37 +                               base + QUADSPI_LUT(lut_base));
  38 +               qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
  39 +                           LUT1(FSL_READ, PAD4, rxfifo),
  40 +                               base + QUADSPI_LUT(lut_base + 1));
  41 +       }
  42
  43         /* Write enable */
  44         lut_base = SEQID_WREN * 4;
  45 @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl
  46  {
  47         switch (cmd) {
  48         case SPINOR_OP_READ_1_1_4:
  49 +       case SPINOR_OP_READ_FAST:
  50                 return SEQID_READ;
  51         case SPINOR_OP_WREN:
  52                 return SEQID_WREN;
  53 @@ -964,6 +975,7 @@ static int fsl_qspi_probe(struct platfor
  54         struct spi_nor *nor;
  55         struct mtd_info *mtd;
  56         int ret, i = 0;
  57 +       enum read_mode mode = SPI_NOR_QUAD;
  58
  59         q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
  60         if (!q)
  61 @@ -1065,7 +1077,10 @@ static int fsl_qspi_probe(struct platfor
  62                 /* set the chip address for READID */
  63                 fsl_qspi_set_base_addr(q, nor);
  64
  65 -               ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
  66 +               ret = of_property_read_bool(np, "m25p,fast-read");
  67 +               mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
  68 +
  69 +               ret = spi_nor_scan(nor, NULL, mode);
  70                 if (ret)
  71                         goto mutex_failed;
  72