target/linux/mpc83xx/patches-3.3/200-powerpc-add-rbppc-support.patch

   1 --- a/arch/powerpc/boot/Makefile
   2 +++ b/arch/powerpc/boot/Makefile
   3 @@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
   4                 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
   5                 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
   6                 fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
   7 -               cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
   8 +               cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c rb333.c \
   9                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
  10                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
  11                 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
  12 @@ -242,6 +242,8 @@ image-$(CONFIG_MPC834x_ITX)         += cuImage.
  13  image-$(CONFIG_MPC834x_MDS)            += cuImage.mpc834x_mds
  14  image-$(CONFIG_MPC836x_MDS)            += cuImage.mpc836x_mds
  15  image-$(CONFIG_ASP834x)                        += dtbImage.asp834x-redboot
  16 +image-$(CONFIG_RB_PPC)                 += dtbImage.rb600 \
  17 +                                          dtbImage.rb333
  18
  19  # Board ports in arch/powerpc/platform/85xx/Kconfig
  20  image-$(CONFIG_MPC8540_ADS)            += cuImage.mpc8540ads
  21 --- /dev/null
  22 +++ b/arch/powerpc/boot/dts/rb600.dts
  23 @@ -0,0 +1,283 @@
  24 +/*
  25 + * RouterBOARD 600 series Device Tree Source
  26 + *
  27 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
  28 + *
  29 + * This program is free software; you can redistribute  it and/or modify it
  30 + * under  the terms of  the GNU General  Public License as published by the
  31 + * Free Software Foundation;  either version 2 of the  License, or (at your
  32 + * option) any later version.
  33 + */
  34 +
  35 +/dts-v1/;
  36 +
  37 +/ {
  38 +       model = "RB600";
  39 +       compatible = "MPC83xx";
  40 +       #address-cells = <1>;
  41 +       #size-cells = <1>;
  42 +
  43 +       aliases {
  44 +               ethernet0 = &enet0;
  45 +               ethernet1 = &enet1;
  46 +               pci0 = &pci0;
  47 +       };
  48 +
  49 +       chosen {
  50 +               bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
  51 +               linux,stdout-path = "/soc8343@e0000000/serial@4500";
  52 +       };
  53 +
  54 +       cpus {
  55 +               #address-cells = <1>;
  56 +               #size-cells = <0>;
  57 +
  58 +               PowerPC,8343E@0 {
  59 +                       device_type = "cpu";
  60 +                       reg = <0x0>;
  61 +                       d-cache-line-size = <0x20>;
  62 +                       i-cache-line-size = <0x20>;
  63 +                       d-cache-size = <0x8000>;
  64 +                       i-cache-size = <0x8000>;
  65 +                       timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
  66 +                       clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
  67 +               };
  68 +       };
  69 +
  70 +       memory {
  71 +               device_type = "memory";
  72 +               reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
  73 +       };
  74 +
  75 +       cf@f9200000 {
  76 +               lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
  77 +               interrupt-at-level = <0x0>;
  78 +               interrupt-parent = <&ipic>;
  79 +               interrupts = <0x16 0x8>;
  80 +               lbc_extra_divider = <0x1>;
  81 +               reg = <0xf9200000 0x200000>;
  82 +               device_type = "rb,cf";
  83 +       };
  84 +
  85 +       cf@f9000000 {
  86 +               lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
  87 +               interrupt-at-level = <0x0>;
  88 +               interrupt-parent = <&ipic>;
  89 +               interrupts = <0x14 0x8>;
  90 +               lbc_extra_divider = <0x1>;
  91 +               reg = <0xf9000000 0x200000>;
  92 +               device_type = "rb,cf";
  93 +       };
  94 +
  95 +       flash {
  96 +               reg = <0xff800000 0x20000>;
  97 +       };
  98 +
  99 +       nnand {
 100 +               reg = <0xf0000000 0x1000>;
 101 +       };
 102 +
 103 +       nand {
 104 +               ale = <&gpio 0x6>;
 105 +               cle = <&gpio 0x5>;
 106 +               nce = <&gpio 0x4>;
 107 +               rdy = <&gpio 0x3>;
 108 +               reg = <0xf8000000 0x1000>;
 109 +               device_type = "rb,nand";
 110 +       };
 111 +
 112 +       fancon {
 113 +               interrupt-parent = <&ipic>;
 114 +               interrupts = <0x17 0x8>;
 115 +               sense = <&gpio 0x7>;
 116 +               fan_on = <&gpio 0x9>;
 117 +       };
 118 +
 119 +       pci0: pci@e0008500 {
 120 +               device_type = "pci";
 121 +               compatible = "fsl,mpc8349-pci";
 122 +               reg = <0xe0008500 0x100 0xe0008300 0x8>;
 123 +               #address-cells = <3>;
 124 +               #size-cells = <2>;
 125 +               #interrupt-cells = <1>;
 126 +               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
 127 +               bus-range = <0x0 0x0>;
 128 +               interrupt-map = <
 129 +                       0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
 130 +                       0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
 131 +                       0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
 132 +                       0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
 133 +                       0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
 134 +                       0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
 135 +                       0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
 136 +                       0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
 137 +                       0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
 138 +                       0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
 139 +                       0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
 140 +                       0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
 141 +                       0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
 142 +                       0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
 143 +                       0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
 144 +                       0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
 145 +                       0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
 146 +                       0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
 147 +                       0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
 148 +                       0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
 149 +                       0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
 150 +               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 151 +               interrupt-parent = <&ipic>;
 152 +       };
 153 +
 154 +       soc8343@e0000000 {
 155 +               #address-cells = <1>;
 156 +               #size-cells = <1>;
 157 +               device_type = "soc";
 158 +               compatible = "simple-bus";
 159 +               ranges = <0x0 0xe0000000 0x100000>;
 160 +               reg = <0xe0000000 0x200>;
 161 +               bus-frequency = <0x1>;
 162 +
 163 +               led {
 164 +                       user_led = <0x400 0x8>;
 165 +               };
 166 +
 167 +               beeper {
 168 +                       reg = <0x500 0x100>;
 169 +               };
 170 +
 171 +               gpio: gpio@0 {
 172 +                       reg = <0xc08 0x4>;
 173 +                       device-id = <0x0>;
 174 +                       compatible = "gpio";
 175 +                       device_type = "gpio";
 176 +               };
 177 +
 178 +               dma@82a8 {
 179 +                        #address-cells = <1>;
 180 +                        #size-cells = <1>;
 181 +                        compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
 182 +                        reg = <0x82a8 4>;
 183 +                        ranges = <0 0x8100 0x1a8>;
 184 +                        interrupt-parent = <&ipic>;
 185 +                        interrupts = <71 8>;
 186 +                        cell-index = <0>;
 187 +                        dma-channel@0 {
 188 +                                compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 189 +                                reg = <0 0x80>;
 190 +                                cell-index = <0>;
 191 +                                interrupt-parent = <&ipic>;
 192 +                                interrupts = <71 8>;
 193 +                        };
 194 +                        dma-channel@80 {
 195 +                                compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 196 +                                reg = <0x80 0x80>;
 197 +                                cell-index = <1>;
 198 +                                interrupt-parent = <&ipic>;
 199 +                                interrupts = <71 8>;
 200 +                        };
 201 +                        dma-channel@100 {
 202 +                                compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 203 +                                reg = <0x100 0x80>;
 204 +                                cell-index = <2>;
 205 +                                interrupt-parent = <&ipic>;
 206 +                                interrupts = <71 8>;
 207 +                        };
 208 +                        dma-channel@180 {
 209 +                                compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 210 +                                reg = <0x180 0x28>;
 211 +                                cell-index = <3>;
 212 +                                interrupt-parent = <&ipic>;
 213 +                                interrupts = <71 8>;
 214 +                        };
 215 +                };
 216 +
 217 +               enet0: ethernet@25000 {
 218 +                       #address-cells = <1>;
 219 +                       #size-cells = <1>;
 220 +                       cell-index = <0>;
 221 +                       phy-handle = <&phy0>;
 222 +                       tbi-handle = <&tbi0>;
 223 +                       interrupt-parent = <&ipic>;
 224 +                       interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
 225 +                       local-mac-address = [00 00 00 00 00 00];
 226 +                       reg = <0x25000 0x1000>;
 227 +                       ranges = <0x0 0x25000 0x1000>;
 228 +                       compatible = "gianfar";
 229 +                       model = "TSEC";
 230 +                       device_type = "network";
 231 +
 232 +                       mdio@520 {
 233 +                               #address-cells = <1>;
 234 +                               #size-cells = <0>;
 235 +                               compatible = "fsl,gianfar-tbi";
 236 +                               reg = <0x520 0x20>;
 237 +
 238 +                               tbi0: tbi-phy@11 {
 239 +                                       reg = <0x11>;
 240 +                                       device_type = "tbi-phy";
 241 +                               };
 242 +                       };
 243 +               };
 244 +
 245 +               enet1: ethernet@24000 {
 246 +                       #address-cells = <1>;
 247 +                       #size-cells = <1>;
 248 +                       cell-index = <1>;
 249 +                       phy-handle = <&phy1>;
 250 +                       tbi-handle = <&tbi1>;
 251 +                       interrupt-parent = <&ipic>;
 252 +                       interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
 253 +                       local-mac-address = [00 00 00 00 00 00];
 254 +                       reg = <0x24000 0x1000>;
 255 +                       ranges = <0x0 0x24000 0x1000>;
 256 +                       compatible = "gianfar";
 257 +                       model = "TSEC";
 258 +                       device_type = "network";
 259 +
 260 +                       mdio@520 {
 261 +                               #size-cells = <0x0>;
 262 +                               #address-cells = <0x1>;
 263 +                               reg = <0x520 0x20>;
 264 +                               compatible = "fsl,gianfar-mdio";
 265 +
 266 +                               phy0: ethernet-phy@0 {
 267 +                                       device_type = "ethernet-phy";
 268 +                                       reg = <0x0>;
 269 +                               };
 270 +
 271 +                               phy1: ethernet-phy@1 {
 272 +                                       device_type = "ethernet-phy";
 273 +                                       reg = <0x1>;
 274 +                               };
 275 +
 276 +                               tbi1: tbi-phy@11 {
 277 +                                       reg = <0x11>;
 278 +                                       device_type = "tbi-phy";
 279 +                               };
 280 +                       };
 281 +               };
 282 +
 283 +               ipic: pic@700 {
 284 +                       interrupt-controller;
 285 +                       #address-cells = <0>;
 286 +                       #interrupt-cells = <2>;
 287 +                       reg = <0x700 0x100>;
 288 +                       device_type = "ipic";
 289 +               };
 290 +
 291 +               serial@4500 {
 292 +                       interrupt-parent = <&ipic>;
 293 +                       interrupts = <0x9 0x8>;
 294 +                       clock-frequency = <0xfe4f840>;
 295 +                       reg = <0x4500 0x100>;
 296 +                       compatible = "ns16550";
 297 +                       device_type = "serial";
 298 +               };
 299 +
 300 +               wdt@200 {
 301 +                       reg = <0x200 0x100>;
 302 +                       compatible = "mpc83xx_wdt";
 303 +                       device_type = "watchdog";
 304 +               };
 305 +       };
 306 +};
 307 --- /dev/null
 308 +++ b/arch/powerpc/boot/rb600.c
 309 @@ -0,0 +1,72 @@
 310 +/*
 311 + * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
 312 + *
 313 + * Author: Michael Guntsche <mike@it-loops.com>
 314 + *
 315 + * Copyright (c) 2009 Michael Guntsche
 316 + *
 317 + * This program is free software; you can redistribute it and/or modify it
 318 + * under the terms of the GNU General Public License version 2 as published
 319 + * by the Free Software Foundation.
 320 + */
 321 +
 322 +#include "ops.h"
 323 +#include "types.h"
 324 +#include "io.h"
 325 +#include "stdio.h"
 326 +#include <libfdt.h>
 327 +
 328 +BSS_STACK(4*1024);
 329 +
 330 +u64 memsize64;
 331 +const void *fw_dtb;
 332 +
 333 +static void rb600_fixups(void)
 334 +{
 335 +       const u32 *reg, *timebase, *clock;
 336 +       int node, size;
 337 +       void *chosen;
 338 +       const char* bootargs;
 339 +
 340 +       dt_fixup_memory(0, memsize64);
 341 +
 342 +       /* Set the MAC addresses. */
 343 +       node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
 344 +       reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
 345 +       dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
 346 +
 347 +       node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
 348 +       reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
 349 +       dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
 350 +
 351 +       /* Find the CPU timebase and clock frequencies. */
 352 +       node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
 353 +       timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
 354 +       clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
 355 +       dt_fixup_cpu_clocks(*clock, *timebase, 0);
 356 +
 357 +}
 358 +
 359 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 360 +                  unsigned long r6, unsigned long r7)
 361 +{
 362 +       const u32 *reg;
 363 +       int node, size;
 364 +
 365 +       fw_dtb = (const void *)r3;
 366 +
 367 +       /* Find the memory range. */
 368 +       node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
 369 +       reg = fdt_getprop(fw_dtb, node, "reg", &size);
 370 +       memsize64 = reg[1];
 371 +
 372 +       /* Now we have the memory size; initialize the heap. */
 373 +       simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
 374 +
 375 +       /* Prepare the device tree and find the console. */
 376 +       fdt_init(_dtb_start);
 377 +       serial_console_init();
 378 +
 379 +       /* Remaining fixups... */
 380 +       platform_ops.fixups = rb600_fixups;
 381 +}
 382 --- a/arch/powerpc/boot/wrapper
 383 +++ b/arch/powerpc/boot/wrapper
 384 @@ -215,7 +215,7 @@ ps3)
 385      link_address=''
 386      pie=
 387      ;;
 388 -ep88xc|ep405|ep8248e)
 389 +ep88xc|ep405|ep8248e|rb600|rb333)
 390      platformo="$object/fixed-head.o $object/$platform.o"
 391      binary=y
 392      ;;
 393 --- a/arch/powerpc/platforms/83xx/Kconfig
 394 +++ b/arch/powerpc/platforms/83xx/Kconfig
 395 @@ -38,6 +38,15 @@ config MPC832x_RDB
 396         help
 397           This option enables support for the MPC8323 RDB board.
 398
 399 +config RB_PPC
 400 +       bool "MikroTik RouterBOARD 333/600 series"
 401 +       select DEFAULT_UIMAGE
 402 +       select QUICC_ENGINE
 403 +       select PPC_MPC832x
 404 +       select PPC_MPC834x
 405 +       help
 406 +         This option enables support for MikroTik RouterBOARD 333/600 series boards.
 407 +
 408  config MPC834x_MDS
 409         bool "Freescale MPC834x MDS"
 410         select DEFAULT_UIMAGE
 411 --- /dev/null
 412 +++ b/arch/powerpc/boot/dts/rb333.dts
 413 @@ -0,0 +1,432 @@
 414 +
 415 +/*
 416 + * RouterBOARD 333 series Device Tree Source
 417 + *
 418 + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
 419 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
 420 + *
 421 + * This program is free software; you can redistribute  it and/or modify it
 422 + * under  the terms of  the GNU General  Public License as published by the
 423 + * Free Software Foundation;  either version 2 of the  License, or (at your
 424 + * option) any later version.
 425 + *
 426 + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
 427 + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
 428 + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
 429 + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
 430 + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
 431 + *
 432 + */
 433 +
 434 +
 435 +/dts-v1/;
 436 +
 437 +/ {
 438 +       model = "RB333";
 439 +       compatible = "MPC83xx";
 440 +       #size-cells = <1>;
 441 +       #address-cells = <1>;
 442 +
 443 +
 444 +       aliases {
 445 +               ethernet0 = &enet0;
 446 +               ethernet1 = &enet1;
 447 +               ethernet2 = &enet2;
 448 +               pci0 = &pci0;
 449 +       };
 450 +
 451 +
 452 +       chosen {
 453 +               bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
 454 +               // linux,platform = <0x8062>;
 455 +               // linux,initrd = <0x488000 0x0>;
 456 +               linux,stdout-path = "/soc8323@e0000000/serial@4500";
 457 +               // interrupt-controller = <&ipic>;
 458 +       };
 459 +
 460 +        cpus {
 461 +                #cpus = <1>;
 462 +                #size-cells = <0>;
 463 +                #address-cells = <1>;
 464 +
 465 +                PowerPC,8323E@0 {
 466 +                        device_type = "cpu";
 467 +                        reg = <0x0>;
 468 +                        i-cache-size = <0x4000>;
 469 +                        d-cache-size = <0x4000>;
 470 +                        i-cache-line-size = <0x20>;
 471 +                        d-cache-line-size = <0x20>;
 472 +                        // clock-frequency = <0x13de3650>;
 473 +                        // timebase-frequency = <0x1fc9f08>;
 474 +                       timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
 475 +                       clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
 476 +                       32-bit;
 477 +                };
 478 +        };
 479 +
 480 +        memory {
 481 +                device_type = "memory";
 482 +                reg = <0x0 0x4000000>;
 483 +                // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
 484 +        };
 485 +
 486 +       flash {
 487 +               reg = <0xfe000000 0x20000>;
 488 +       };
 489 +
 490 +       nand {
 491 +               ale = <&gpio2 0x3>;
 492 +               cle = <&gpio2 0x2>;
 493 +               nce = <&gpio2 0x1>;
 494 +               rdy = <&gpio2 0x0>;
 495 +               reg = <0xf8000000 0x1000>;
 496 +               device_type = "rb,nand";
 497 +       };
 498 +
 499 +       nnand {
 500 +               reg = <0xf0000000 0x1000>;
 501 +       };
 502 +
 503 +       voltage {
 504 +               voltage_gpio = <&gpio3 0x11>;
 505 +       };
 506 +
 507 +       fancon {
 508 +               interrupt-parent = <&ipic>;
 509 +               interrupts = <0x14 0x8>;
 510 +               fan_on = <&gpio0 0x10>;
 511 +       };
 512 +
 513 +       pci0: pci@e0008500 {
 514 +                device_type = "pci";
 515 +                // compatible = "83xx";
 516 +               compatible = "fsl,mpc8349-pci";
 517 +                reg = <0xe0008500 0x100 0xe0008300 0x8>;
 518 +                #address-cells = <3>;
 519 +                #size-cells = <2>;
 520 +                #interrupt-cells = <1>;
 521 +               // clock-frequency = <0>;
 522 +                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
 523 +                bus-range = <0x0 0x0>;
 524 +                interrupt-map = <
 525 +                       /* IDSEL 0x10 AD16 miniPCI slot 0 */
 526 +                        0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
 527 +                        0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
 528 +
 529 +                       /* IDSEL 0x11 AD17 miniPCI slot 1 */
 530 +                        0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
 531 +                        0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
 532 +
 533 +                       /* IDSEL 0x12 AD18  miniPCI slot 2 */
 534 +                        0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
 535 +                        0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
 536 +
 537 +                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 538 +               interrupt-parent = <&ipic>;
 539 +               // interrupts = <66 0x8>;
 540 +        };
 541 +
 542 +
 543 +       qe@e0100000 {
 544 +               reg = <0xe0100000 0x480>;
 545 +               ranges = <0x0 0xe0100000 0x100000>;
 546 +               model = "QE";
 547 +               device_type = "qe";
 548 +               compatible = "fsl,qe";
 549 +               #size-cells = <1>;
 550 +               #address-cells = <1>;
 551 +               brg-frequency = <0>;
 552 +                bus-frequency = <0>;
 553 +                // bus-frequency = <198000000>;
 554 +                fsl,qe-num-riscs = <1>;
 555 +                fsl,qe-num-snums = <28>;
 556 +
 557 +               qeic: qeic@80 {
 558 +                       interrupt-controller;
 559 +                       compatible = "fsl,qe-ic";
 560 +                       big-endian;
 561 +                       built-in;
 562 +                       reg = <0x80 0x80>;
 563 +                       #interrupt-cells = <1>;
 564 +                       #address-cells = <0>;
 565 +                       device_type = "qeic";
 566 +                       interrupts = <0x20 0x8 0x21 0x8>;
 567 +                       interrupt-parent = <&ipic>;
 568 +               };
 569 +
 570 +               mdio@2120 {
 571 +                       compatible = "ucc_geth_phy";
 572 +                       device_type = "mdio";
 573 +                       reg = <0x3120 0x18>;
 574 +                       #size-cells = <0>;
 575 +                       #address-cells = <1>;
 576 +
 577 +                       phy3: ethernet-phy@03 {
 578 +                               // interface = <0x3>;
 579 +                               device_type = "ethernet-phy";
 580 +                               reg = <0x3>;
 581 +                       };
 582 +
 583 +                       phy2: ethernet-phy@02 {
 584 +                               // interface = <0x3>;
 585 +                               device_type = "ethernet-phy";
 586 +                               reg = <0x2>;
 587 +                       };
 588 +
 589 +                       phy1: ethernet-phy@01 {
 590 +                               // interface = <0x3>;
 591 +                               device_type = "ethernet-phy";
 592 +                               reg = <0x1>;
 593 +                       };
 594 +               };
 595 +
 596 +               enet0: ucc@2200 {
 597 +                       tx-clock = <0x1a>;
 598 +                       rx-clock = <0x1f>;
 599 +                       mac-address = [00 0c 42 1c 29 d2];
 600 +                       interrupt-parent = <&qeic>;
 601 +                       interrupts = <0x22>;
 602 +                       reg = <0x2200 0x200>;
 603 +                       device-id = <0x3>;
 604 +                       model = "UCC";
 605 +                       compatible = "ucc_geth";
 606 +                       device_type = "network";
 607 +                       phy-handle = <&phy2>;
 608 +                       pio-handle = <&pio3>;
 609 +               };
 610 +
 611 +               enet1: ucc@3200 {
 612 +                       tx-clock = <0x22>;
 613 +                       rx-clock = <0x20>;
 614 +                       mac-address = [00 0c 42 1c 29 d1];
 615 +                       interrupt-parent = <&qeic>;
 616 +                       interrupts = <0x23>;
 617 +                       reg = <0x3200 0x200>;
 618 +                       device-id = <0x4>;
 619 +                       model = "UCC";
 620 +                       compatible = "ucc_geth";
 621 +                       device_type = "network";
 622 +                       phy-handle = <&phy3>;
 623 +                       pio-handle = <&pio4>;
 624 +               };
 625 +
 626 +               enet2: ucc@3000 {
 627 +                       tx-clock = <0x18>;
 628 +                       rx-clock = <0x17>;
 629 +                       mac-address = [00 0c 42 1c 29 d0];
 630 +                       interrupt-parent = <&qeic>;
 631 +                       interrupts = <0x21>;
 632 +                       reg = <0x3000 0x200>;
 633 +                       device-id = <0x2>;
 634 +                       model = "UCC";
 635 +                       compatible = "ucc_geth";
 636 +                       device_type = "network";
 637 +                       phy-handle = <&phy1>;
 638 +                       pio-handle = <&pio2>;
 639 +               };
 640 +
 641 +               spi@500 {
 642 +                       mode = "cpu";
 643 +                       interrupt-parent = <&qeic>;
 644 +                       interrupts = <0x1>;
 645 +                       reg = <0x500 0x40>;
 646 +                       compatible = "fsl,spi";
 647 +                       device_type = "spi";
 648 +               };
 649 +
 650 +               spi@4c0 {
 651 +                       mode = "cpu";
 652 +                       interrupt-parent = <&qeic>;
 653 +                       interrupts = <0x2>;
 654 +                       reg = <0x4c0 0x40>;
 655 +                       compatible = "fsl,spi";
 656 +                       device_type = "spi";
 657 +               };
 658 +
 659 +               muram@10000 {
 660 +                       #address-cells = <1>;
 661 +                       #size-cells = <1>;
 662 +                       compatible = "fsl,qe-muram", "fsl,cpm-muram";
 663 +                       ranges = <0x0 0x10000 0x4000>;
 664 +                       device_type = "muram";
 665 +
 666 +                       data-only@0 {
 667 +                               compatible = "fsl,qe-muram-data",
 668 +                                       "fsl,cpm-muram-data";
 669 +                               reg = <0x0 0x4000>;
 670 +                       };
 671 +               };
 672 +       };
 673 +
 674 +
 675 +       soc8323@e0000000 {
 676 +               bus-frequency = <0x1>;
 677 +               reg = <0xe0000000 0x200>;
 678 +               ranges = <0x0 0xe0000000 0x100000>;
 679 +               device_type = "soc";
 680 +               compatible = "simple-bus";
 681 +               #interrupt-cells = <0x2>;
 682 +               #size-cells = <1>;
 683 +               #address-cells = <1>;
 684 +
 685 +               beeper {
 686 +                       gpio = <&gpio3 0x12>;
 687 +                       reg = <0x500 0x100>;
 688 +                       interrupt-parent = <&ipic>;
 689 +                       interrupts = <0x48 0x8>;
 690 +               };
 691 +
 692 +               gpio3: gpio@3 {
 693 +                       reg = <0x144c 0x4>;
 694 +                       device-id = <0x3>;
 695 +                       compatible = "qe_gpio";
 696 +                       device_type = "gpio";
 697 +               };
 698 +
 699 +               gpio2: gpio@2 {
 700 +                       reg = <0x1434 0x4>;
 701 +                       device-id = <0x2>;
 702 +                       compatible = "qe_gpio";
 703 +                       device_type = "gpio";
 704 +               };
 705 +
 706 +               gpio0: gpio@0 {
 707 +                       reg = <0x1404 0x4>;
 708 +                       device-id = <0x0>;
 709 +                       compatible = "qe_gpio";
 710 +                       device_type = "gpio";
 711 +               };
 712 +
 713 +               par_io@1400 {
 714 +                       num-ports = <4>;
 715 +                       device_type = "par_io";
 716 +                       reg = <0x1400 0x100>;
 717 +
 718 +                       pio4: ucc_pin@04 {
 719 +                               pio-map = <
 720 +                       /* port  pin  dir  open_drain  assignment  has_irq */
 721 +                                       1 18 1 0 1 0
 722 +                                       1 19 1 0 1 0
 723 +                                       1 20 1 0 1 0
 724 +                                       1 21 1 0 1 0
 725 +                                       1 30 1 0 1 0
 726 +                                       3 20 2 0 1 0
 727 +                                       1 30 2 0 1 0
 728 +                                       1 31 2 0 1 0
 729 +                                       1 22 2 0 1 0
 730 +                                       1 23 2 0 1 0
 731 +                                       1 24 2 0 1 0
 732 +                                       1 25 2 0 1 0
 733 +                                       1 28 2 0 1 0
 734 +                                       1 26 2 0 1 0
 735 +                                       3 21 2 0 1 0>;
 736 +                       };
 737 +
 738 +                       pio3: ucc_pin@03 {
 739 +                               pio-map = <
 740 +                       /* port  pin  dir  open_drain  assignment  has_irq */
 741 +                                       1 0  1 0 1 0
 742 +                                       1 1  1 0 1 0
 743 +                                       1 2  1 0 1 0
 744 +                                       1 3  1 0 1 0
 745 +                                       1 12 1 0 1 0
 746 +                                       3 24 2 0 1 0
 747 +                                       1 11 2 0 1 0
 748 +                                       1 13 2 0 1 0
 749 +                                       1 4  2 0 1 0
 750 +                                       1 5  2 0 1 0
 751 +                                       1 6  2 0 1 0
 752 +                                       1 7  2 0 1 0
 753 +                                       1 10 2 0 1 0
 754 +                                       1 8  2 0 1 0
 755 +                                       3 29 2 0 1 0>;
 756 +                       };
 757 +
 758 +                       pio2: ucc_pin@02 {
 759 +                               pio-map = <
 760 +                       /* port  pin  dir  open_drain  assignment  has_irq */
 761 +                                       3 4  3 0 2 0
 762 +                                       3 5  1 0 2 0
 763 +                                       0 18 1 0 1 0
 764 +                                       0 19 1 0 1 0
 765 +                                       0 20 1 0 1 0
 766 +                                       0 21 1 0 1 0
 767 +                                       0 30 1 0 1 0
 768 +                                       3 6  2 0 1 0
 769 +                                       0 29 2 0 1 0
 770 +                                       0 31 2 0 1 0
 771 +                                       0 22 2 0 1 0
 772 +                                       0 23 2 0 1 0
 773 +                                       0 24 2 0 1 0
 774 +                                       0 25 2 0 1 0
 775 +                                       0 28 2 0 1 0
 776 +                                       0 26 2 0 1 0
 777 +                                       3 31 2 0 1 0>;
 778 +                       };
 779 +               };
 780 +
 781 +               ipic: pic@700 {
 782 +                       device_type = "ipic";
 783 +                       built-in;
 784 +                       reg = <0x700 0x100>;
 785 +                       #interrupt-cells = <0x2>;
 786 +                       #address-cells = <0x0>;
 787 +                       interrupt-controller;
 788 +               };
 789 +
 790 +
 791 +               serial@4500 {
 792 +                       interrupt-parent = <&ipic>;
 793 +                       interrupts = <0x9 0x8>;
 794 +                       clock-frequency = <0x7f27c20>;
 795 +                       reg = <0x4500 0x100>;
 796 +                       compatible = "ns16550";
 797 +                       device_type = "serial";
 798 +               };
 799 +
 800 +                dma@82a8 {
 801 +                        #address-cells = <1>;
 802 +                        #size-cells = <1>;
 803 +                        compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
 804 +                        reg = <0x82a8 4>;
 805 +                        ranges = <0 0x8100 0x1a8>;
 806 +                        interrupt-parent = <&ipic>;
 807 +                        interrupts = <71 8>;
 808 +                        cell-index = <0>;
 809 +                        dma-channel@0 {
 810 +                                compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 811 +                                reg = <0 0x80>;
 812 +                                cell-index = <0>;
 813 +                                interrupt-parent = <&ipic>;
 814 +                                interrupts = <71 8>;
 815 +                        };
 816 +                        dma-channel@80 {
 817 +                                compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 818 +                                reg = <0x80 0x80>;
 819 +                                cell-index = <1>;
 820 +                                interrupt-parent = <&ipic>;
 821 +                                interrupts = <71 8>;
 822 +                        };
 823 +                        dma-channel@100 {
 824 +                                compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 825 +                                reg = <0x100 0x80>;
 826 +                                cell-index = <2>;
 827 +                                interrupt-parent = <&ipic>;
 828 +                                interrupts = <71 8>;
 829 +                        };
 830 +                        dma-channel@180 {
 831 +                                compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 832 +                                reg = <0x180 0x28>;
 833 +                                cell-index = <3>;
 834 +                                interrupt-parent = <&ipic>;
 835 +                                interrupts = <71 8>;
 836 +                        };
 837 +                };
 838 +
 839 +               wdt@200 {
 840 +                       reg = <0x200 0x100>;
 841 +                       compatible = "mpc83xx_wdt";
 842 +                       device_type = "watchdog";
 843 +               };
 844 +       };
 845 +};
 846 --- /dev/null
 847 +++ b/arch/powerpc/boot/rb333.c
 848 @@ -0,0 +1,73 @@
 849 +/*
 850 + * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
 851 + *
 852 + * Author: Alexandros C. Couloumbis  <alex@ozo.com>
 853 + * Author: Michael Guntsche <mike@it-loops.com>
 854 + *
 855 + * Copyright (c) 2010 Alexandros C. Couloumbis
 856 + * Copyright (c) 2009 Michael Guntsche
 857 + *
 858 + * This program is free software; you can redistribute it and/or modify it
 859 + * under the terms of the GNU General Public License version 2 as published
 860 + * by the Free Software Foundation.
 861 + */
 862 +
 863 +#include "ops.h"
 864 +#include "types.h"
 865 +#include "io.h"
 866 +#include "stdio.h"
 867 +#include <libfdt.h>
 868 +
 869 +BSS_STACK(4*1024);
 870 +
 871 +u64 memsize64;
 872 +const void *fw_dtb;
 873 +
 874 +static void rb333_fixups(void)
 875 +{
 876 +       const u32 *reg, *timebase, *clock;
 877 +       int node, size;
 878 +       void *chosen;
 879 +       const char* bootargs;
 880 +
 881 +       dt_fixup_memory(0, memsize64);
 882 +
 883 +       /* Find the CPU timebase and clock frequencies. */
 884 +       node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
 885 +       timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
 886 +       clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
 887 +       dt_fixup_cpu_clocks(*clock, *timebase, 0);
 888 +
 889 +       /* Fixup chosen
 890 +        * The bootloader reads the kernelparm segment and adds the content to
 891 +        * bootargs. This is needed to specify root and other boot flags.
 892 +        */
 893 +       chosen = finddevice("/chosen");
 894 +       node = fdt_path_offset(fw_dtb, "/chosen");
 895 +       bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
 896 +       setprop_str(chosen, "bootargs", bootargs);
 897 +}
 898 +
 899 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 900 +                  unsigned long r6, unsigned long r7)
 901 +{
 902 +       const u32 *reg;
 903 +       int node, size;
 904 +
 905 +       fw_dtb = (const void *)r3;
 906 +
 907 +       /* Find the memory range. */
 908 +       node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
 909 +       reg = fdt_getprop(fw_dtb, node, "reg", &size);
 910 +       memsize64 = reg[1];
 911 +
 912 +       /* Now we have the memory size; initialize the heap. */
 913 +       simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
 914 +
 915 +       /* Prepare the device tree and find the console. */
 916 +       fdt_init(_dtb_start);
 917 +       serial_console_init();
 918 +
 919 +       /* Remaining fixups... */
 920 +       platform_ops.fixups = rb333_fixups;
 921 +}
 922 --- /dev/null
 923 +++ b/arch/powerpc/platforms/83xx/rbppc.c
 924 @@ -0,0 +1,388 @@
 925 +/*
 926 + * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
 927 + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
 928 + * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
 929 + * Copyright (C) Mikrotik 2007
 930 + *
 931 + * This program is free software; you can redistribute it and/or modify it
 932 + * under the terms of the GNU General Public License as published by the
 933 + * Free Software Foundation; either version 2 of the License, or (at your
 934 + * option) any later version.
 935 + */
 936 +
 937 +#include <linux/delay.h>
 938 +#include <linux/root_dev.h>
 939 +#include <linux/initrd.h>
 940 +#include <linux/interrupt.h>
 941 +#include <linux/of_platform.h>
 942 +#include <linux/of_device.h>
 943 +#include <linux/of_platform.h>
 944 +#include <linux/pci.h>
 945 +#include <asm/time.h>
 946 +#include <asm/ipic.h>
 947 +#include <asm/udbg.h>
 948 +#include <asm/qe.h>
 949 +#include <asm/qe_ic.h>
 950 +#include <sysdev/fsl_soc.h>
 951 +#include <sysdev/fsl_pci.h>
 952 +#include "mpc83xx.h"
 953 +
 954 +#define SYSCTL         0x100
 955 +#define SICRL          0x014
 956 +
 957 +#define GTCFR2         0x04
 958 +#define GTMDR4         0x22
 959 +#define GTRFR4         0x26
 960 +#define GTCNR4         0x2e
 961 +#define GTVER4         0x36
 962 +#define GTPSR4         0x3e
 963 +
 964 +#define GTCFR_BCM      0x40
 965 +#define GTCFR_STP4     0x20
 966 +#define GTCFR_RST4     0x10
 967 +#define GTCFR_STP3     0x02
 968 +#define GTCFR_RST3     0x01
 969 +
 970 +#define GTMDR_ORI      0x10
 971 +#define GTMDR_FRR      0x08
 972 +#define GTMDR_ICLK16   0x04
 973 +
 974 +extern int par_io_data_set(u8 port, u8 pin, u8 val);
 975 +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 976 +                            int assignment, int has_irq);
 977 +
 978 +static unsigned timer_freq;
 979 +static void *gtm;
 980 +
 981 +static int beeper_irq;
 982 +static unsigned beeper_gpio_pin[2];
 983 +
 984 +int rb333model = 0;
 985 +
 986 +irqreturn_t rbppc_timer_irq(int irq, void *ptr)
 987 +{
 988 +       static int toggle = 0;
 989 +
 990 +       par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
 991 +       toggle = !toggle;
 992 +
 993 +       /* ack interrupt */
 994 +       out_be16(gtm + GTVER4, 3);
 995 +
 996 +       return IRQ_HANDLED;
 997 +}
 998 +
 999 +void rbppc_beep(unsigned freq)
1000 +{
1001 +       unsigned gtmdr;
1002 +
1003 +       if (freq > 5000) freq = 5000;
1004 +
1005 +       if (!gtm)
1006 +               return;
1007 +       if (!freq) {
1008 +               out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
1009 +               return;
1010 +       }
1011 +
1012 +       out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
1013 +       out_be16(gtm + GTPSR4, 255);
1014 +       gtmdr = GTMDR_FRR | GTMDR_ICLK16;
1015 +       if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
1016 +       out_be16(gtm + GTMDR4, gtmdr);
1017 +       out_be16(gtm + GTVER4, 3);
1018 +
1019 +       out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
1020 +       out_be16(gtm + GTCNR4, 0);
1021 +}
1022 +EXPORT_SYMBOL(rbppc_beep);
1023 +
1024 +static void __init rbppc_setup_arch(void)
1025 +{
1026 +       struct device_node *np;
1027 +
1028 +       np = of_find_node_by_type(NULL, "cpu");
1029 +       if (np) {
1030 +               const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
1031 +               loops_per_jiffy = fp ? *fp / HZ : 0;
1032 +
1033 +               of_node_put(np);
1034 +       }
1035 +
1036 +       np = of_find_node_by_name(NULL, "serial");
1037 +       if (np) {
1038 +               timer_freq =
1039 +                   *(unsigned *) of_get_property(np, "clock-frequency", NULL);
1040 +               of_node_put(np);
1041 +       }
1042 +
1043 +#ifdef CONFIG_PCI
1044 +       np = of_find_node_by_type(NULL, "pci");
1045 +       if (np) {
1046 +               mpc83xx_add_bridge(np);
1047 +       }
1048 +#endif
1049 +
1050 +if (rb333model) {
1051 +
1052 +#ifdef CONFIG_QUICC_ENGINE
1053 +        qe_reset();
1054 +
1055 +        if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
1056 +                par_io_init(np);
1057 +                of_node_put(np);
1058 +
1059 +                for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
1060 +                        par_io_of_config(np);
1061 +        }
1062 +#endif
1063 +
1064 +}  /* RB333 */
1065 +
1066 +}
1067 +
1068 +void __init rbppc_init_IRQ(void)
1069 +{
1070 +       struct device_node *np;
1071 +
1072 +       np = of_find_node_by_type(NULL, "ipic");
1073 +       if (np) {
1074 +               ipic_init(np, 0);
1075 +               ipic_set_default_priority();
1076 +               of_node_put(np);
1077 +       }
1078 +
1079 +if (rb333model) {
1080 +
1081 +#ifdef CONFIG_QUICC_ENGINE
1082 +        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
1083 +        if (!np) {
1084 +                np = of_find_node_by_type(NULL, "qeic");
1085 +                if (!np)
1086 +                        return;
1087 +        }
1088 +        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
1089 +        of_node_put(np);
1090 +#endif                          /* CONFIG_QUICC_ENGINE */
1091 +
1092 +}  /* RB333 */
1093 +
1094 +}
1095 +
1096 +static int __init rbppc_probe(void)
1097 +{
1098 +       char *model;
1099 +
1100 +       model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
1101 +
1102 +       if (!model)
1103 +               return 0;
1104 +
1105 +       if (strcmp(model, "RB333") == 0) {
1106 +               rb333model = 1;
1107 +               return 1;
1108 +       }
1109 +
1110 +       if (strcmp(model, "RB600") == 0)
1111 +               return 1;
1112 +
1113 +       return 0;
1114 +}
1115 +
1116 +static void __init rbppc_beeper_init(struct device_node *beeper)
1117 +{
1118 +       struct resource res;
1119 +       struct device_node *gpio;
1120 +       const unsigned *pin;
1121 +       const unsigned *gpio_id;
1122 +
1123 +       if (of_address_to_resource(beeper, 0, &res)) {
1124 +               printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
1125 +               return;
1126 +       }
1127 +
1128 +       pin = of_get_property(beeper, "gpio", NULL);
1129 +       if (pin) {
1130 +               gpio = of_find_node_by_phandle(pin[0]);
1131 +
1132 +               if (!gpio) {
1133 +                       printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
1134 +                       return;
1135 +               }
1136 +
1137 +               gpio_id = of_get_property(gpio, "device-id", NULL);
1138 +               if (!gpio_id) {
1139 +                       printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
1140 +                       return;
1141 +               }
1142 +
1143 +               beeper_gpio_pin[0] = *gpio_id;
1144 +               beeper_gpio_pin[1] = pin[1];
1145 +
1146 +               par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
1147 +       } else {
1148 +               void *sysctl;
1149 +
1150 +               sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
1151 +               out_be32(sysctl + SICRL,
1152 +                        in_be32(sysctl + SICRL) | (1 << (31 - 19)));
1153 +               iounmap(sysctl);
1154 +       }
1155 +
1156 +       gtm = ioremap_nocache(res.start, res.end - res.start + 1);
1157 +
1158 +       beeper_irq = irq_of_parse_and_map(beeper, 0);
1159 +       if (beeper_irq != NO_IRQ) {
1160 +               int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
1161 +               if (e) {
1162 +                       printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
1163 +               }
1164 +       }
1165 +}
1166 +
1167 +#define SBIT(x) (0x80000000 >> (x))
1168 +#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
1169 +
1170 +#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
1171 +#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
1172 +
1173 +#define SICRL_RB600(x) ((x) + (0x114 >> 2))
1174 +#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
1175 +#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
1176 +
1177 +static void rbppc_restart(char *cmd)
1178 +{
1179 +       __be32 __iomem *reg;
1180 +       unsigned rb_model;
1181 +       struct device_node *root;
1182 +       unsigned int size;
1183 +
1184 +       root = of_find_node_by_path("/");
1185 +       if (root) {
1186 +               const char *prop = (char *) of_get_property(root, "model", &size);
1187 +               rb_model = prop[sizeof("RB") - 1] - '0';
1188 +               of_node_put(root);
1189 +               switch (rb_model) {
1190 +               case 3:
1191 +                       reg = ioremap(get_immrbase(), 0x2000);
1192 +                       local_irq_disable();
1193 +                       out_be32(GPIO_DIR_RB333(reg),
1194 +                       (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
1195 +                       out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
1196 +                       break;
1197 +               case 6:
1198 +                       reg = ioremap(get_immrbase(), 0x1000);
1199 +                       local_irq_disable();
1200 +                       out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
1201 +                       out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
1202 +                       out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
1203 +                       break;
1204 +               default:
1205 +                       mpc83xx_restart(cmd);
1206 +                       break;
1207 +               }
1208 +       }
1209 +       else mpc83xx_restart(cmd);
1210 +
1211 +       for (;;) ;
1212 +}
1213 +
1214 +static void rbppc_halt(void)
1215 +{
1216 +       while (1);
1217 +}
1218 +
1219 +static struct of_device_id rbppc_ids[] = {
1220 +       { .type = "soc", },
1221 +       { .compatible = "soc", },
1222 +       { .compatible = "simple-bus", },
1223 +       { .type = "qe", },
1224 +       { .compatible = "fsl,qe", },
1225 +       { .compatible = "gianfar", },
1226 +       { },
1227 +};
1228 +
1229 +static int __init rbppc_declare_of_platform_devices(void)
1230 +{
1231 +       struct device_node *np;
1232 +       unsigned idx;
1233 +
1234 +       of_platform_bus_probe(NULL, rbppc_ids, NULL);
1235 +
1236 +       np = of_find_node_by_type(NULL, "mdio");
1237 +       if (np) {
1238 +               unsigned len;
1239 +               unsigned *res;
1240 +               const unsigned *eres;
1241 +               struct device_node *ep;
1242 +
1243 +               ep = of_find_compatible_node(NULL, "network", "ucc_geth");
1244 +               if (ep) {
1245 +                       eres = of_get_property(ep, "reg", &len);
1246 +                       res = (unsigned *) of_get_property(np, "reg", &len);
1247 +                       if (res && eres) {
1248 +                               res[0] = eres[0] + 0x120;
1249 +                       }
1250 +               }
1251 +       }
1252 +
1253 +       np = of_find_node_by_name(NULL, "nand");
1254 +       if (np) {
1255 +               of_platform_device_create(np, "nand", NULL);
1256 +       }
1257 +
1258 +       idx = 0;
1259 +       for_each_node_by_type(np, "rb,cf") {
1260 +               char dev_name[12];
1261 +               snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
1262 +               of_platform_device_create(np, dev_name, NULL);
1263 +               ++idx;
1264 +       }
1265 +
1266 +       np = of_find_node_by_name(NULL, "beeper");
1267 +       if (np) {
1268 +               rbppc_beeper_init(np);
1269 +       }
1270 +
1271 +       return 0;
1272 +}
1273 +machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
1274 +
1275 +define_machine(rb600) {
1276 +       .name                           = "MikroTik RouterBOARD 333/600 series",
1277 +       .probe                          = rbppc_probe,
1278 +       .setup_arch                     = rbppc_setup_arch,
1279 +       .init_IRQ                       = rbppc_init_IRQ,
1280 +       .get_irq                        = ipic_get_irq,
1281 +       .restart                        = rbppc_restart,
1282 +       .halt                           = rbppc_halt,
1283 +       .time_init                      = mpc83xx_time_init,
1284 +       .calibrate_decr                 = generic_calibrate_decr,
1285 +};
1286 +
1287 +static void fixup_pcibridge(struct pci_dev *dev)
1288 +{
1289 +       if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1290 +               /* let the kernel itself set right memory windows */
1291 +               pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
1292 +               pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
1293 +               pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
1294 +               pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
1295 +               pci_write_config_byte(dev, PCI_IO_BASE, 0);
1296 +               pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
1297 +
1298 +               pci_write_config_byte(
1299 +                       dev, PCI_COMMAND,
1300 +                       PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
1301 +               pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1302 +       }
1303 +}
1304 +
1305 +
1306 +static void fixup_rb604(struct pci_dev *dev)
1307 +{
1308 +       pci_write_config_byte(dev, 0xC0, 0x01);
1309 +}
1310 +
1311 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
1312 +DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)