2 * Ralink RT288x SoC PCI register definitions
4 * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Parts of this file are based on Ralink's 2.6.21 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/types.h>
15 #include <linux/pci.h>
17 #include <linux/init.h>
19 #include <asm/mach-ralink/rt288x.h>
20 #include <asm/mach-ralink/rt288x_regs.h>
22 #define RT2880_PCI_MEM_BASE 0x20000000
23 #define RT2880_PCI_MEM_SIZE 0x10000000
24 #define RT2880_PCI_IO_BASE 0x00460000
25 #define RT2880_PCI_IO_SIZE 0x00010000
27 #define RT2880_PCI_REG_PCICFG_ADDR 0x00
28 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
29 #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
30 #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
31 #define RT2880_PCI_REG_CONFIG_ADDR 0x20
32 #define RT2880_PCI_REG_CONFIG_DATA 0x24
33 #define RT2880_PCI_REG_MEMBASE 0x28
34 #define RT2880_PCI_REG_IOBASE 0x2c
35 #define RT2880_PCI_REG_ID 0x30
36 #define RT2880_PCI_REG_CLASS 0x34
37 #define RT2880_PCI_REG_SUBID 0x38
38 #define RT2880_PCI_REG_ARBCTL 0x80
40 #define PCI_ACCESS_READ 0
41 #define PCI_ACCESS_WRITE 1
43 static void __iomem *rt2880_pci_base;
44 static DEFINE_SPINLOCK(rt2880_pci_lock);
46 static u32 rt2880_pci_reg_read(u32 reg)
48 return readl(rt2880_pci_base + reg);
51 static void rt2880_pci_reg_write(u32 val, u32 reg)
53 writel(val, rt2880_pci_base + reg);
56 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
57 unsigned int func, unsigned int where)
59 return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
63 static void config_access(unsigned char access_type, struct pci_bus *bus,
64 unsigned int devfn, unsigned char where, u32 *data)
68 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
69 PCI_FUNC(devfn), where);
71 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
72 if (access_type == PCI_ACCESS_WRITE)
73 rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
75 *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
78 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
84 spin_lock_irqsave(&rt2880_pci_lock, flags);
85 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
86 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
90 *val = (data >> ((where & 3) << 3)) & 0xff;
93 *val = (data >> ((where & 3) << 3)) & 0xffff;
100 return PCIBIOS_SUCCESSFUL;
103 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
104 int where, int size, u32 val)
109 spin_lock_irqsave(&rt2880_pci_lock, flags);
113 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
114 data = (data & ~(0xff << ((where & 3) << 3))) |
115 (val << ((where & 3) << 3));
118 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
119 data = (data & ~(0xffff << ((where & 3) << 3))) |
120 (val << ((where & 3) << 3));
127 config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
128 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
130 return PCIBIOS_SUCCESSFUL;
133 static struct pci_ops rt2880_pci_ops = {
134 .read = rt2880_pci_config_read,
135 .write = rt2880_pci_config_write,
138 static struct resource rt2880_pci_io_resource = {
139 .name = "PCI MEM space",
140 .start = RT2880_PCI_MEM_BASE,
141 .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
142 .flags = IORESOURCE_MEM,
145 static struct resource rt2880_pci_mem_resource = {
146 .name = "PCI IO space",
147 .start = RT2880_PCI_IO_BASE,
148 .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
149 .flags = IORESOURCE_IO,
152 static struct pci_controller rt2880_pci_controller = {
153 .pci_ops = &rt2880_pci_ops,
154 .mem_resource = &rt2880_pci_io_resource,
155 .io_resource = &rt2880_pci_mem_resource,
158 static inline void read_config(unsigned long bus, unsigned long dev,
159 unsigned long func, unsigned long reg,
162 unsigned long address;
165 address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
167 spin_lock_irqsave(&rt2880_pci_lock, flags);
168 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
169 *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
170 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
173 static inline void write_config(unsigned long bus, unsigned long dev,
174 unsigned long func, unsigned long reg,
177 unsigned long address;
180 address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
182 spin_lock_irqsave(&rt2880_pci_lock, flags);
183 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
184 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
185 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
188 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
194 if (dev->bus->number != 0)
197 switch (PCI_SLOT(dev->devfn)) {
199 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
200 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
203 irq = RT288X_CPU_IRQ_PCI;
206 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
207 __FILE__, __func__, __LINE__);
212 pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
213 pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
214 pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
215 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
216 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
217 PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
218 pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
219 pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
224 static int __init rt2880_pci_init(void)
226 unsigned long val = 0;
229 rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
231 rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
232 for(i = 0; i < 0xfffff; i++) {}
234 rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
235 rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
236 rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
237 rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
238 rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
239 rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
240 rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
241 rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
242 rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
243 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
244 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
246 register_pci_controller(&rt2880_pci_controller);
250 int pcibios_plat_dev_init(struct pci_dev *dev)
255 arch_initcall(rt2880_pci_init);