1 #include <linux/types.h>
4 #include <linux/init.h>
6 #include <asm/mach-ralink/rt288x.h>
8 #define RT2880_PCI_SLOT1_BASE 0x20000000
9 #define RALINK_PCI_BASE 0xA0440000
10 #define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
11 #define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
12 #define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
13 #define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
14 #define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
15 #define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
16 #define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
17 #define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
18 #define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
19 #define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
20 #define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
21 #define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
23 #define PCI_ACCESS_READ 0
24 #define PCI_ACCESS_WRITE 1
26 static int config_access(unsigned char access_type, struct pci_bus *bus,
27 unsigned int devfn, unsigned char where, u32 *data)
29 unsigned int slot = PCI_SLOT(devfn);
31 u8 func = PCI_FUNC(devfn);
33 address = (bus->number << 16) | (slot << 11) | (func << 8) |
34 (where & 0xfc) | 0x80000000;
36 writel(address, RT2880_PCI_CONFIG_ADDR);
37 if (access_type == PCI_ACCESS_WRITE)
38 writel(*data, RT2880_PCI_CONFIG_DATA);
40 *data = readl(RT2880_PCI_CONFIG_DATA);
45 int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
50 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
51 return PCIBIOS_DEVICE_NOT_FOUND;
54 *val = (data >> ((where & 3) << 3)) & 0xff;
56 *val = (data >> ((where & 3) << 3)) & 0xffff;
60 return PCIBIOS_SUCCESSFUL;
63 int pci_config_write(struct pci_bus *bus, unsigned int devfn,
64 int where, int size, u32 val)
71 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
72 return PCIBIOS_DEVICE_NOT_FOUND;
74 data = (data & ~(0xff << ((where & 3) << 3))) |
75 (val << ((where & 3) << 3));
77 data = (data & ~(0xffff << ((where & 3) << 3))) |
78 (val << ((where & 3) << 3));
81 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
82 return PCIBIOS_DEVICE_NOT_FOUND;
84 return PCIBIOS_SUCCESSFUL;
87 struct pci_ops rt2880_pci_ops = {
88 .read = pci_config_read,
89 .write = pci_config_write,
92 static struct resource pci_io_resource = {
93 .name = "pci MEM space",
96 .flags = IORESOURCE_MEM,
99 static struct resource pci_mem_resource = {
100 .name = "pci IO space",
103 .flags = IORESOURCE_IO,
106 struct pci_controller rt2880_controller = {
107 .pci_ops = &rt2880_pci_ops,
108 .mem_resource = &pci_io_resource,
109 .io_resource = &pci_mem_resource,
110 .mem_offset = 0x00000000UL,
111 .io_offset = 0x00000000UL,
114 void inline read_config(unsigned long bus, unsigned long dev,
115 unsigned long func, unsigned long reg,
118 unsigned long address;
120 address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
122 writel(address, RT2880_PCI_CONFIG_ADDR);
123 *val = readl(RT2880_PCI_CONFIG_DATA);
126 void inline write_config(unsigned long bus, unsigned long dev,
127 unsigned long func, unsigned long reg,
130 unsigned long address;
132 address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
134 writel(address, RT2880_PCI_CONFIG_ADDR);
135 writel(val, RT2880_PCI_CONFIG_DATA);
138 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
144 if (dev->bus->number != 0)
147 switch (PCI_SLOT(dev->devfn)) {
149 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
150 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
153 irq = RT288X_CPU_IRQ_PCI;
156 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
157 __FILE__, __func__, __LINE__);
162 pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
163 pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
164 pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
165 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
166 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
167 PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
168 pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
169 pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
174 int init_rt2880pci(void)
176 unsigned long val = 0;
179 writel(0, RT2880_PCI_PCICFG_ADDR);
180 for(i = 0; i < 0xfffff; i++) {}
182 writel(0x79, RT2880_PCI_ARBCTL);
183 writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
184 writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
185 writel(0x00460000, RT2880_PCI_IOBASE);
186 writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
187 writel(0x08021814, RT2880_PCI_ID);
188 writel(0x00800001, RT2880_PCI_CLASS);
189 writel(0x28801814, RT2880_PCI_SUBID);
190 writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
191 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
192 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
194 register_pci_controller(&rt2880_controller);
198 int pcibios_plat_dev_init(struct pci_dev *dev)
203 struct pci_fixup pcibios_fixups[] = {
207 arch_initcall(init_rt2880pci);