2 * Ralink SoC Interrupt controller routines
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/bitops.h>
18 #include <asm/irq_cpu.h>
19 #include <asm/mipsregs.h>
21 #include <asm/mach-ralink/common.h>
23 /* INTC register offsets */
24 #define INTC_REG_STATUS0 0x00
25 #define INTC_REG_STATUS1 0x04
26 #define INTC_REG_TYPE 0x20
27 #define INTC_REG_RAW_STATUS 0x30
28 #define INTC_REG_ENABLE 0x34
29 #define INTC_REG_DISABLE 0x38
31 #define INTC_INT_GLOBAL BIT(31)
32 #define INTC_IRQ_COUNT 32
34 static unsigned int ramips_intc_irq_base;
35 static void __iomem *ramips_intc_base;
37 static inline void ramips_intc_wr(u32 val, unsigned reg)
39 __raw_writel(val, ramips_intc_base + reg);
42 static inline u32 ramips_intc_rr(unsigned reg)
44 return __raw_readl(ramips_intc_base + reg);
47 static void ramips_intc_irq_unmask(unsigned int irq)
49 irq -= ramips_intc_irq_base;
50 ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
53 static void ramips_intc_irq_mask(unsigned int irq)
55 irq -= ramips_intc_irq_base;
56 ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
59 static struct irq_chip ramips_intc_irq_chip = {
61 .unmask = ramips_intc_irq_unmask,
62 .mask = ramips_intc_irq_mask,
63 .mask_ack = ramips_intc_irq_mask,
66 static struct irqaction ramips_intc_irqaction = {
68 .name = "cascade [INTC]",
71 void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
76 ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
77 ramips_intc_irq_base = irq_base;
79 /* disable all interrupts */
80 ramips_intc_wr(~0, INTC_REG_DISABLE);
82 /* route all INTC interrupts to MIPS HW0 interrupt */
83 ramips_intc_wr(0, INTC_REG_TYPE);
85 for (i = ramips_intc_irq_base;
86 i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
87 set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
91 setup_irq(irq, &ramips_intc_irqaction);
92 ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
95 u32 ramips_intc_get_status(void)
97 return ramips_intc_rr(INTC_REG_STATUS0);