2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
35 #include <linux/bug.h>
37 #include <asm/mach-ralink/ralink_regs.h>
39 #include "ralink_soc_eth.h"
40 #include "esw_rt3052.h"
42 #include "ralink_ethtool.h"
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
46 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
47 #define DMA_DUMMY_DESC 0xffffffff
48 #define FE_DEFAULT_MSG_ENABLE \
58 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
59 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
60 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
61 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
63 #define SYSC_REG_RSTCTRL 0x34
65 static int fe_msg_level = -1;
66 module_param_named(msg_level, fe_msg_level, int, 0);
67 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
69 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
70 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
71 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
72 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
73 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
74 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
75 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
76 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
77 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
78 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
79 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
80 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
81 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
82 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
83 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
84 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
85 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
88 static const u16 *fe_reg_table = fe_reg_table_default;
92 void (*action)(struct fe_priv *);
95 static void __iomem *fe_base = 0;
97 void fe_w32(u32 val, unsigned reg)
99 __raw_writel(val, fe_base + reg);
102 u32 fe_r32(unsigned reg)
104 return __raw_readl(fe_base + reg);
107 void fe_reg_w32(u32 val, enum fe_reg reg)
109 fe_w32(val, fe_reg_table[reg]);
112 u32 fe_reg_r32(enum fe_reg reg)
114 return fe_r32(fe_reg_table[reg]);
117 void fe_reset(u32 reset_bits)
121 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
123 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
127 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
131 static inline void fe_int_disable(u32 mask)
133 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
134 FE_REG_FE_INT_ENABLE);
136 fe_reg_r32(FE_REG_FE_INT_ENABLE);
139 static inline void fe_int_enable(u32 mask)
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
142 FE_REG_FE_INT_ENABLE);
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
147 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
151 spin_lock_irqsave(&priv->page_lock, flags);
152 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
153 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
155 spin_unlock_irqrestore(&priv->page_lock, flags);
158 static int fe_set_mac_address(struct net_device *dev, void *p)
160 int ret = eth_mac_addr(dev, p);
163 struct fe_priv *priv = netdev_priv(dev);
165 if (priv->soc->set_mac)
166 priv->soc->set_mac(priv, dev->dev_addr);
168 fe_hw_set_macaddr(priv, p);
174 static inline int fe_max_frag_size(int mtu)
176 /* make sure buf_size will be at least MAX_RX_LENGTH */
177 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
178 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
180 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
181 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
184 static inline int fe_max_buf_size(int frag_size)
186 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
189 BUG_ON(buf_size < MAX_RX_LENGTH);
193 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
195 rxd->rxd1 = dma_rxd->rxd1;
196 rxd->rxd2 = dma_rxd->rxd2;
197 rxd->rxd3 = dma_rxd->rxd3;
198 rxd->rxd4 = dma_rxd->rxd4;
201 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
203 dma_txd->txd1 = txd->txd1;
204 dma_txd->txd3 = txd->txd3;
205 dma_txd->txd4 = txd->txd4;
206 /* clean dma done flag last */
207 dma_txd->txd2 = txd->txd2;
210 static void fe_clean_rx(struct fe_priv *priv)
213 struct fe_rx_ring *ring = &priv->rx_ring;
216 for (i = 0; i < ring->rx_ring_size; i++)
217 if (ring->rx_data[i]) {
218 if (ring->rx_dma && ring->rx_dma[i].rxd1)
219 dma_unmap_single(&priv->netdev->dev,
220 ring->rx_dma[i].rxd1,
223 put_page(virt_to_head_page(ring->rx_data[i]));
226 kfree(ring->rx_data);
227 ring->rx_data = NULL;
231 dma_free_coherent(&priv->netdev->dev,
232 ring->rx_ring_size * sizeof(*ring->rx_dma),
239 static int fe_alloc_rx(struct fe_priv *priv)
241 struct net_device *netdev = priv->netdev;
242 struct fe_rx_ring *ring = &priv->rx_ring;
245 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
250 for (i = 0; i < ring->rx_ring_size; i++) {
251 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
252 if (!ring->rx_data[i])
256 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
257 ring->rx_ring_size * sizeof(*ring->rx_dma),
259 GFP_ATOMIC | __GFP_ZERO);
263 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
267 for (i = 0; i < ring->rx_ring_size; i++) {
268 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
269 ring->rx_data[i] + NET_SKB_PAD + pad,
272 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
274 ring->rx_dma[i].rxd1 = (unsigned int) dma_addr;
276 if (priv->flags & FE_FLAG_RX_SG_DMA)
277 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
279 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
281 ring->rx_calc_idx = ring->rx_ring_size - 1;
284 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
285 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
286 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
287 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
295 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
297 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
298 dma_unmap_single(dev,
299 dma_unmap_addr(tx_buf, dma_addr0),
300 dma_unmap_len(tx_buf, dma_len0),
302 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
304 dma_unmap_addr(tx_buf, dma_addr0),
305 dma_unmap_len(tx_buf, dma_len0),
308 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
310 dma_unmap_addr(tx_buf, dma_addr1),
311 dma_unmap_len(tx_buf, dma_len1),
315 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
316 dev_kfree_skb_any(tx_buf->skb);
321 static void fe_clean_tx(struct fe_priv *priv)
324 struct device *dev = &priv->netdev->dev;
325 struct fe_tx_ring *ring = &priv->tx_ring;
328 for (i = 0; i < ring->tx_ring_size; i++)
329 fe_txd_unmap(dev, &ring->tx_buf[i]);
335 dma_free_coherent(dev,
336 ring->tx_ring_size * sizeof(*ring->tx_dma),
342 netdev_reset_queue(priv->netdev);
345 static int fe_alloc_tx(struct fe_priv *priv)
348 struct fe_tx_ring *ring = &priv->tx_ring;
350 ring->tx_free_idx = 0;
351 ring->tx_next_idx = 0;
352 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
354 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
359 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
360 ring->tx_ring_size * sizeof(*ring->tx_dma),
362 GFP_ATOMIC | __GFP_ZERO);
366 for (i = 0; i < ring->tx_ring_size; i++) {
367 if (priv->soc->tx_dma) {
368 priv->soc->tx_dma(&ring->tx_dma[i]);
370 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
374 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
375 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
376 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
377 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
385 static int fe_init_dma(struct fe_priv *priv)
389 err = fe_alloc_tx(priv);
393 err = fe_alloc_rx(priv);
400 static void fe_free_dma(struct fe_priv *priv)
406 void fe_stats_update(struct fe_priv *priv)
408 struct fe_hw_stats *hwstats = priv->hw_stats;
409 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
412 u64_stats_update_begin(&hwstats->syncp);
414 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
415 hwstats->rx_bytes += fe_r32(base);
416 stats = fe_r32(base + 0x04);
418 hwstats->rx_bytes += (stats << 32);
419 hwstats->rx_packets += fe_r32(base + 0x08);
420 hwstats->rx_overflow += fe_r32(base + 0x10);
421 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
422 hwstats->rx_short_errors += fe_r32(base + 0x18);
423 hwstats->rx_long_errors += fe_r32(base + 0x1c);
424 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
425 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
426 hwstats->tx_skip += fe_r32(base + 0x28);
427 hwstats->tx_collisions += fe_r32(base + 0x2c);
428 hwstats->tx_bytes += fe_r32(base + 0x30);
429 stats = fe_r32(base + 0x34);
431 hwstats->tx_bytes += (stats << 32);
432 hwstats->tx_packets += fe_r32(base + 0x38);
434 hwstats->tx_bytes += fe_r32(base);
435 hwstats->tx_packets += fe_r32(base + 0x04);
436 hwstats->tx_skip += fe_r32(base + 0x08);
437 hwstats->tx_collisions += fe_r32(base + 0x0c);
438 hwstats->rx_bytes += fe_r32(base + 0x20);
439 hwstats->rx_packets += fe_r32(base + 0x24);
440 hwstats->rx_overflow += fe_r32(base + 0x28);
441 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
442 hwstats->rx_short_errors += fe_r32(base + 0x30);
443 hwstats->rx_long_errors += fe_r32(base + 0x34);
444 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
445 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
448 u64_stats_update_end(&hwstats->syncp);
451 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
452 struct rtnl_link_stats64 *storage)
454 struct fe_priv *priv = netdev_priv(dev);
455 struct fe_hw_stats *hwstats = priv->hw_stats;
456 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
460 netdev_stats_to_stats64(storage, &dev->stats);
464 if (netif_running(dev) && netif_device_present(dev)) {
465 if (spin_trylock(&hwstats->stats_lock)) {
466 fe_stats_update(priv);
467 spin_unlock(&hwstats->stats_lock);
472 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
473 storage->rx_packets = hwstats->rx_packets;
474 storage->tx_packets = hwstats->tx_packets;
475 storage->rx_bytes = hwstats->rx_bytes;
476 storage->tx_bytes = hwstats->tx_bytes;
477 storage->collisions = hwstats->tx_collisions;
478 storage->rx_length_errors = hwstats->rx_short_errors +
479 hwstats->rx_long_errors;
480 storage->rx_over_errors = hwstats->rx_overflow;
481 storage->rx_crc_errors = hwstats->rx_fcs_errors;
482 storage->rx_errors = hwstats->rx_checksum_errors;
483 storage->tx_aborted_errors = hwstats->tx_skip;
484 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
486 storage->tx_errors = priv->netdev->stats.tx_errors;
487 storage->rx_dropped = priv->netdev->stats.rx_dropped;
488 storage->tx_dropped = priv->netdev->stats.tx_dropped;
493 static int fe_vlan_rx_add_vid(struct net_device *dev,
494 __be16 proto, u16 vid)
496 struct fe_priv *priv = netdev_priv(dev);
497 u32 idx = (vid & 0xf);
500 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
501 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
504 if (test_bit(idx, &priv->vlan_map)) {
505 netdev_warn(dev, "disable tx vlan offload\n");
506 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
507 netdev_update_features(dev);
509 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
513 vlan_cfg |= (vid << 16);
515 vlan_cfg &= 0xffff0000;
518 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
520 set_bit(idx, &priv->vlan_map);
526 static int fe_vlan_rx_kill_vid(struct net_device *dev,
527 __be16 proto, u16 vid)
529 struct fe_priv *priv = netdev_priv(dev);
530 u32 idx = (vid & 0xf);
532 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
533 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
536 clear_bit(idx, &priv->vlan_map);
541 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
544 return (u32)(ring->tx_ring_size -
545 ((ring->tx_next_idx - ring->tx_free_idx) &
546 (ring->tx_ring_size - 1)));
549 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
550 int tx_num, struct fe_tx_ring *ring)
552 struct fe_priv *priv = netdev_priv(dev);
553 struct skb_frag_struct *frag;
554 struct fe_tx_dma txd, *ptxd;
555 struct fe_tx_buf *tx_buf;
556 dma_addr_t mapped_addr;
557 unsigned int nr_frags;
559 int i, j, k, frag_size, frag_map_size, offset;
561 tx_buf = &ring->tx_buf[ring->tx_next_idx];
562 memset(tx_buf, 0, sizeof(*tx_buf));
563 memset(&txd, 0, sizeof(txd));
564 nr_frags = skb_shinfo(skb)->nr_frags;
566 /* init tx descriptor */
567 if (priv->soc->tx_dma)
568 priv->soc->tx_dma(&txd);
570 txd.txd4 = TX_DMA_DESP4_DEF;
573 /* TX Checksum offload */
574 if (skb->ip_summed == CHECKSUM_PARTIAL)
575 txd.txd4 |= TX_DMA_CHKSUM;
577 /* VLAN header offload */
578 if (vlan_tx_tag_present(skb)) {
579 if (IS_ENABLED(CONFIG_SOC_MT7621))
580 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
582 txd.txd4 |= TX_DMA_INS_VLAN |
583 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
584 (vlan_tx_tag_get(skb) & 0xF);
587 /* TSO: fill MSS info in tcp checksum field */
588 if (skb_is_gso(skb)) {
589 if (skb_cow_head(skb, 0)) {
590 netif_warn(priv, tx_err, dev,
591 "GSO expand head fail.\n");
594 if (skb_shinfo(skb)->gso_type &
595 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
596 txd.txd4 |= TX_DMA_TSO;
597 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
601 mapped_addr = dma_map_single(&dev->dev, skb->data,
602 skb_headlen(skb), DMA_TO_DEVICE);
603 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
605 txd.txd1 = mapped_addr;
606 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
608 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
609 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
610 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
613 j = ring->tx_next_idx;
615 for (i = 0; i < nr_frags; i++) {
617 frag = &skb_shinfo(skb)->frags[i];
618 frag_size = skb_frag_size(frag);
620 while (frag_size > 0) {
621 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
622 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
623 frag_map_size, DMA_TO_DEVICE);
624 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
628 j = NEXT_TX_DESP_IDX(j);
629 txd.txd1 = mapped_addr;
630 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
633 tx_buf = &ring->tx_buf[j];
634 memset(tx_buf, 0, sizeof(*tx_buf));
636 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
637 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
638 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
640 txd.txd3 = mapped_addr;
641 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
643 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
644 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
645 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
646 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
648 if (!((i == (nr_frags -1)) &&
649 (frag_map_size == frag_size))) {
650 fe_set_txd(&txd, &ring->tx_dma[j]);
651 memset(&txd, 0, sizeof(txd));
654 frag_size -= frag_map_size;
655 offset += frag_map_size;
660 /* set last segment */
662 txd.txd2 |= TX_DMA_LS1;
664 txd.txd2 |= TX_DMA_LS0;
665 fe_set_txd(&txd, &ring->tx_dma[j]);
667 /* store skb to cleanup */
670 netdev_sent_queue(dev, skb->len);
671 skb_tx_timestamp(skb);
673 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
675 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
676 netif_stop_queue(dev);
678 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
679 netif_wake_queue(dev);
682 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
683 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
688 j = ring->tx_next_idx;
689 for (i = 0; i < tx_num; i++) {
690 ptxd = &ring->tx_dma[j];
691 tx_buf = &ring->tx_buf[j];
694 fe_txd_unmap(&dev->dev, tx_buf);
696 ptxd->txd2 = TX_DMA_DESP2_DEF;
697 j = NEXT_TX_DESP_IDX(j);
705 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
710 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
711 if ((priv->flags & FE_FLAG_PADDING_64B) &&
712 !(priv->flags & FE_FLAG_PADDING_BUG))
715 if (vlan_tx_tag_present(skb))
717 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
719 else if(!(priv->flags & FE_FLAG_PADDING_64B))
724 if (skb->len < len) {
725 if ((ret = skb_pad(skb, len - skb->len)) < 0)
728 skb_set_tail_pointer(skb, len);
735 static inline int fe_cal_txd_req(struct sk_buff *skb)
738 struct skb_frag_struct *frag;
741 if (skb_is_gso(skb)) {
742 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
743 frag = &skb_shinfo(skb)->frags[i];
744 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
747 nfrags += skb_shinfo(skb)->nr_frags;
750 return DIV_ROUND_UP(nfrags, 2);
753 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
755 struct fe_priv *priv = netdev_priv(dev);
756 struct fe_tx_ring *ring = &priv->tx_ring;
757 struct net_device_stats *stats = &dev->stats;
761 if (fe_skb_padto(skb, priv)) {
762 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
766 tx_num = fe_cal_txd_req(skb);
767 if (unlikely(fe_empty_txd(ring) <= tx_num))
769 netif_stop_queue(dev);
770 netif_err(priv, tx_queued,dev,
771 "Tx Ring full when queue awake!\n");
772 return NETDEV_TX_BUSY;
775 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
779 stats->tx_bytes += len;
785 static inline void fe_rx_vlan(struct sk_buff *skb)
790 if (!__vlan_get_tag(skb, &vlanid)) {
791 /* pop the vlan tag */
792 ehdr = (struct ethhdr *)skb->data;
793 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
794 skb_pull(skb, VLAN_HLEN);
795 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
799 static int fe_poll_rx(struct napi_struct *napi, int budget,
800 struct fe_priv *priv, u32 rx_intr)
802 struct net_device *netdev = priv->netdev;
803 struct net_device_stats *stats = &netdev->stats;
804 struct fe_soc_data *soc = priv->soc;
805 struct fe_rx_ring *ring = &priv->rx_ring;
806 int idx = ring->rx_calc_idx;
810 struct fe_rx_dma *rxd, trxd;
812 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
814 if (netdev->features & NETIF_F_RXCSUM)
815 checksum_bit = soc->checksum_bit;
819 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
824 while (done < budget) {
827 idx = NEXT_RX_DESP_IDX(idx);
828 rxd = &ring->rx_dma[idx];
829 data = ring->rx_data[idx];
831 fe_get_rxd(&trxd, rxd);
832 if (!(trxd.rxd2 & RX_DMA_DONE))
835 /* alloc new buffer */
836 new_data = netdev_alloc_frag(ring->frag_size);
837 if (unlikely(!new_data)) {
841 dma_addr = dma_map_single(&netdev->dev,
842 new_data + NET_SKB_PAD + pad,
845 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
846 put_page(virt_to_head_page(new_data));
851 skb = build_skb(data, ring->frag_size);
852 if (unlikely(!skb)) {
853 put_page(virt_to_head_page(new_data));
856 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
858 dma_unmap_single(&netdev->dev, trxd.rxd1,
859 ring->rx_buf_size, DMA_FROM_DEVICE);
860 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
862 skb_put(skb, pktlen);
863 if (trxd.rxd4 & checksum_bit) {
864 skb->ip_summed = CHECKSUM_UNNECESSARY;
866 skb_checksum_none_assert(skb);
870 skb->protocol = eth_type_trans(skb, netdev);
873 stats->rx_bytes += pktlen;
875 napi_gro_receive(napi, skb);
877 ring->rx_data[idx] = new_data;
878 rxd->rxd1 = (unsigned int) dma_addr;
881 if (priv->flags & FE_FLAG_RX_SG_DMA)
882 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
884 rxd->rxd2 = RX_DMA_LSO;
886 ring->rx_calc_idx = idx;
888 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
893 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
898 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
901 struct net_device *netdev = priv->netdev;
902 struct device *dev = &netdev->dev;
903 unsigned int bytes_compl = 0;
905 struct fe_tx_buf *tx_buf;
908 struct fe_tx_ring *ring = &priv->tx_ring;
910 idx = ring->tx_free_idx;
911 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
913 while ((idx != hwidx) && budget) {
914 tx_buf = &ring->tx_buf[idx];
920 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
921 bytes_compl += skb->len;
925 fe_txd_unmap(dev, tx_buf);
926 idx = NEXT_TX_DESP_IDX(idx);
928 ring->tx_free_idx = idx;
931 /* read hw index again make sure no new tx packet */
932 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
934 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
941 netdev_completed_queue(netdev, done, bytes_compl);
943 if (unlikely(netif_queue_stopped(netdev) &&
944 (fe_empty_txd(ring) > ring->tx_thresh)))
945 netif_wake_queue(netdev);
951 static int fe_poll(struct napi_struct *napi, int budget)
953 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
954 struct fe_hw_stats *hwstat = priv->hw_stats;
955 int tx_done, rx_done, tx_again;
956 u32 status, fe_status, status_reg, mask;
957 u32 tx_intr, rx_intr, status_intr;
959 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
960 tx_intr = priv->soc->tx_int;
961 rx_intr = priv->soc->rx_int;
962 status_intr = priv->soc->status_int;
963 tx_done = rx_done = tx_again = 0;
965 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
966 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
967 status_reg = FE_REG_FE_INT_STATUS2;
969 status_reg = FE_REG_FE_INT_STATUS;
971 if (status & tx_intr)
972 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
974 if (status & rx_intr)
975 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
977 if (unlikely(fe_status & status_intr)) {
978 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
979 fe_stats_update(priv);
980 spin_unlock(&hwstat->stats_lock);
982 fe_reg_w32(status_intr, status_reg);
985 if (unlikely(netif_msg_intr(priv))) {
986 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
987 netdev_info(priv->netdev,
988 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
989 tx_done, rx_done, status, mask);
992 if (!tx_again && (rx_done < budget)) {
993 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
994 if (status & (tx_intr | rx_intr)) {
995 /* let napi poll again */
1000 napi_complete(napi);
1001 fe_int_enable(tx_intr | rx_intr);
1008 static void fe_tx_timeout(struct net_device *dev)
1010 struct fe_priv *priv = netdev_priv(dev);
1011 struct fe_tx_ring *ring = &priv->tx_ring;
1013 priv->netdev->stats.tx_errors++;
1014 netif_err(priv, tx_err, dev,
1015 "transmit timed out\n");
1016 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1017 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1018 netif_info(priv, drv, dev, "tx_ring=%d, " \
1019 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1020 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1021 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1022 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1023 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1027 netif_info(priv, drv, dev, "rx_ring=%d, " \
1028 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1029 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1030 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1031 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1032 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1035 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1036 schedule_work(&priv->pending_work);
1039 static irqreturn_t fe_handle_irq(int irq, void *dev)
1041 struct fe_priv *priv = netdev_priv(dev);
1042 u32 status, int_mask;
1044 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1046 if (unlikely(!status))
1049 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1050 if (likely(status & int_mask)) {
1051 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1052 fe_int_disable(int_mask);
1053 __napi_schedule(&priv->rx_napi);
1056 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1062 #ifdef CONFIG_NET_POLL_CONTROLLER
1063 static void fe_poll_controller(struct net_device *dev)
1065 struct fe_priv *priv = netdev_priv(dev);
1066 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1068 fe_int_disable(int_mask);
1069 fe_handle_irq(dev->irq, dev);
1070 fe_int_enable(int_mask);
1074 int fe_set_clock_cycle(struct fe_priv *priv)
1076 unsigned long sysclk = priv->sysclk;
1082 sysclk /= FE_US_CYC_CNT_DIVISOR;
1083 sysclk <<= FE_US_CYC_CNT_SHIFT;
1085 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1086 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1092 void fe_fwd_config(struct fe_priv *priv)
1096 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1098 /* disable jumbo frame */
1099 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1100 fwd_cfg &= ~FE_GDM1_JMB_EN;
1102 /* set unicast/multicast/broadcast frame to cpu */
1105 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1108 static void fe_rxcsum_config(bool enable)
1111 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1112 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1115 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1116 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1120 static void fe_txcsum_config(bool enable)
1123 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1124 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1127 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1128 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1132 void fe_csum_config(struct fe_priv *priv)
1134 struct net_device *dev = priv_netdev(priv);
1136 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1137 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1140 static int fe_hw_init(struct net_device *dev)
1142 struct fe_priv *priv = netdev_priv(dev);
1145 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1146 dev_name(priv->device), dev);
1150 if (priv->soc->set_mac)
1151 priv->soc->set_mac(priv, dev->dev_addr);
1153 fe_hw_set_macaddr(priv, dev->dev_addr);
1155 /* disable delay interrupt */
1156 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1158 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1160 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1161 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1162 for (i = 0; i < 16; i += 2)
1163 fe_w32(((i + 1) << 16) + i,
1164 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1167 BUG_ON(!priv->soc->fwd_config);
1168 if (priv->soc->fwd_config(priv))
1169 netdev_err(dev, "unable to get clock\n");
1171 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1172 fe_reg_w32(1, FE_REG_FE_RST_GL);
1173 fe_reg_w32(0, FE_REG_FE_RST_GL);
1179 static int fe_open(struct net_device *dev)
1181 struct fe_priv *priv = netdev_priv(dev);
1182 unsigned long flags;
1186 err = fe_init_dma(priv);
1190 spin_lock_irqsave(&priv->page_lock, flags);
1192 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1193 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1194 val |= FE_RX_2B_OFFSET;
1195 val |= priv->soc->pdma_glo_cfg;
1196 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1198 spin_unlock_irqrestore(&priv->page_lock, flags);
1201 priv->phy->start(priv);
1203 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1204 netif_carrier_on(dev);
1206 napi_enable(&priv->rx_napi);
1207 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1208 netif_start_queue(dev);
1217 static int fe_stop(struct net_device *dev)
1219 struct fe_priv *priv = netdev_priv(dev);
1220 unsigned long flags;
1223 netif_tx_disable(dev);
1224 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1225 napi_disable(&priv->rx_napi);
1228 priv->phy->stop(priv);
1230 spin_lock_irqsave(&priv->page_lock, flags);
1232 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1233 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1234 FE_REG_PDMA_GLO_CFG);
1235 spin_unlock_irqrestore(&priv->page_lock, flags);
1238 for (i = 0; i < 10; i++) {
1239 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1240 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1252 static int __init fe_init(struct net_device *dev)
1254 struct fe_priv *priv = netdev_priv(dev);
1255 struct device_node *port;
1258 BUG_ON(!priv->soc->reset_fe);
1259 priv->soc->reset_fe();
1261 if (priv->soc->switch_init)
1262 priv->soc->switch_init(priv);
1264 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1265 /*If the mac address is invalid, use random mac address */
1266 if (!is_valid_ether_addr(dev->dev_addr)) {
1267 random_ether_addr(dev->dev_addr);
1268 dev_err(priv->device, "generated random MAC address %pM\n",
1272 err = fe_mdio_init(priv);
1276 if (priv->soc->port_init)
1277 for_each_child_of_node(priv->device->of_node, port)
1278 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1279 priv->soc->port_init(priv, port);
1282 err = priv->phy->connect(priv);
1284 goto err_phy_disconnect;
1287 err = fe_hw_init(dev);
1289 goto err_phy_disconnect;
1291 if (priv->soc->switch_config)
1292 priv->soc->switch_config(priv);
1298 priv->phy->disconnect(priv);
1299 fe_mdio_cleanup(priv);
1304 static void fe_uninit(struct net_device *dev)
1306 struct fe_priv *priv = netdev_priv(dev);
1309 priv->phy->disconnect(priv);
1310 fe_mdio_cleanup(priv);
1312 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1313 free_irq(dev->irq, dev);
1316 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1318 struct fe_priv *priv = netdev_priv(dev);
1325 return phy_ethtool_ioctl(priv->phy_dev,
1326 (void *) ifr->ifr_data);
1330 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1338 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1340 struct fe_priv *priv = netdev_priv(dev);
1341 int frag_size, old_mtu;
1344 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1345 return eth_change_mtu(dev, new_mtu);
1347 frag_size = fe_max_frag_size(new_mtu);
1348 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1354 /* return early if the buffer sizes will not change */
1355 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1357 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1360 if (new_mtu <= ETH_DATA_LEN)
1361 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1363 priv->rx_ring.frag_size = PAGE_SIZE;
1364 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1366 if (!netif_running(dev))
1370 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1371 if (new_mtu <= ETH_DATA_LEN)
1372 fwd_cfg &= ~FE_GDM1_JMB_EN;
1374 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1375 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1376 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1378 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1380 return fe_open(dev);
1383 static const struct net_device_ops fe_netdev_ops = {
1384 .ndo_init = fe_init,
1385 .ndo_uninit = fe_uninit,
1386 .ndo_open = fe_open,
1387 .ndo_stop = fe_stop,
1388 .ndo_start_xmit = fe_start_xmit,
1389 .ndo_set_mac_address = fe_set_mac_address,
1390 .ndo_validate_addr = eth_validate_addr,
1391 .ndo_do_ioctl = fe_do_ioctl,
1392 .ndo_change_mtu = fe_change_mtu,
1393 .ndo_tx_timeout = fe_tx_timeout,
1394 .ndo_get_stats64 = fe_get_stats64,
1395 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1396 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1397 #ifdef CONFIG_NET_POLL_CONTROLLER
1398 .ndo_poll_controller = fe_poll_controller,
1402 static void fe_reset_pending(struct fe_priv *priv)
1404 struct net_device *dev = priv->netdev;
1417 netif_alert(priv, ifup, dev,
1418 "Driver up/down cycle failed, closing device.\n");
1423 static const struct fe_work_t fe_work[] = {
1424 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1427 static void fe_pending_work(struct work_struct *work)
1429 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1433 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1434 pending = test_and_clear_bit(fe_work[i].bitnr,
1435 priv->pending_flags);
1437 fe_work[i].action(priv);
1441 static int fe_probe(struct platform_device *pdev)
1443 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1444 const struct of_device_id *match;
1445 struct fe_soc_data *soc;
1446 struct net_device *netdev;
1447 struct fe_priv *priv;
1449 int err, napi_weight;
1451 device_reset(&pdev->dev);
1453 match = of_match_device(of_fe_match, &pdev->dev);
1454 soc = (struct fe_soc_data *) match->data;
1457 fe_reg_table = soc->reg_table;
1459 soc->reg_table = fe_reg_table;
1461 fe_base = devm_ioremap_resource(&pdev->dev, res);
1463 err = -EADDRNOTAVAIL;
1467 netdev = alloc_etherdev(sizeof(*priv));
1469 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1474 SET_NETDEV_DEV(netdev, &pdev->dev);
1475 netdev->netdev_ops = &fe_netdev_ops;
1476 netdev->base_addr = (unsigned long) fe_base;
1478 netdev->irq = platform_get_irq(pdev, 0);
1479 if (netdev->irq < 0) {
1480 dev_err(&pdev->dev, "no IRQ resource found\n");
1486 soc->init_data(soc, netdev);
1487 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1488 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1489 netdev->vlan_features = netdev->hw_features &
1490 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1491 netdev->features |= netdev->hw_features;
1493 /* fake rx vlan filter func. to support tx vlan offload func */
1494 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1495 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1497 priv = netdev_priv(netdev);
1498 spin_lock_init(&priv->page_lock);
1499 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1500 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1501 if (!priv->hw_stats) {
1505 spin_lock_init(&priv->hw_stats->stats_lock);
1508 sysclk = devm_clk_get(&pdev->dev, NULL);
1509 if (!IS_ERR(sysclk))
1510 priv->sysclk = clk_get_rate(sysclk);
1512 priv->netdev = netdev;
1513 priv->device = &pdev->dev;
1515 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1516 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1517 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1518 priv->tx_ring.tx_ring_size = priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1519 INIT_WORK(&priv->pending_work, fe_pending_work);
1522 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1524 priv->tx_ring.tx_ring_size *= 4;
1525 priv->rx_ring.rx_ring_size *= 4;
1527 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1528 fe_set_ethtool_ops(netdev);
1530 err = register_netdev(netdev);
1532 dev_err(&pdev->dev, "error bringing up device\n");
1536 platform_set_drvdata(pdev, netdev);
1538 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1539 netdev->base_addr, netdev->irq);
1544 free_netdev(netdev);
1546 devm_iounmap(&pdev->dev, fe_base);
1551 static int fe_remove(struct platform_device *pdev)
1553 struct net_device *dev = platform_get_drvdata(pdev);
1554 struct fe_priv *priv = netdev_priv(dev);
1556 netif_napi_del(&priv->rx_napi);
1558 kfree(priv->hw_stats);
1560 cancel_work_sync(&priv->pending_work);
1562 unregister_netdev(dev);
1564 platform_set_drvdata(pdev, NULL);
1569 static struct platform_driver fe_driver = {
1571 .remove = fe_remove,
1573 .name = "ralink_soc_eth",
1574 .owner = THIS_MODULE,
1575 .of_match_table = of_fe_match,
1579 static int __init init_rtfe(void)
1587 ret = platform_driver_register(&fe_driver);
1594 static void __exit exit_rtfe(void)
1596 platform_driver_unregister(&fe_driver);
1600 module_init(init_rtfe);
1601 module_exit(exit_rtfe);
1603 MODULE_LICENSE("GPL");
1604 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1605 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1606 MODULE_VERSION(FE_DRV_VERSION);