1 #include <linux/ioport.h>
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
24 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
27 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
29 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
31 #define RT305X_ESW_PVIDC_PVID_M 0xfff
32 #define RT305X_ESW_PVIDC_PVID_S 12
34 #define RT305X_ESW_VLANI_VID_M 0xfff
35 #define RT305X_ESW_VLANI_VID_S 12
37 #define RT305X_ESW_VMSC_MSC_M 0xff
38 #define RT305X_ESW_VMSC_MSC_S 8
40 #define RT305X_ESW_PORT0 0
41 #define RT305X_ESW_PORT1 1
42 #define RT305X_ESW_PORT2 2
43 #define RT305X_ESW_PORT3 3
44 #define RT305X_ESW_PORT4 4
45 #define RT305X_ESW_PORT5 5
46 #define RT305X_ESW_PORT6 6
50 struct rt305x_esw_platform_data *pdata;
51 spinlock_t reg_rw_lock;
55 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
57 __raw_writel(val, esw->base + reg);
61 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
63 return __raw_readl(esw->base + reg);
67 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
72 t = __raw_readl(esw->base + reg) & ~mask;
73 __raw_writel(t | val, esw->base + reg);
77 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
82 spin_lock_irqsave(&esw->reg_rw_lock, flags);
83 rt305x_esw_rmw_raw(esw, reg, mask, val);
84 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
88 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
91 unsigned long t_start = jiffies;
95 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
96 RT305X_ESW_PCR1_WT_DONE))
98 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
104 write_data &= 0xffff;
106 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
107 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
108 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
109 RT305X_ESW_REG_PCR0);
113 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
114 RT305X_ESW_PCR1_WT_DONE)
117 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
124 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
129 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
133 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
135 RT305X_ESW_REG_VLANI(vlan / 2),
136 RT305X_ESW_VLANI_VID_M << s,
137 (vid & RT305X_ESW_VLANI_VID_M) << s);
141 rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
145 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
147 RT305X_ESW_REG_PVIDC(port / 2),
148 RT305X_ESW_PVIDC_PVID_S << s,
149 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
153 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
157 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
159 RT305X_ESW_REG_VMSC(vlan / 4),
160 RT305X_ESW_VMSC_MSC_M << s,
161 (msc & RT305X_ESW_VMSC_MSC_M) << s);
165 rt305x_esw_hw_init(struct rt305x_esw *esw)
169 /* vodoo from original driver */
170 rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
171 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
172 rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
173 rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
174 rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
175 rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
176 rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
177 rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
178 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
179 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1);
180 rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
181 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
183 rt305x_mii_write(esw, 0, 31, 0x8000);
184 for (i = 0; i < 5; i++) {
185 /* TX10 waveform coefficient */
186 rt305x_mii_write(esw, i, 0, 0x3100);
187 /* TX10 waveform coefficient */
188 rt305x_mii_write(esw, i, 26, 0x1601);
189 /* TX100/TX10 AD/DA current bias */
190 rt305x_mii_write(esw, i, 29, 0x7058);
191 /* TX100 slew rate control */
192 rt305x_mii_write(esw, i, 30, 0x0018);
196 /* select global register */
197 rt305x_mii_write(esw, 0, 31, 0x0);
198 /* tune TP_IDL tail and head waveform */
199 rt305x_mii_write(esw, 0, 22, 0x052f);
200 /* set TX10 signal amplitude threshold to minimum */
201 rt305x_mii_write(esw, 0, 17, 0x0fe0);
202 /* set squelch amplitude to higher threshold */
203 rt305x_mii_write(esw, 0, 18, 0x40ba);
204 /* longer TP_IDL tail length */
205 rt305x_mii_write(esw, 0, 14, 0x65);
206 /* select local register */
207 rt305x_mii_write(esw, 0, 31, 0x8000);
209 /* set default vlan */
210 rt305x_esw_set_vlan_id(esw, 0, 1);
211 rt305x_esw_set_vlan_id(esw, 1, 2);
212 rt305x_esw_set_vmsc(esw, 0,
213 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
214 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
215 BIT(RT305X_ESW_PORT6)));
216 rt305x_esw_set_vmsc(esw, 1,
217 (BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
218 rt305x_esw_set_vmsc(esw, 2, 0);
219 rt305x_esw_set_vmsc(esw, 3, 0);
223 rt305x_esw_probe(struct platform_device *pdev)
225 struct rt305x_esw_platform_data *pdata;
226 struct rt305x_esw *esw;
227 struct resource *res;
230 pdata = pdev->dev.platform_data;
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
236 dev_err(&pdev->dev, "no memory resource found\n");
240 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
242 dev_err(&pdev->dev, "no memory for private data\n");
246 esw->base = ioremap(res->start, resource_size(res));
248 dev_err(&pdev->dev, "ioremap failed\n");
253 platform_set_drvdata(pdev, esw);
256 spin_lock_init(&esw->reg_rw_lock);
257 rt305x_esw_hw_init(esw);
267 rt305x_esw_remove(struct platform_device *pdev)
269 struct rt305x_esw *esw;
271 esw = platform_get_drvdata(pdev);
273 platform_set_drvdata(pdev, NULL);
281 static struct platform_driver rt305x_esw_driver = {
282 .probe = rt305x_esw_probe,
283 .remove = rt305x_esw_remove,
285 .name = "rt305x-esw",
286 .owner = THIS_MODULE,
291 rt305x_esw_init(void)
293 return platform_driver_register(&rt305x_esw_driver);
297 rt305x_esw_exit(void)
299 platform_driver_unregister(&rt305x_esw_driver);