1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
4 * $Date: 2008-11-21 05:39:15 $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
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18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
36 * The Core Interface Layer provides basic services for accessing and
37 * managing the DWC_otg hardware. These services are used by both the
38 * Host Controller Driver and the Peripheral Controller Driver.
40 * This file contains the Common Interrupt handlers.
42 #include "linux/dwc_otg_plat.h"
43 #include "dwc_otg_regs.h"
44 #include "dwc_otg_cil.h"
47 inline const char *op_state_str(dwc_otg_core_if_t *core_if)
49 return (core_if->op_state==A_HOST?"a_host":
50 (core_if->op_state==A_SUSPEND?"a_suspend":
51 (core_if->op_state==A_PERIPHERAL?"a_peripheral":
52 (core_if->op_state==B_PERIPHERAL?"b_peripheral":
53 (core_if->op_state==B_HOST?"b_host":
58 /** This function will log a debug message
60 * @param core_if Programming view of DWC_otg controller.
62 int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
64 gintsts_data_t gintsts;
65 DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
66 dwc_otg_mode(core_if) ? "Host" : "Device");
70 gintsts.b.modemismatch = 1;
71 dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
75 /** Start the HCD. Helper function for using the HCD callbacks.
77 * @param core_if Programming view of DWC_otg controller.
79 static inline void hcd_start(dwc_otg_core_if_t *core_if)
81 if (core_if->hcd_cb && core_if->hcd_cb->start) {
82 core_if->hcd_cb->start(core_if->hcd_cb->p);
85 /** Stop the HCD. Helper function for using the HCD callbacks.
87 * @param core_if Programming view of DWC_otg controller.
89 static inline void hcd_stop(dwc_otg_core_if_t *core_if)
91 if (core_if->hcd_cb && core_if->hcd_cb->stop) {
92 core_if->hcd_cb->stop(core_if->hcd_cb->p);
95 /** Disconnect the HCD. Helper function for using the HCD callbacks.
97 * @param core_if Programming view of DWC_otg controller.
99 static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
101 if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
102 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
105 /** Inform the HCD the a New Session has begun. Helper function for
106 * using the HCD callbacks.
108 * @param core_if Programming view of DWC_otg controller.
110 static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
112 if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
113 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
117 /** Start the PCD. Helper function for using the PCD callbacks.
119 * @param core_if Programming view of DWC_otg controller.
121 static inline void pcd_start(dwc_otg_core_if_t *core_if)
123 if (core_if->pcd_cb && core_if->pcd_cb->start) {
124 core_if->pcd_cb->start(core_if->pcd_cb->p);
127 /** Stop the PCD. Helper function for using the PCD callbacks.
129 * @param core_if Programming view of DWC_otg controller.
131 static inline void pcd_stop(dwc_otg_core_if_t *core_if)
133 if (core_if->pcd_cb && core_if->pcd_cb->stop) {
134 core_if->pcd_cb->stop(core_if->pcd_cb->p);
137 /** Suspend the PCD. Helper function for using the PCD callbacks.
139 * @param core_if Programming view of DWC_otg controller.
141 static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
143 if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
144 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
147 /** Resume the PCD. Helper function for using the PCD callbacks.
149 * @param core_if Programming view of DWC_otg controller.
151 static inline void pcd_resume(dwc_otg_core_if_t *core_if)
153 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
154 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
159 * This function handles the OTG Interrupts. It reads the OTG
160 * Interrupt Register (GOTGINT) to determine what interrupt has
163 * @param core_if Programming view of DWC_otg controller.
165 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
167 dwc_otg_core_global_regs_t *global_regs =
168 core_if->core_global_regs;
169 gotgint_data_t gotgint;
170 gotgctl_data_t gotgctl;
171 gintmsk_data_t gintmsk;
173 gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
174 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
175 DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
177 if (gotgint.b.sesenddet) {
178 DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: "
179 "Session End Detected++ (%s)\n",
180 op_state_str(core_if));
181 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
183 if (core_if->op_state == B_HOST) {
185 core_if->op_state = B_PERIPHERAL;
187 /* If not B_HOST and Device HNP still set. HNP
189 if (gotgctl.b.devhnpen) {
190 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
191 DWC_ERROR("Device Not Connected/Responding!\n");
194 /* If Session End Detected the B-Cable has
195 * been disconnected. */
196 /* Reset PCD and Gadget driver to a
201 gotgctl.b.devhnpen = 1;
202 dwc_modify_reg32(&global_regs->gotgctl,
205 if (gotgint.b.sesreqsucstschng) {
206 DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: "
207 "Session Reqeust Success Status Change++\n");
208 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
209 if (gotgctl.b.sesreqscs) {
210 if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
211 (core_if->core_params->i2c_enable)) {
212 core_if->srp_success = 1;
216 /* Clear Session Request */
218 gotgctl.b.sesreq = 1;
219 dwc_modify_reg32(&global_regs->gotgctl,
224 if (gotgint.b.hstnegsucstschng) {
225 /* Print statements during the HNP interrupt handling
226 * can cause it to fail.*/
227 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
228 if (gotgctl.b.hstnegscs) {
229 if (dwc_otg_is_host_mode(core_if)) {
230 core_if->op_state = B_HOST;
232 * Need to disable SOF interrupt immediately.
233 * When switching from device to host, the PCD
234 * interrupt handler won't handle the
235 * interrupt if host mode is already set. The
236 * HCD interrupt handler won't get called if
237 * the HCD state is HALT. This means that the
238 * interrupt does not get handled and Linux
242 gintmsk.b.sofintr = 1;
243 dwc_modify_reg32(&global_regs->gintmsk,
247 * Initialize the Core for Host mode.
250 core_if->op_state = B_HOST;
254 gotgctl.b.hnpreq = 1;
255 gotgctl.b.devhnpen = 1;
256 dwc_modify_reg32(&global_regs->gotgctl,
258 DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
259 DWC_ERROR("Device Not Connected/Responding\n");
262 if (gotgint.b.hstnegdet) {
263 /* The disconnect interrupt is set at the same time as
264 * Host Negotiation Detected. During the mode
265 * switch all interrupts are cleared so the disconnect
266 * interrupt handler will not get executed.
268 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
269 "Host Negotiation Detected++ (%s)\n",
270 (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
271 if (dwc_otg_is_device_mode(core_if)){
272 DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
273 hcd_disconnect(core_if);
275 core_if->op_state = A_PERIPHERAL;
278 * Need to disable SOF interrupt immediately. When
279 * switching from device to host, the PCD interrupt
280 * handler won't handle the interrupt if host mode is
281 * already set. The HCD interrupt handler won't get
282 * called if the HCD state is HALT. This means that
283 * the interrupt does not get handled and Linux
287 gintmsk.b.sofintr = 1;
288 dwc_modify_reg32(&global_regs->gintmsk,
292 core_if->op_state = A_HOST;
295 if (gotgint.b.adevtoutchng) {
296 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
297 "A-Device Timeout Change++\n");
299 if (gotgint.b.debdone) {
300 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
301 "Debounce Done++\n");
305 dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
311 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
313 void w_conn_id_status_change(void *p)
315 dwc_otg_core_if_t *core_if = p;
319 void w_conn_id_status_change(struct work_struct *p)
321 dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
327 gotgctl_data_t gotgctl = { .d32 = 0 };
329 gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
330 DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
331 DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
333 /* B-Device connector (Device Mode) */
334 if (gotgctl.b.conidsts) {
335 /* Wait for switch to device mode. */
336 while (!dwc_otg_is_device_mode(core_if)){
337 DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
338 (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
340 if (++count > 10000) *(uint32_t*)NULL=0;
342 core_if->op_state = B_PERIPHERAL;
343 dwc_otg_core_init(core_if);
344 dwc_otg_enable_global_interrupts(core_if);
347 /* A-Device connector (Host Mode) */
348 while (!dwc_otg_is_host_mode(core_if)) {
349 DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
350 (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
352 if (++count > 10000) *(uint32_t*)NULL=0;
354 core_if->op_state = A_HOST;
356 * Initialize the Core for Host mode.
358 dwc_otg_core_init(core_if);
359 dwc_otg_enable_global_interrupts(core_if);
366 * This function handles the Connector ID Status Change Interrupt. It
367 * reads the OTG Interrupt Register (GOTCTL) to determine whether this
368 * is a Device to Host Mode transition or a Host Mode to Device
371 * This only occurs when the cable is connected/removed from the PHY
374 * @param core_if Programming view of DWC_otg controller.
376 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
380 * Need to disable SOF interrupt immediately. If switching from device
381 * to host, the PCD interrupt handler won't handle the interrupt if
382 * host mode is already set. The HCD interrupt handler won't get
383 * called if the HCD state is HALT. This means that the interrupt does
384 * not get handled and Linux complains loudly.
386 gintmsk_data_t gintmsk = { .d32 = 0 };
387 gintsts_data_t gintsts = { .d32 = 0 };
389 gintmsk.b.sofintr = 1;
390 dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
392 DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
393 (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
396 * Need to schedule a work, as there are possible DELAY function calls
398 queue_work(core_if->wq_otg, &core_if->w_conn_id);
400 /* Set flag and clear interrupt */
401 gintsts.b.conidstschng = 1;
402 dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
408 * This interrupt indicates that a device is initiating the Session
409 * Request Protocol to request the host to turn on bus power so a new
410 * session can begin. The handler responds by turning on bus power. If
411 * the DWC_otg controller is in low power mode, the handler brings the
412 * controller out of low power mode before turning on bus power.
414 * @param core_if Programming view of DWC_otg controller.
416 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
418 gintsts_data_t gintsts;
420 #ifndef DWC_HOST_ONLY
422 DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
424 if (dwc_otg_is_device_mode(core_if)) {
425 DWC_PRINT("SRP: Device mode\n");
427 DWC_PRINT("SRP: Host mode\n");
429 /* Turn on the port power bit. */
430 hprt0.d32 = dwc_otg_read_hprt0(core_if);
432 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
434 /* Start the Connection timer. So a message can be displayed
435 * if connect does not occur within 10 seconds. */
436 hcd_session_start(core_if);
440 /* Clear interrupt */
442 gintsts.b.sessreqintr = 1;
443 dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
449 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
450 void w_wakeup_detected(void *p)
452 dwc_otg_core_if_t* core_if = p;
456 void w_wakeup_detected(struct work_struct *p)
458 struct delayed_work *dw = container_of(p, struct delayed_work, work);
459 dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
463 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
464 * so that OPT tests pass with all PHYs).
466 hprt0_data_t hprt0 = {.d32=0};
468 pcgcctl_data_t pcgcctl = {.d32=0};
469 /* Restart the Phy Clock */
470 pcgcctl.b.stoppclk = 1;
471 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
474 hprt0.d32 = dwc_otg_read_hprt0(core_if);
475 DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
477 hprt0.b.prtres = 0; /* Resume */
478 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
479 DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
482 * This interrupt indicates that the DWC_otg controller has detected a
483 * resume or remote wakeup sequence. If the DWC_otg controller is in
484 * low power mode, the handler must brings the controller out of low
485 * power mode. The controller automatically begins resume
486 * signaling. The handler schedules a time to stop resume signaling.
488 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
490 gintsts_data_t gintsts;
492 DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
494 if (dwc_otg_is_device_mode(core_if)) {
495 dctl_data_t dctl = {.d32=0};
496 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
497 dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
498 #ifdef PARTIAL_POWER_DOWN
499 if (core_if->hwcfg4.b.power_optimiz) {
500 pcgcctl_data_t power = {.d32=0};
502 power.d32 = dwc_read_reg32(core_if->pcgcctl);
503 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
505 power.b.stoppclk = 0;
506 dwc_write_reg32(core_if->pcgcctl, power.d32);
509 dwc_write_reg32(core_if->pcgcctl, power.d32);
511 power.b.rstpdwnmodule = 0;
512 dwc_write_reg32(core_if->pcgcctl, power.d32);
515 /* Clear the Remote Wakeup Signalling */
516 dctl.b.rmtwkupsig = 1;
517 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
520 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
521 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
525 pcgcctl_data_t pcgcctl = {.d32=0};
527 /* Restart the Phy Clock */
528 pcgcctl.b.stoppclk = 1;
529 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
531 queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
534 /* Clear interrupt */
536 gintsts.b.wkupintr = 1;
537 dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
543 * This interrupt indicates that a device has been disconnected from
546 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
548 gintsts_data_t gintsts;
550 DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
551 (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
552 op_state_str(core_if));
554 /** @todo Consolidate this if statement. */
555 #ifndef DWC_HOST_ONLY
556 if (core_if->op_state == B_HOST) {
557 /* If in device mode Disconnect and stop the HCD, then
559 hcd_disconnect(core_if);
561 core_if->op_state = B_PERIPHERAL;
562 } else if (dwc_otg_is_device_mode(core_if)) {
563 gotgctl_data_t gotgctl = { .d32 = 0 };
564 gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
565 if (gotgctl.b.hstsethnpen==1) {
566 /* Do nothing, if HNP in process the OTG
567 * interrupt "Host Negotiation Detected"
568 * interrupt will do the mode switch.
570 } else if (gotgctl.b.devhnpen == 0) {
571 /* If in device mode Disconnect and stop the HCD, then
573 hcd_disconnect(core_if);
575 core_if->op_state = B_PERIPHERAL;
577 DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
580 if (core_if->op_state == A_HOST) {
581 /* A-Cable still connected but device disconnected. */
582 hcd_disconnect(core_if);
588 gintsts.b.disconnect = 1;
589 dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
593 * This interrupt indicates that SUSPEND state has been detected on
596 * For HNP the USB Suspend interrupt signals the change from
597 * "a_peripheral" to "a_host".
599 * When power management is enabled the core will be put in low power
602 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
605 gintsts_data_t gintsts;
607 DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
609 if (dwc_otg_is_device_mode(core_if)) {
610 /* Check the Device status register to determine if the Suspend
611 * state is active. */
612 dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
613 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
614 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
615 "HWCFG4.power Optimize=%d\n",
616 dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
619 #ifdef PARTIAL_POWER_DOWN
620 /** @todo Add a module parameter for power management. */
622 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
623 pcgcctl_data_t power = {.d32=0};
624 DWC_DEBUGPL(DBG_CIL, "suspend\n");
627 dwc_write_reg32(core_if->pcgcctl, power.d32);
629 power.b.rstpdwnmodule = 1;
630 dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
632 power.b.stoppclk = 1;
633 dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
636 DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
639 /* PCD callback for suspend. */
640 pcd_suspend(core_if);
642 if (core_if->op_state == A_PERIPHERAL) {
643 DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
644 /* Clear the a_peripheral flag, back to a_host. */
647 core_if->op_state = A_HOST;
651 /* Clear interrupt */
653 gintsts.b.usbsuspend = 1;
654 dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
661 * This function returns the Core Interrupt register.
663 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
665 gintsts_data_t gintsts;
666 gintmsk_data_t gintmsk;
667 gintmsk_data_t gintmsk_common = {.d32=0};
668 gintmsk_common.b.wkupintr = 1;
669 gintmsk_common.b.sessreqintr = 1;
670 gintmsk_common.b.conidstschng = 1;
671 gintmsk_common.b.otgintr = 1;
672 gintmsk_common.b.modemismatch = 1;
673 gintmsk_common.b.disconnect = 1;
674 gintmsk_common.b.usbsuspend = 1;
675 /** @todo: The port interrupt occurs while in device
676 * mode. Added code to CIL to clear the interrupt for now!
678 gintmsk_common.b.portintr = 1;
680 gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
681 gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
683 /* if any common interrupts set */
684 if (gintsts.d32 & gintmsk_common.d32) {
685 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
686 gintsts.d32, gintmsk.d32);
690 return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
695 * Common interrupt handler.
697 * The common interrupts are those that occur in both Host and Device mode.
698 * This handler handles the following interrupts:
699 * - Mode Mismatch Interrupt
700 * - Disconnect Interrupt
702 * - Connector ID Status Change Interrupt
703 * - Session Request Interrupt.
704 * - Resume / Remote Wakeup Detected Interrupt.
707 int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
710 gintsts_data_t gintsts;
712 gintsts.d32 = dwc_otg_read_common_intr(core_if);
714 if (gintsts.b.modemismatch) {
715 retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
717 if (gintsts.b.otgintr) {
718 retval |= dwc_otg_handle_otg_intr(core_if);
720 if (gintsts.b.conidstschng) {
721 retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
723 if (gintsts.b.disconnect) {
724 retval |= dwc_otg_handle_disconnect_intr(core_if);
726 if (gintsts.b.sessreqintr) {
727 retval |= dwc_otg_handle_session_req_intr(core_if);
729 if (gintsts.b.wkupintr) {
730 retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
732 if (gintsts.b.usbsuspend) {
733 retval |= dwc_otg_handle_usb_suspend_intr(core_if);
735 if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
736 /* The port interrupt occurs while in device mode with HPRT0
737 * Port Enable/Disable.
740 gintsts.b.portintr = 1;
741 dwc_write_reg32(&core_if->core_global_regs->gintsts,
747 S3C2410X_CLEAR_EINTPEND();